instruction known as Fetch and Execute (or Wait). Compare the single instruction illustration above with the

multi-instruction pipeline flow below— the instruction above appears in the next illustration with the prefix "a" while

others use prefixes "b", "c", etc. This seven-cycle slice of time is processing six contiguous instructions.

Instruction Pipeline Flow

As the pipeline fills (or is full, as shown here) instructions overlap in time by three stages. Each cycle of the instruction pipeline

simultaneously processes different stages of two or three contiguous instructions. Here, instruction a is read (in the first

cycle) at the same moment its two previous instructions (yand z) write results and latch for later ALU operation, respectively.

additional cycles ahead of the instruction's execute stage. These extra cycles align the target instruction's

MUX-update to the delayed resource's moment-of-result while performing no operation in any other instruction.

When the resource is ready, processing continues again for all instructions in the pipeline. For example, if

instruction a needs to wait 2 extra cycles to execute properly, the pipeline flow (above) would be stretched starting

at cycle 4; appearing like this:

Pipeline Stall

static operations (such as JMP or CALL) or among many dynamic operations (such as a conditionally-executed

JMP or CALL, or a modify/test-and-branch instruction like DJZ or TJNZ). When processing a branch instruction,

one of two things will happen.