MC9S08 PL4 Reference Manual
Supports: MC9S08PL4
Document Number: MC9S08PL4RM
Rev. 4, 08/2019
MC9S08 PL4 Reference Manual, Rev. 4, 08/2019
2 NXP Semiconductors
Contents
Section number Title Page
Chapter 1
Device Overview
1.1 Introduction.....................................................................................................................................................................23
1.2 MCU block diagram....................................................................................................................................................... 24
1.3 System clock distribution................................................................................................................................................25
Chapter 2
Pins and connections
2.1 Device pin assignment.................................................................................................................................................... 29
2.2 Pin functions................................................................................................................................................................... 30
2.2.1 Power (VDD, VSS)..........................................................................................................................................30
2.2.2 Oscillator (XTAL, EXTAL)............................................................................................................................ 31
2.2.3 External reset pin (RESET) and interrupt pin (IRQ)....................................................................................... 32
2.2.4 Background/mode select (BKGD/MS)............................................................................................................ 33
2.2.5 Port A input/output (I/O) pins (PTA5–PTA0)................................................................................................. 34
2.2.6 Port B input/output (I/O) pins (PTB7–PTB0)..................................................................................................34
2.2.7 Port C input/output (I/O) pins (PTC3–PTC0)..................................................................................................34
2.2.8 True open drain pins (PTB0)........................................................................................................................... 34
2.3 Peripheral pinouts........................................................................................................................................................... 34
Chapter 3
Power management
3.1 Introduction.....................................................................................................................................................................37
3.2 Features...........................................................................................................................................................................37
3.2.1 Run mode......................................................................................................................................................... 37
3.2.2 Wait mode........................................................................................................................................................38
3.2.3 Stop3 mode...................................................................................................................................................... 38
3.2.4 Active BDM enabled in stop3 mode................................................................................................................38
3.2.5 LVD enabled in stop mode.............................................................................................................................. 39
3.2.6 Power modes behaviors................................................................................................................................... 39
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3.3 Low voltage detect (LVD) system..................................................................................................................................40
3.3.1 Power-on reset (POR) operation......................................................................................................................41
3.3.2 LVD reset operation.........................................................................................................................................41
3.3.3 Low-voltage warning (LVW).......................................................................................................................... 41
3.4 Bandgap reference.......................................................................................................................................................... 42
3.5 Power management control bits and registers................................................................................................................ 42
3.5.1 System Power Management Status and Control 1 Register (PMC_SPMSC1)................................................42
3.5.2 System Power Management Status and Control 2 Register (PMC_SPMSC2)................................................44
Chapter 4
Memory map
4.1 Memory map...................................................................................................................................................................45
4.2 Reset and interrupt vector assignments...........................................................................................................................46
4.3 Register addresses and bit assignments.......................................................................................................................... 47
4.4 Random-access memory (RAM).................................................................................................................................... 54
4.5 Flash and EEPROM........................................................................................................................................................55
4.5.1 Overview..........................................................................................................................................................55
4.5.2 Function descriptions....................................................................................................................................... 57
4.5.2.1 Modes of operation.......................................................................................................................... 57
4.5.2.2 Flash and EEPROM memory map...................................................................................................57
4.5.2.3 Flash and EEPROM initialization after system reset.......................................................................58
4.5.2.4 Flash and EEPROM command operations.......................................................................................58
4.5.2.5 Flash and EEPROM interrupts.........................................................................................................63
4.5.2.6 Protection......................................................................................................................................... 64
4.5.2.7 Security............................................................................................................................................ 67
4.5.2.8 Flash and EEPROM commands.......................................................................................................69
4.5.2.9 Flash and EEPROM command summary........................................................................................ 71
4.6 Flash and EEPROM registers descriptions.....................................................................................................................85
4.6.1 Flash Clock Divider Register (NVM_FCLKDIV)...........................................................................................85
4.6.2 Flash Security Register (NVM_FSEC)............................................................................................................86
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4.6.3 Flash CCOB Index Register (NVM_FCCOBIX)............................................................................................ 87
4.6.4 Flash Configuration Register (NVM_FCNFG)............................................................................................... 87
4.6.5 Flash Error Configuration Register (NVM_FERCNFG).................................................................................88
4.6.6 Flash Status Register (NVM_FSTAT).............................................................................................................89
4.6.7 Flash Error Status Register (NVM_FERSTAT).............................................................................................. 90
4.6.8 Flash Protection Register (NVM_FPROT)......................................................................................................91
4.6.9 EEPROM Protection Register (NVM_EEPROT)............................................................................................92
4.6.10 Flash Common Command Object Register:High (NVM_FCCOBHI)............................................................93
4.6.11 Flash Common Command Object Register: Low (NVM_FCCOBLO)...........................................................94
4.6.12 Flash Option Register (NVM_FOPT)..............................................................................................................94
Chapter 5
Interrupt
5.1 Interrupts.........................................................................................................................................................................97
5.1.1 Interrupt stack frame........................................................................................................................................ 98
5.1.2 Interrupt vectors, sources, and local masks......................................................................................................99
5.1.3 Hardware nested interrupt................................................................................................................................101
5.1.3.1 Interrupt priority level register.........................................................................................................103
5.1.3.2 Interrupt priority level comparator set............................................................................................. 104
5.1.3.3 Interrupt priority mask update and restore mechanism....................................................................104
5.1.3.4 Integration and application of the IPC............................................................................................. 105
5.2 IRQ..................................................................................................................................................................................105
5.2.1 Features............................................................................................................................................................ 106
5.2.1.1 Pin configuration options.................................................................................................................106
5.2.1.2 Edge and level sensitivity................................................................................................................ 107
5.3 Interrupt pin request register...........................................................................................................................................107
5.3.1 Interrupt Pin Request Status and Control Register (IRQ_SC).........................................................................108
5.4 Interrupt priority control register.................................................................................................................................... 109
5.4.1 IPC Status and Control Register (IPC_SC)......................................................................................................110
5.4.2 Interrupt Priority Mask Pseudo Stack Register (IPC_IPMPS)........................................................................ 111
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5.4.3
Interrupt Level Setting Registers n (IPC_ILRSn)............................................................................................111
Chapter 6
System control
6.1 System device identification (SDID)..............................................................................................................................113
6.2 Universally unique identification (UUID)......................................................................................................................113
6.3 Reset and system initialization........................................................................................................................................113
6.4 System options................................................................................................................................................................114
6.4.1 BKGD pin enable.............................................................................................................................................114
6.4.2 RESET pin enable............................................................................................................................................114
6.4.3 SCI0 pin reassignment..................................................................................................................................... 114
6.4.4 FTM0 channels pin reassignment.................................................................................................................... 115
6.4.5 FTM1 pin reassignment................................................................................................................................... 115
6.5 System interconnection...................................................................................................................................................115
6.5.1 ACMP output selection....................................................................................................................................115
6.5.2 SCI0 TxD modulation......................................................................................................................................115
6.5.3 SCI0 RxD capture............................................................................................................................................ 116
6.5.4 SCI0 RxD filter................................................................................................................................................ 116
6.5.5 RTC capture..................................................................................................................................................... 117
6.5.6 ADC hardware trigger......................................................................................................................................117
6.6 System Control Registers................................................................................................................................................118
6.6.1 System Reset Status Register (SYS_SRS).......................................................................................................118
6.6.2 System Background Debug Force Reset Register (SYS_SBDFR)..................................................................120
6.6.3 System Device Identification Register: High (SYS_SDIDH)......................................................................... 121
6.6.4 System Device Identification Register: Low (SYS_SDIDL).......................................................................... 121
6.6.5 System Options Register 1 (SYS_SOPT1)...................................................................................................... 122
6.6.6 System Options Register 2 (SYS_SOPT2)...................................................................................................... 123
6.6.7 System Options Register 3 (SYS_SOPT3)...................................................................................................... 124
6.6.8 Illegal Address Register: High (SYS_ILLAH)................................................................................................125
6.6.9 Illegal Address Register: Low (SYS_ILLAL).................................................................................................126
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6.6.10 Universally Unique Identifier Register 1 (SYS_UUID1)................................................................................126
6.6.11 Universally Unique Identifier Register 2 (SYS_UUID2)................................................................................127
6.6.12 Universally Unique Identifier Register 3 (SYS_UUID3)................................................................................127
6.6.13 Universally Unique Identifier Register 4 (SYS_UUID4)................................................................................128
6.6.14 Universally Unique Identifier Register 5 (SYS_UUID5)................................................................................128
6.6.15 Universally Unique Identifier Register 6 (SYS_UUID6)................................................................................129
6.6.16 Universally Unique Identifier Register 7 (SYS_UUID7)................................................................................129
6.6.17 Universally Unique Identifier Register 8 (SYS_UUID8)................................................................................130
Chapter 7
Parallel input/output
7.1 Introduction.....................................................................................................................................................................131
7.2 Port data and data direction.............................................................................................................................................132
7.3 Internal pullup enable..................................................................................................................................................... 133
7.4 Input glitch filter setting..................................................................................................................................................133
7.5 Pin behavior in stop mode...............................................................................................................................................133
7.6 Port data registers............................................................................................................................................................134
7.6.1 Port A Data Register (PORT_PTAD)..............................................................................................................134
7.6.2 Port B Data Register (PORT_PTBD).............................................................................................................. 135
7.6.3 Port C Data Register (PORT_PTCD).............................................................................................................. 135
7.6.4 Port A Output Enable Register (PORT_PTAOE)............................................................................................136
7.6.5 Port B Output Enable Register (PORT_PTBOE)............................................................................................ 137
7.6.6 Port C Output Enable Register (PORT_PTCOE)............................................................................................ 138
7.6.7 Port A Input Enable Register (PORT_PTAIE)................................................................................................139
7.6.8 Port B Input Enable Register (PORT_PTBIE)................................................................................................ 140
7.6.9 Port C Input Enable Register (PORT_PTCIE)................................................................................................ 141
7.6.10 Port Filter Register 0 (PORT_IOFLT0)...........................................................................................................142
7.6.11 Port Filter Register 2 (PORT_IOFLT2)...........................................................................................................143
7.6.12 Port Clock Division Register (PORT_FCLKDIV).......................................................................................... 144
7.6.13 Port A Pullup Enable Register (PORT_PTAPE)............................................................................................. 145
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7.6.14 Port B Pullup Enable Register (PORT_PTBPE)..............................................................................................146
7.6.15 Port C Pullup Enable Register (PORT_PTCPE)..............................................................................................147
Chapter 8
Clock management
8.1 Clock module..................................................................................................................................................................149
8.2 Internal clock source (ICS)............................................................................................................................................. 149
8.2.1 Function description.........................................................................................................................................150
8.2.1.1 Bus frequency divider...................................................................................................................... 151
8.2.1.2 Low power bit usage........................................................................................................................151
8.2.1.3 Internal reference clock (ICSIRCLK)..............................................................................................151
8.2.1.4 Fixed frequency clock (ICSFFCLK)................................................................................................152
8.2.1.5 BDC clock........................................................................................................................................153
8.2.2 Modes of operation.......................................................................................................................................... 153
8.2.2.1 FLL engaged internal (FEI)............................................................................................................. 154
8.2.2.2 FLL engaged external (FEE)............................................................................................................155
8.2.2.3 FLL bypassed internal (FBI)............................................................................................................155
8.2.2.4 FLL bypassed internal low power (FBILP)..................................................................................... 155
8.2.2.5 FLL bypassed external (FBE)..........................................................................................................156
8.2.2.6 FLL bypassed external low power (FBELP)................................................................................... 156
8.2.2.7 Stop (STOP).....................................................................................................................................157
8.2.3 FLL lock and clock monitor.............................................................................................................................158
8.2.3.1 FLL clock lock.................................................................................................................................158
8.2.3.2 External reference clock monitor.....................................................................................................158
8.3 Initialization / application information........................................................................................................................... 158
8.3.1 Initializing FEI mode....................................................................................................................................... 159
8.3.2 Initializing FBI mode.......................................................................................................................................159
8.3.3 Initializing FEE mode...................................................................................................................................... 159
8.3.4 Initializing FBE mode......................................................................................................................................160
8.3.5 External oscillator (OSC).................................................................................................................................160
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8.3.5.1 Bypass mode.................................................................................................................................... 161
8.3.5.2 Low-power configuration................................................................................................................ 161
8.3.5.3 High-gain configuration...................................................................................................................162
8.3.5.4 Initializing external oscillator for peripherals..................................................................................162
8.4 1 kHz low-power oscillator (LPO)................................................................................................................................. 163
8.5 Peripheral clock gating................................................................................................................................................... 163
8.6 ICS control registers....................................................................................................................................................... 163
8.6.1 ICS Control Register 1 (ICS_C1).................................................................................................................... 164
8.6.2 ICS Control Register 2 (ICS_C2).................................................................................................................... 165
8.6.3 ICS Control Register 3 (ICS_C3).................................................................................................................... 166
8.6.4 ICS Control Register 4 (ICS_C4).................................................................................................................... 166
8.6.5 ICS Status Register (ICS_S)............................................................................................................................ 167
8.6.6 OSC Status and Control Register (ICS_OSCSC)............................................................................................ 168
8.7 System clock gating control registers............................................................................................................................. 169
8.7.1 System Clock Gating Control 1 Register (SCG_C1).......................................................................................170
8.7.2 System Clock Gating Control 2 Register (SCG_C2).......................................................................................171
8.7.3 System Clock Gating Control 3 Register (SCG_C3).......................................................................................172
8.7.4 System Clock Gating Control 4 Register (SCG_C4).......................................................................................172
Chapter 9
Chip configurations
9.1 Introduction.....................................................................................................................................................................175
9.2 Core modules.................................................................................................................................................................. 175
9.2.1 Central processor unit (CPU)...........................................................................................................................175
9.2.2 Debug module (DBG)......................................................................................................................................175
9.3 System modules.............................................................................................................................................................. 176
9.3.1 Watchdog (WDOG)......................................................................................................................................... 176
9.4 Clock module..................................................................................................................................................................176
9.5 Memory...........................................................................................................................................................................176
9.5.1 Random-access-memory (RAM)..................................................................................................................... 176
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9.5.2 Non-volatile memory (NVM).......................................................................................................................... 177
9.6 Power modules................................................................................................................................................................177
9.7 Timers............................................................................................................................................................................. 177
9.7.1 FlexTimer module (FTM)................................................................................................................................177
9.7.1.1 FTM0 interconnection......................................................................................................................178
9.7.1.2 FTM1 interconnection......................................................................................................................178
9.7.2 Real-time counter (RTC)................................................................................................................................. 178
9.8 Communication interfaces.............................................................................................................................................. 179
9.8.1 Serial communications interface (SCI)............................................................................................................179
9.8.1.1 SCI0 infrared functions....................................................................................................................179
9.9 Analog.............................................................................................................................................................................180
9.9.1 Analog-to-digital converter (ADC)..................................................................................................................180
9.9.1.1 ADC block diagram......................................................................................................................... 180
9.9.1.2 ADC channel assignments............................................................................................................... 181
9.9.1.3 Alternate clock................................................................................................................................. 182
9.9.1.4 Hardware trigger.............................................................................................................................. 183
9.9.1.5 Temperature sensor..........................................................................................................................183
9.9.2 Analog comparator (ACMP)............................................................................................................................184
9.9.2.1 ACMP configuration information....................................................................................................184
9.9.2.2 ACMP in stop3 mode.......................................................................................................................185
9.9.2.3 ACMP to FTM configuration information.......................................................................................185
9.9.2.4 ACMP for SCI0 RXD filter............................................................................................................. 185
9.10 Human-machine interfaces HMI.....................................................................................................................................186
9.10.1 Keyboard interrupts (KBI)...............................................................................................................................186
Chapter 10
Central processor unit
10.1 Introduction.....................................................................................................................................................................187
10.1.1 Features............................................................................................................................................................ 187
10.2 Programmer's Model and CPU Registers....................................................................................................................... 188
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10.2.1 Accumulator (A).............................................................................................................................................. 188
10.2.2 Index Register (H:X)........................................................................................................................................189
10.2.3 Stack Pointer (SP)............................................................................................................................................ 189
10.2.4 Program Counter (PC)..................................................................................................................................... 190
10.2.5 Condition Code Register (CCR)...................................................................................................................... 190
10.3 Addressing Modes.......................................................................................................................................................... 191
10.3.1 Inherent Addressing Mode (INH)....................................................................................................................192
10.3.2 Relative Addressing Mode (REL)....................................................................................................................192
10.3.3 Immediate Addressing Mode (IMM)...............................................................................................................192
10.3.4 Direct Addressing Mode (DIR)........................................................................................................................193
10.3.5 Extended Addressing Mode (EXT)..................................................................................................................193
10.3.6 Indexed Addressing Mode............................................................................................................................... 194
10.3.6.1 Indexed, No Offset (IX)...................................................................................................................194
10.3.6.2 Indexed, No Offset with Post Increment (IX+)................................................................................194
10.3.6.3 Indexed, 8-Bit Offset (IX1)..............................................................................................................194
10.3.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+).......................................................................... 195
10.3.6.5 Indexed, 16-Bit Offset (IX2)............................................................................................................195
10.3.6.6 SP-Relative, 8-Bit Offset (SP1)....................................................................................................... 195
10.3.6.7 SP-Relative, 16-Bit Offset (SP2)..................................................................................................... 196
10.3.7 Memory to memory Addressing Mode............................................................................................................196
10.3.7.1 Direct to Direct.................................................................................................................................196
10.3.7.2 Immediate to Direct......................................................................................................................... 196
10.3.7.3 Indexed to Direct, Post Increment....................................................................................................196
10.3.7.4 Direct to Indexed, Post-Increment................................................................................................... 197
10.4 Operation modes............................................................................................................................................................. 197
10.4.1 Stop mode........................................................................................................................................................ 197
10.4.2 Wait mode........................................................................................................................................................197
10.4.3 Background mode............................................................................................................................................ 198
10.4.4 Security mode.................................................................................................................................................. 199
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10.5 HCS08 V6 Opcodes........................................................................................................................................................201
10.6 Special Operations.......................................................................................................................................................... 201
10.6.1 Reset Sequence................................................................................................................................................ 201
10.6.2 Interrupt Sequence........................................................................................................................................... 201
10.7 Instruction Set Summary.................................................................................................................................................202
Chapter 11
Keyboard Interrupts (KBI)
11.1 Introduction.....................................................................................................................................................................215
11.1.1 Features............................................................................................................................................................ 215
11.1.2 Modes of Operation......................................................................................................................................... 215
11.1.2.1 KBI in Wait mode............................................................................................................................215
11.1.2.2 KBI in Stop modes...........................................................................................................................216
11.1.2.3 KBI in Active Background mode.....................................................................................................216
11.1.3 Block Diagram................................................................................................................................................. 216
11.2 External signals description............................................................................................................................................ 217
11.3 Register definition...........................................................................................................................................................217
11.4 Memory Map and Registers............................................................................................................................................217
11.4.1
KBI Status and Control Register (KBIx_SC).................................................................................................. 218
11.4.2
KBI Pin Enable Register (KBIx_PE)...............................................................................................................219
11.4.3
KBI Edge Select Register (KBIx_ES)............................................................................................................. 219
11.5 Functional Description....................................................................................................................................................220
11.5.1 Edge-only sensitivity........................................................................................................................................220
11.5.2 Edge and level sensitivity................................................................................................................................ 220
11.5.3 KBI Pullup Resistor......................................................................................................................................... 220
11.5.4 KBI initialization..............................................................................................................................................221
Chapter 12
FlexTimer Module (FTM)
12.1 Introduction.....................................................................................................................................................................223
12.1.1 FlexTimer philosophy......................................................................................................................................223
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12.1.2 Features............................................................................................................................................................ 223
12.1.3 Modes of operation.......................................................................................................................................... 224
12.1.4 Block diagram..................................................................................................................................................224
12.2 Signal description............................................................................................................................................................225
12.2.1 EXTCLK — FTM external clock.................................................................................................................... 226
12.2.2 CHn — FTM channel (n) I/O pin.................................................................................................................... 226
12.3 Memory map and register definition...............................................................................................................................226
12.3.1 Module memory map.......................................................................................................................................226
12.3.2 Register descriptions........................................................................................................................................226
12.3.3
Status and Control (FTMx_SC)....................................................................................................................... 227
12.3.4
Counter High (FTMx_CNTH)......................................................................................................................... 229
12.3.5
Counter Low (FTMx_CNTL).......................................................................................................................... 229
12.3.6
Modulo High (FTMx_MODH)........................................................................................................................ 230
12.3.7
Modulo Low (FTMx_MODL)......................................................................................................................... 231
12.3.8
Channel Status and Control (FTMx_CnSC).................................................................................................... 231
12.3.9
Channel Value High (FTMx_CnVH)...............................................................................................................232
12.3.10
Channel Value Low (FTMx_CnVL)................................................................................................................234
12.4 Functional Description....................................................................................................................................................234
12.4.1 Clock Source....................................................................................................................................................235
12.4.1.1 Counter Clock Source...................................................................................................................... 235
12.4.2 Prescaler...........................................................................................................................................................235
12.4.3 Counter.............................................................................................................................................................236
12.4.3.1 Up counting......................................................................................................................................236
12.4.3.2 Up-down counting............................................................................................................................236
12.4.3.3 Free running counter........................................................................................................................ 237
12.4.3.4 Counter reset.................................................................................................................................... 238
12.4.4 Input capture mode...........................................................................................................................................238
12.4.5 Output compare mode......................................................................................................................................239
12.4.6 Edge-aligned PWM (EPWM) mode................................................................................................................ 240
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12.4.7 Center-aligned PWM (CPWM) mode..............................................................................................................242
12.4.8 Update of the registers with write buffers........................................................................................................244
12.4.8.1 MODH:L registers........................................................................................................................... 244
12.4.8.2 CnVH:L registers............................................................................................................................. 244
12.4.9 BDM mode.......................................................................................................................................................245
12.5 Reset overview................................................................................................................................................................245
12.6 FTM Interrupts................................................................................................................................................................247
12.6.1 Timer overflow interrupt..................................................................................................................................247
12.6.2 Channel (n) interrupt........................................................................................................................................247
Chapter 13
Real-time counter (RTC)
13.1 Introduction.....................................................................................................................................................................249
13.2 Features...........................................................................................................................................................................249
13.2.1 Modes of operation.......................................................................................................................................... 249
13.2.1.1 Wait mode........................................................................................................................................249
13.2.1.2 Stop modes.......................................................................................................................................250
13.2.2 Block diagram..................................................................................................................................................250
13.3 Register definition...........................................................................................................................................................250
13.3.1 RTC Status and Control Register 1 (RTC_SC1)............................................................................................. 251
13.3.2 RTC Status and Control Register 2 (RTC_SC2)............................................................................................. 252
13.3.3 RTC Modulo Register: High (RTC_MODH).................................................................................................. 253
13.3.4 RTC Modulo Register: Low (RTC_MODL)................................................................................................... 253
13.3.5 RTC Counter Register: High (RTC_CNTH)................................................................................................... 253
13.3.6 RTC Counter Register: Low (RTC_CNTL).................................................................................................... 254
13.4 Functional description.....................................................................................................................................................254
13.4.1 RTC operation example................................................................................................................................... 255
13.5 Initialization/application information............................................................................................................................. 257
Chapter 14
Serial communications interface (SCI)
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14.1 Introduction.....................................................................................................................................................................259
14.1.1 Features............................................................................................................................................................ 259
14.1.2 Modes of operation.......................................................................................................................................... 259
14.1.3 Block diagram..................................................................................................................................................260
14.2 SCI signal descriptions................................................................................................................................................... 262
14.2.1 Detailed signal descriptions............................................................................................................................. 262
14.3 Register definition...........................................................................................................................................................262
14.3.1
SCI Baud Rate Register: High (SCIx_BDH)................................................................................................... 263
14.3.2
SCI Baud Rate Register: Low (SCIx_BDL).................................................................................................... 264
14.3.3
SCI Control Register 1 (SCIx_C1)...................................................................................................................264
14.3.4
SCI Control Register 2 (SCIx_C2)...................................................................................................................266
14.3.5
SCI Status Register 1 (SCIx_S1)..................................................................................................................... 267
14.3.6
SCI Status Register 2 (SCIx_S2)..................................................................................................................... 269
14.3.7
SCI Control Register 3 (SCIx_C3)...................................................................................................................270
14.3.8
SCI Data Register (SCIx_D)............................................................................................................................272
14.4 Functional description.....................................................................................................................................................272
14.4.1 Baud rate generation........................................................................................................................................ 273
14.4.2 Transmitter functional description...................................................................................................................273
14.4.2.1 Send break and queued idle............................................................................................................. 274
14.4.3 Receiver functional description....................................................................................................................... 275
14.4.3.1 Data sampling technique..................................................................................................................276
14.4.3.2 Receiver wake-up operation.............................................................................................................277
14.4.4 Interrupts and status flags................................................................................................................................ 278
14.4.5 Baud rate tolerance...........................................................................................................................................279
14.4.5.1 Slow data tolerance.......................................................................................................................... 279
14.4.5.2 Fast data tolerance............................................................................................................................281
14.4.6 Additional SCI functions................................................................................................................................. 282
14.4.6.1 8- and 9-bit data modes....................................................................................................................282
14.4.6.2 Stop mode operation........................................................................................................................ 282
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14.4.6.3 Loop mode....................................................................................................................................... 282
14.4.6.4 Single-wire operation.......................................................................................................................283
Chapter 15
Analog-to-digital converter (ADC)
15.1 Introduction.....................................................................................................................................................................285
15.1.1 Features............................................................................................................................................................ 285
15.1.2 Block Diagram................................................................................................................................................. 286
15.2 External Signal Description............................................................................................................................................ 286
15.2.1 Analog Power (VDDA)................................................................................................................................... 286
15.2.2 Analog Ground (VSSA)...................................................................................................................................286
15.2.3 Voltage Reference High (VREFH)..................................................................................................................286
15.2.4 Voltage Reference Low (VREFL)................................................................................................................... 287
15.2.5 Analog Channel Inputs (ADx)......................................................................................................................... 287
15.3 ADC Control Registers...................................................................................................................................................287
15.3.1 Status and Control Register 1 (ADC_SC1)......................................................................................................288
15.3.2 Status and Control Register 2 (ADC_SC2)......................................................................................................289
15.3.3 Status and Control Register 3 (ADC_SC3)......................................................................................................290
15.3.4 Status and Control Register 4 (ADC_SC4)......................................................................................................291
15.3.5 Conversion Result High Register (ADC_RH).................................................................................................292
15.3.6 Conversion Result Low Register (ADC_RL).................................................................................................. 293
15.3.7 Compare Value High Register (ADC_CVH)...................................................................................................294
15.3.8 Compare Value Low Register (ADC_CVL)....................................................................................................294
15.3.9 Pin Control 1 Register (ADC_APCTL1).........................................................................................................295
15.4 Functional description.....................................................................................................................................................296
15.4.1 Clock select and divide control........................................................................................................................296
15.4.2 Input select and pin control..............................................................................................................................297
15.4.3 Hardware trigger.............................................................................................................................................. 297
15.4.4 Conversion control...........................................................................................................................................298
15.4.4.1 Initiating conversions.......................................................................................................................298
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15.4.4.2 Completing conversions...................................................................................................................298
15.4.4.3 Aborting conversions....................................................................................................................... 299
15.4.4.4 Power control................................................................................................................................... 300
15.4.4.5 Sample time and total conversion time............................................................................................300
15.4.5 Automatic compare function............................................................................................................................301
15.4.6 FIFO operation.................................................................................................................................................302
15.4.7 MCU wait mode operation...............................................................................................................................305
15.4.8 MCU Stop3 mode operation............................................................................................................................ 306
15.4.8.1 Stop3 mode with ADACK disabled.................................................................................................306
15.4.8.2 Stop3 mode with ADACK enabled..................................................................................................306
15.5 Initialization information................................................................................................................................................ 307
15.5.1 ADC module initialization example................................................................................................................ 307
15.5.1.1 Initialization sequence......................................................................................................................307
15.5.1.2 Pseudo-code example.......................................................................................................................308
15.5.2 ADC FIFO module initialization example.......................................................................................................308
15.5.2.1 Pseudo-code example.......................................................................................................................309
15.6 Application information..................................................................................................................................................310
15.6.1 External pins and routing................................................................................................................................. 310
15.6.1.1 Analog supply pins...........................................................................................................................310
15.6.1.2 Analog reference pins...................................................................................................................... 310
15.6.1.3 Analog input pins.............................................................................................................................311
15.6.2 Sources of error................................................................................................................................................312
15.6.2.1 Sampling error..................................................................................................................................312
15.6.2.2 Pin leakage error.............................................................................................................................. 312
15.6.2.3 Noise-induced errors........................................................................................................................312
15.6.2.4 Code width and quantization error...................................................................................................313
15.6.2.5 Linearity errors.................................................................................................................................314
15.6.2.6 Code jitter, non-monotonicity, and missing codes...........................................................................315
Chapter 16
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Section number Title Page
Analog comparator (ACMP)
16.1 Introduction.....................................................................................................................................................................317
16.1.1 Features............................................................................................................................................................ 317
16.1.2 Modes of operation.......................................................................................................................................... 317
16.1.2.1 Operation in Wait mode...................................................................................................................318
16.1.2.2 Operation in Stop3 mode................................................................................................................. 318
16.1.2.3 Operation in Debug mode................................................................................................................318
16.1.3 Block diagram..................................................................................................................................................318
16.2 External signal description..............................................................................................................................................319
16.3 Memory map and register definition...............................................................................................................................319
16.3.1 ACMP Control and Status Register (ACMP_CS)........................................................................................... 320
16.3.2 ACMP Control Register 0 (ACMP_C0).......................................................................................................... 321
16.3.3 ACMP Control Register 1 (ACMP_C1).......................................................................................................... 321
16.3.4 ACMP Control Register 2 (ACMP_C2).......................................................................................................... 322
16.4 Functional description.....................................................................................................................................................322
16.5 Setup and operation of ACMP........................................................................................................................................323
16.6 Resets..............................................................................................................................................................................324
16.7 Interrupts.........................................................................................................................................................................324
Chapter 17
Watchdog (WDOG)
17.1 Introduction.....................................................................................................................................................................325
17.1.1 Features............................................................................................................................................................ 325
17.1.2 Block diagram..................................................................................................................................................326
17.2 Memory map and register definition...............................................................................................................................327
17.2.1 Watchdog Control and Status Register 1 (WDOG_CS1)................................................................................ 327
17.2.2 Watchdog Control and Status Register 2 (WDOG_CS2)................................................................................ 329
17.2.3 Watchdog Counter Register: High (WDOG_CNTH)......................................................................................330
17.2.4 Watchdog Counter Register: Low (WDOG_CNTL).......................................................................................330
17.2.5 Watchdog Timeout Value Register: High (WDOG_TOVALH)..................................................................... 331
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17.2.6 Watchdog Timeout Value Register: Low (WDOG_TOVALL)...................................................................... 331
17.2.7 Watchdog Window Register: High (WDOG_WINH).....................................................................................332
17.2.8 Watchdog Window Register: Low (WDOG_WINL)...................................................................................... 332
17.3 Functional description.....................................................................................................................................................333
17.3.1 Watchdog refresh mechanism..........................................................................................................................333
17.3.1.1 Window mode..................................................................................................................................334
17.3.1.2 Refreshing the Watchdog.................................................................................................................334
17.3.1.3 Example code: Refreshing the Watchdog........................................................................................335
17.3.2 Configuring the Watchdog...............................................................................................................................335
17.3.2.1 Reconfiguring the Watchdog........................................................................................................... 335
17.3.2.2 Unlocking the Watchdog................................................................................................................. 336
17.3.2.3 Example code: Reconfiguring the Watchdog.................................................................................. 336
17.3.3 Clock source.....................................................................................................................................................336
17.3.4 Using interrupts to delay resets........................................................................................................................338
17.3.5 Backup reset.....................................................................................................................................................338
17.3.6 Functionality in debug and low-power modes.................................................................................................338
17.3.7 Fast testing of the watchdog.............................................................................................................................339
17.3.7.1 Testing each byte of the counter...................................................................................................... 339
17.3.7.2 Entering user mode.......................................................................................................................... 340
Chapter 18
Development support
18.1 Introduction.....................................................................................................................................................................341
18.1.1 Forcing active background...............................................................................................................................341
18.1.2 Features............................................................................................................................................................ 341
18.2 Background debug controller (BDC)..............................................................................................................................342
18.2.1 BKGD pin description..................................................................................................................................... 343
18.2.2 Communication details.................................................................................................................................... 344
18.2.3 BDC commands............................................................................................................................................... 346
18.2.4 BDC hardware breakpoint............................................................................................................................... 349
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18.3 On-chip debug system (DBG)........................................................................................................................................ 349
18.3.1 Comparators A and B.......................................................................................................................................350
18.3.2 Bus capture information and FIFO operation.................................................................................................. 350
18.3.3 Change-of-flow information............................................................................................................................ 351
18.3.4 Tag vs. force breakpoints and triggers.............................................................................................................352
18.3.5 Trigger modes.................................................................................................................................................. 353
18.3.6 Hardware breakpoints...................................................................................................................................... 354
18.4 Memory map and register description............................................................................................................................ 355
18.4.1 BDC Status and Control Register (BDC_SCR)...............................................................................................355
18.4.2 BDC Breakpoint Match Register: High (BDC_BKPTH)................................................................................357
18.4.3 BDC Breakpoint Register: Low (BDC_BKPTL)............................................................................................ 358
18.4.4 System Background Debug Force Reset Register (BDC_SBDFR).................................................................358
Chapter 19
Debug module (DBG)
19.1 Introduction.....................................................................................................................................................................361
19.1.1 Features............................................................................................................................................................ 361
19.1.2 Modes of operation.......................................................................................................................................... 362
19.1.3 Block diagram..................................................................................................................................................362
19.2 Signal description............................................................................................................................................................363
19.3 Memory map and registers..............................................................................................................................................363
19.3.1 Debug Comparator A High Register (DBG_CAH)......................................................................................... 364
19.3.2 Debug Comparator A Low Register (DBG_CAL).......................................................................................... 365
19.3.3 Debug Comparator B High Register (DBG_CBH)..........................................................................................366
19.3.4 Debug Comparator B Low Register (DBG_CBL)...........................................................................................366
19.3.5 Debug Comparator C High Register (DBG_CCH)..........................................................................................367
19.3.6 Debug Comparator C Low Register (DBG_CCL)...........................................................................................368
19.3.7 Debug FIFO High Register (DBG_FH)...........................................................................................................368
19.3.8 Debug FIFO Low Register (DBG_FL)............................................................................................................369
19.3.9 Debug Comparator A Extension Register (DBG_CAX)................................................................................. 370
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