MC9S08 PL60 Reference Manual
Supports: MC9S08PL60 and MC9S08PL32
Document Number: MC9S08PL60RM
Rev. 4, 08/2019
MC9S08 PL60 Reference Manual, Rev. 4, 08/2019
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Contents
Section number Title Page
Chapter 1
Device Overview
1.1 Introduction.....................................................................................................................................................................25
1.2 MCU block diagram....................................................................................................................................................... 26
1.3 System clock distribution................................................................................................................................................28
Chapter 2
Pins and connections
2.1 Device pin assignment.................................................................................................................................................... 31
2.2 Pin functions................................................................................................................................................................... 34
2.2.1 Power (VDD, VSS)..........................................................................................................................................34
2.2.2 Analog power supply and reference pins (VDDA/VREFH and VSSA/VREFL)............................................35
2.2.3 Oscillator (XTAL, EXTAL)............................................................................................................................ 36
2.2.4 External reset pin (RESET) and interrupt pin (IRQ)....................................................................................... 37
2.2.5 Background/mode select (BKGD/MS)............................................................................................................ 38
2.2.6 Port A input/output (I/O) pins (PTA7–PTA0)................................................................................................. 39
2.2.7 Port B input/output (I/O) pins (PTB7–PTB0)..................................................................................................39
2.2.8 Port C input/output (I/O) pins (PTC7–PTC0)..................................................................................................39
2.2.9 Port D input/output (I/O) pins (PTD7–PTD0)................................................................................................. 39
2.2.10 Port E input/Output (I/O) pins (PTE7-PTE0).................................................................................................. 40
2.2.11 Port F input/output (I/O) pins (PTF7–PTF0)................................................................................................... 40
2.2.12 Port G input/output (I/O) pins (PTG3–PTG0)................................................................................................. 40
2.2.13 Port H input/output (I/O) pins (PTH7–PTH6, PTH2–PTH0)..........................................................................40
2.2.14 True open drain pins (PTA3–PTA2)................................................................................................................40
2.3 Peripheral pinouts........................................................................................................................................................... 41
Chapter 3
Power management
3.1 Introduction.....................................................................................................................................................................45
3.2 Features...........................................................................................................................................................................45
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3.2.1 Run mode......................................................................................................................................................... 45
3.2.2 Wait mode........................................................................................................................................................46
3.2.3 Stop3 mode...................................................................................................................................................... 46
3.2.4 Active BDM enabled in stop3 mode................................................................................................................46
3.2.5 LVD enabled in stop mode.............................................................................................................................. 47
3.2.6 Power modes behaviors................................................................................................................................... 47
3.3 Low voltage detect (LVD) system..................................................................................................................................48
3.3.1 Power-on reset (POR) operation......................................................................................................................49
3.3.2 LVD reset operation.........................................................................................................................................49
3.3.3 Low-voltage warning (LVW).......................................................................................................................... 49
3.4 Bandgap reference.......................................................................................................................................................... 50
3.5 Power management control bits and registers................................................................................................................ 50
3.5.1 System Power Management Status and Control 1 Register (PMC_SPMSC1)................................................50
3.5.2 System Power Management Status and Control 2 Register (PMC_SPMSC2)................................................52
Chapter 4
Memory map
4.1 Memory map...................................................................................................................................................................53
4.2 Reset and interrupt vector assignments...........................................................................................................................54
4.3 Register addresses and bit assignments.......................................................................................................................... 55
4.4 Random-access memory (RAM).................................................................................................................................... 65
4.5 Flash and EEPROM........................................................................................................................................................65
4.5.1 Overview..........................................................................................................................................................65
4.5.2 Function descriptions....................................................................................................................................... 68
4.5.2.1 Modes of operation.......................................................................................................................... 68
4.5.2.2 Flash and EEPROM memory map...................................................................................................68
4.5.2.3 Flash and EEPROM initialization after system reset.......................................................................69
4.5.2.4 Flash and EEPROM command operations.......................................................................................69
4.5.2.5 Flash and EEPROM interrupts.........................................................................................................74
4.5.2.6 Protection......................................................................................................................................... 75
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4.5.2.7 Security............................................................................................................................................ 79
4.5.2.8 Flash and EEPROM commands.......................................................................................................81
4.5.2.9 Flash and EEPROM command summary........................................................................................ 83
4.6 Flash and EEPROM registers descriptions.....................................................................................................................97
4.6.1 Flash Clock Divider Register (NVM_FCLKDIV)...........................................................................................97
4.6.2 Flash Security Register (NVM_FSEC)............................................................................................................98
4.6.3 Flash CCOB Index Register (NVM_FCCOBIX)............................................................................................ 99
4.6.4 Flash Configuration Register (NVM_FCNFG)............................................................................................... 99
4.6.5 Flash Error Configuration Register (NVM_FERCNFG).................................................................................100
4.6.6 Flash Status Register (NVM_FSTAT).............................................................................................................101
4.6.7 Flash Error Status Register (NVM_FERSTAT).............................................................................................. 102
4.6.8 Flash Protection Register (NVM_FPROT)......................................................................................................103
4.6.9 EEPROM Protection Register (NVM_EEPROT)............................................................................................104
4.6.10 Flash Common Command Object Register:High (NVM_FCCOBHI)............................................................106
4.6.11 Flash Common Command Object Register: Low (NVM_FCCOBLO)...........................................................106
4.6.12 Flash Option Register (NVM_FOPT)..............................................................................................................106
Chapter 5
Interrupt
5.1 Interrupts.........................................................................................................................................................................109
5.1.1 Interrupt stack frame........................................................................................................................................ 110
5.1.2 Interrupt vectors, sources, and local masks......................................................................................................111
5.1.3 Hardware nested interrupt................................................................................................................................114
5.1.3.1 Interrupt priority level register.........................................................................................................115
5.1.3.2 Interrupt priority level comparator set............................................................................................. 116
5.1.3.3 Interrupt priority mask update and restore mechanism....................................................................116
5.1.3.4 Integration and application of the IPC............................................................................................. 117
5.2 IRQ..................................................................................................................................................................................117
5.2.1 Features............................................................................................................................................................ 118
5.2.1.1 Pin configuration options.................................................................................................................118
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5.2.1.2 Edge and level sensitivity................................................................................................................ 119
5.3 Interrupt pin request register...........................................................................................................................................119
5.3.1 Interrupt Pin Request Status and Control Register (IRQ_SC).........................................................................120
5.4 Interrupt priority control register.................................................................................................................................... 121
5.4.1 IPC Status and Control Register (IPC_SC)......................................................................................................122
5.4.2 Interrupt Priority Mask Pseudo Stack Register (IPC_IPMPS)........................................................................ 123
5.4.3
Interrupt Level Setting Registers n (IPC_ILRSn)............................................................................................123
Chapter 6
System control
6.1 System device identification (SDID)..............................................................................................................................125
6.2 Universally unique identification (UUID)......................................................................................................................125
6.3 Reset and system initialization........................................................................................................................................125
6.4 System options................................................................................................................................................................126
6.4.1 BKGD pin enable.............................................................................................................................................126
6.4.2 RESET pin enable............................................................................................................................................126
6.4.3 SCI0 pin reassignment..................................................................................................................................... 126
6.4.4 FTM2 channels pin reassignment.................................................................................................................... 127
6.4.5 Bus clock output pin enable.............................................................................................................................127
6.5 System interconnection...................................................................................................................................................127
6.5.1 ACMP output selection....................................................................................................................................128
6.5.2 SCI0 TxD modulation......................................................................................................................................128
6.5.3 SCI0 RxD capture............................................................................................................................................ 129
6.5.4 SCI0 RxD filter................................................................................................................................................ 129
6.5.5 RTC capture..................................................................................................................................................... 130
6.5.6 ADC hardware trigger......................................................................................................................................130
6.6 System Control Registers................................................................................................................................................131
6.6.1 System Reset Status Register (SYS_SRS).......................................................................................................131
6.6.2 System Background Debug Force Reset Register (SYS_SBDFR)..................................................................133
6.6.3 System Device Identification Register: High (SYS_SDIDH)......................................................................... 134
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6.6.4 System Device Identification Register: Low (SYS_SDIDL).......................................................................... 134
6.6.5 System Options Register 1 (SYS_SOPT1)...................................................................................................... 135
6.6.6 System Options Register 2 (SYS_SOPT2)...................................................................................................... 136
6.6.7 System Options Register 3 (SYS_SOPT3)...................................................................................................... 137
6.6.8 Illegal Address Register: High (SYS_ILLAH)................................................................................................138
6.6.9 Illegal Address Register: Low (SYS_ILLAL).................................................................................................139
6.6.10 Universally Unique Identifier Register 1 (SYS_UUID1)................................................................................139
6.6.11 Universally Unique Identifier Register 2 (SYS_UUID2)................................................................................140
6.6.12 Universally Unique Identifier Register 3 (SYS_UUID3)................................................................................140
6.6.13 Universally Unique Identifier Register 4 (SYS_UUID4)................................................................................141
6.6.14 Universally Unique Identifier Register 5 (SYS_UUID5)................................................................................141
6.6.15 Universally Unique Identifier Register 6 (SYS_UUID6)................................................................................142
6.6.16 Universally Unique Identifier Register 7 (SYS_UUID7)................................................................................142
6.6.17 Universally Unique Identifier Register 8 (SYS_UUID8)................................................................................143
Chapter 7
Parallel input/output
7.1 Introduction.....................................................................................................................................................................145
7.2 Port data and data direction.............................................................................................................................................146
7.3 Internal pullup enable..................................................................................................................................................... 147
7.4 Input glitch filter setting..................................................................................................................................................147
7.5 Pin behavior in stop mode...............................................................................................................................................148
7.6 Port data registers............................................................................................................................................................148
7.6.1 Port A Data Register (PORT_PTAD)..............................................................................................................149
7.6.2 Port B Data Register (PORT_PTBD).............................................................................................................. 150
7.6.3 Port C Data Register (PORT_PTCD).............................................................................................................. 150
7.6.4 Port D Data Register (PORT_PTDD)..............................................................................................................151
7.6.5 Port E Data Register (PORT_PTED)...............................................................................................................151
7.6.6 Port F Data Register (PORT_PTFD)............................................................................................................... 152
7.6.7 Port G Data Register (PORT_PTGD)..............................................................................................................152
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7.6.8 Port H Data Register (PORT_PTHD)..............................................................................................................153
7.6.9 Port A Output Enable Register (PORT_PTAOE)............................................................................................153
7.6.10 Port B Output Enable Register (PORT_PTBOE)............................................................................................ 155
7.6.11 Port C Output Enable Register (PORT_PTCOE)............................................................................................ 156
7.6.12 Port D Output Enable Register (PORT_PTDOE)............................................................................................157
7.6.13 Port E Output Enable Register (PORT_PTEOE).............................................................................................158
7.6.14 Port F Output Enable Register (PORT_PTFOE)............................................................................................. 160
7.6.15 Port G Output Enable Register (PORT_PTGOE)............................................................................................161
7.6.16 Port H Output Enable Register (PORT_PTHOE)............................................................................................162
7.6.17 Port A Input Enable Register (PORT_PTAIE)................................................................................................163
7.6.18 Port B Input Enable Register (PORT_PTBIE)................................................................................................ 164
7.6.19 Port C Input Enable Register (PORT_PTCIE)................................................................................................ 165
7.6.20 Port D Input Enable Register (PORT_PTDIE)................................................................................................166
7.6.21 Port E Input Enable Register (PORT_PTEIE).................................................................................................167
7.6.22 Port F Input Enable Register (PORT_PTFIE)................................................................................................. 169
7.6.23 Port G Input Enable Register (PORT_PTGIE)................................................................................................170
7.6.24 Port H Input Enable Register (PORT_PTHIE)................................................................................................171
7.6.25 Port Filter Register 0 (PORT_IOFLT0)...........................................................................................................172
7.6.26 Port Filter Register 1 (PORT_IOFLT1)...........................................................................................................173
7.6.27 Port Filter Register 2 (PORT_IOFLT2)...........................................................................................................174
7.6.28 Port Clock Division Register (PORT_FCLKDIV).......................................................................................... 174
7.6.29 Port A Pullup Enable Register (PORT_PTAPE)............................................................................................. 175
7.6.30 Port B Pullup Enable Register (PORT_PTBPE)..............................................................................................177
7.6.31 Port C Pullup Enable Register (PORT_PTCPE)..............................................................................................178
7.6.32 Port D Pullup Enable Register (PORT_PTDPE)............................................................................................. 179
7.6.33 Port E Pullup Enable Register (PORT_PTEPE)..............................................................................................181
7.6.34 Port F Pullup Enable Register (PORT_PTFPE).............................................................................................. 182
7.6.35 Port G Pullup Enable Register (PORT_PTGPE)............................................................................................. 183
7.6.36 Port H Pullup Enable Register (PORT_PTHPE)............................................................................................. 184
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Chapter 8
Clock management
8.1 Clock module..................................................................................................................................................................187
8.2 Internal clock source (ICS)............................................................................................................................................. 187
8.2.1 Function description.........................................................................................................................................188
8.2.1.1 Bus frequency divider...................................................................................................................... 189
8.2.1.2 Low power bit usage........................................................................................................................189
8.2.1.3 Internal reference clock (ICSIRCLK)..............................................................................................189
8.2.1.4 Fixed frequency clock (ICSFFCLK)................................................................................................190
8.2.1.5 BDC clock........................................................................................................................................191
8.2.2 Modes of operation.......................................................................................................................................... 191
8.2.2.1 FLL engaged internal (FEI)............................................................................................................. 192
8.2.2.2 FLL engaged external (FEE)............................................................................................................193
8.2.2.3 FLL bypassed internal (FBI)............................................................................................................193
8.2.2.4 FLL bypassed internal low power (FBILP)..................................................................................... 193
8.2.2.5 FLL bypassed external (FBE)..........................................................................................................194
8.2.2.6 FLL bypassed external low power (FBELP)................................................................................... 194
8.2.2.7 Stop (STOP).....................................................................................................................................195
8.2.3 FLL lock and clock monitor.............................................................................................................................196
8.2.3.1 FLL clock lock.................................................................................................................................196
8.2.3.2 External reference clock monitor.....................................................................................................196
8.3 Initialization / application information........................................................................................................................... 196
8.3.1 Initializing FEI mode....................................................................................................................................... 197
8.3.2 Initializing FBI mode.......................................................................................................................................197
8.3.3 Initializing FEE mode...................................................................................................................................... 197
8.3.4 Initializing FBE mode......................................................................................................................................198
8.3.5 External oscillator (OSC).................................................................................................................................198
8.3.5.1 Bypass mode.................................................................................................................................... 199
8.3.5.2 Low-power configuration................................................................................................................ 199
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8.3.5.3 High-gain configuration...................................................................................................................200
8.3.5.4 Initializing external oscillator for peripherals..................................................................................200
8.4 1 kHz low-power oscillator (LPO)................................................................................................................................. 201
8.5 Peripheral clock gating................................................................................................................................................... 201
8.6 ICS control registers....................................................................................................................................................... 201
8.6.1 ICS Control Register 1 (ICS_C1).................................................................................................................... 202
8.6.2 ICS Control Register 2 (ICS_C2).................................................................................................................... 203
8.6.3 ICS Control Register 3 (ICS_C3).................................................................................................................... 204
8.6.4 ICS Control Register 4 (ICS_C4).................................................................................................................... 204
8.6.5 ICS Status Register (ICS_S)............................................................................................................................ 205
8.6.6 OSC Status and Control Register (ICS_OSCSC)............................................................................................ 206
8.7 System clock gating control registers............................................................................................................................. 207
8.7.1 System Clock Gating Control 1 Register (SCG_C1).......................................................................................208
8.7.2 System Clock Gating Control 2 Register (SCG_C2).......................................................................................209
8.7.3 System Clock Gating Control 3 Register (SCG_C3).......................................................................................210
8.7.4 System Clock Gating Control 4 Register (SCG_C4).......................................................................................211
Chapter 9
Chip configurations
9.1 Introduction.....................................................................................................................................................................213
9.2 Core modules.................................................................................................................................................................. 213
9.2.1 Central processor unit (CPU)...........................................................................................................................213
9.2.2 Debug module (DBG)......................................................................................................................................213
9.3 System modules.............................................................................................................................................................. 214
9.3.1 Watchdog (WDOG)......................................................................................................................................... 214
9.4 Clock module..................................................................................................................................................................214
9.5 Memory...........................................................................................................................................................................214
9.5.1 Random-access-memory (RAM)..................................................................................................................... 214
9.5.2 Non-volatile memory (NVM).......................................................................................................................... 215
9.6 Power modules................................................................................................................................................................215
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9.7 Security........................................................................................................................................................................... 215
9.7.1 Cyclic redundancy check (CRC)......................................................................................................................215
9.8 Timers............................................................................................................................................................................. 216
9.8.1 FlexTimer module (FTM)................................................................................................................................216
9.8.1.1 FTM0 interconnection......................................................................................................................216
9.8.1.2 FTM1 interconnection......................................................................................................................217
9.8.1.3 FTM2 interconnection......................................................................................................................217
9.8.2 8-bit modulo timer (MTIM).............................................................................................................................217
9.8.2.1 MTIM0 as ADC hardware trigger................................................................................................... 217
9.8.3 Real-time counter (RTC)................................................................................................................................. 217
9.9 Communication interfaces.............................................................................................................................................. 218
9.9.1 Serial communications interface (SCI)............................................................................................................218
9.9.1.1 SCI0 infrared functions....................................................................................................................218
9.10 Analog.............................................................................................................................................................................219
9.10.1 Analog-to-digital converter (ADC)..................................................................................................................219
9.10.1.1 ADC block diagram......................................................................................................................... 219
9.10.1.2 ADC channel assignments............................................................................................................... 220
9.10.1.3 Alternate clock................................................................................................................................. 221
9.10.1.4 Hardware trigger.............................................................................................................................. 222
9.10.1.5 Temperature sensor..........................................................................................................................222
9.10.2 Analog comparator (ACMP)............................................................................................................................223
9.10.2.1 ACMP configuration information....................................................................................................223
9.10.2.2 ACMP in stop3 mode.......................................................................................................................224
9.10.2.3 ACMP to FTM configuration information.......................................................................................224
9.10.2.4 ACMP for SCI0 RXD filter............................................................................................................. 224
9.11 Human-machine interfaces HMI.....................................................................................................................................225
9.11.1 Keyboard interrupts (KBI)...............................................................................................................................225
Chapter 10
Central processor unit
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10.1 Introduction.....................................................................................................................................................................227
10.1.1 Features............................................................................................................................................................ 227
10.2 Programmer's Model and CPU Registers....................................................................................................................... 228
10.2.1 Accumulator (A).............................................................................................................................................. 228
10.2.2 Index Register (H:X)........................................................................................................................................229
10.2.3 Stack Pointer (SP)............................................................................................................................................ 229
10.2.4 Program Counter (PC)..................................................................................................................................... 230
10.2.5 Condition Code Register (CCR)...................................................................................................................... 230
10.3 Addressing Modes.......................................................................................................................................................... 231
10.3.1 Inherent Addressing Mode (INH)....................................................................................................................232
10.3.2 Relative Addressing Mode (REL)....................................................................................................................232
10.3.3 Immediate Addressing Mode (IMM)...............................................................................................................232
10.3.4 Direct Addressing Mode (DIR)........................................................................................................................233
10.3.5 Extended Addressing Mode (EXT)..................................................................................................................233
10.3.6 Indexed Addressing Mode............................................................................................................................... 234
10.3.6.1 Indexed, No Offset (IX)...................................................................................................................234
10.3.6.2 Indexed, No Offset with Post Increment (IX+)................................................................................234
10.3.6.3 Indexed, 8-Bit Offset (IX1)..............................................................................................................234
10.3.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+).......................................................................... 235
10.3.6.5 Indexed, 16-Bit Offset (IX2)............................................................................................................235
10.3.6.6 SP-Relative, 8-Bit Offset (SP1)....................................................................................................... 235
10.3.6.7 SP-Relative, 16-Bit Offset (SP2)..................................................................................................... 236
10.3.7 Memory to memory Addressing Mode............................................................................................................236
10.3.7.1 Direct to Direct.................................................................................................................................236
10.3.7.2 Immediate to Direct......................................................................................................................... 236
10.3.7.3 Indexed to Direct, Post Increment....................................................................................................236
10.3.7.4 Direct to Indexed, Post-Increment................................................................................................... 237
10.4 Operation modes............................................................................................................................................................. 237
10.4.1 Stop mode........................................................................................................................................................ 237
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10.4.2 Wait mode........................................................................................................................................................237
10.4.3 Background mode............................................................................................................................................ 238
10.4.4 Security mode.................................................................................................................................................. 239
10.5 HCS08 V6 Opcodes........................................................................................................................................................241
10.6 Special Operations.......................................................................................................................................................... 241
10.6.1 Reset Sequence................................................................................................................................................ 241
10.6.2 Interrupt Sequence........................................................................................................................................... 241
10.7 Instruction Set Summary.................................................................................................................................................242
Chapter 11
Keyboard Interrupts (KBI)
11.1 Introduction.....................................................................................................................................................................255
11.1.1 Features............................................................................................................................................................ 255
11.1.2 Modes of Operation......................................................................................................................................... 255
11.1.2.1 KBI in Wait mode............................................................................................................................255
11.1.2.2 KBI in Stop modes...........................................................................................................................256
11.1.2.3 KBI in Active Background mode.....................................................................................................256
11.1.3 Block Diagram................................................................................................................................................. 256
11.2 External signals description............................................................................................................................................ 257
11.3 Register definition...........................................................................................................................................................257
11.4 Memory Map and Registers............................................................................................................................................257
11.4.1
KBI Status and Control Register (KBIx_SC).................................................................................................. 258
11.4.2
KBI Pin Enable Register (KBIx_PE)...............................................................................................................259
11.4.3
KBI Edge Select Register (KBIx_ES)............................................................................................................. 259
11.5 Functional Description....................................................................................................................................................260
11.5.1 Edge-only sensitivity........................................................................................................................................260
11.5.2 Edge and level sensitivity................................................................................................................................ 260
11.5.3 KBI Pullup Resistor......................................................................................................................................... 261
11.5.4 KBI initialization..............................................................................................................................................261
Chapter 12
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FlexTimer Module (FTM)
12.1 Introduction.....................................................................................................................................................................263
12.1.1 FlexTimer philosophy......................................................................................................................................263
12.1.2 Features............................................................................................................................................................ 263
12.1.3 Modes of operation.......................................................................................................................................... 264
12.1.4 Block diagram..................................................................................................................................................264
12.2 Signal description............................................................................................................................................................265
12.2.1 EXTCLK — FTM external clock.................................................................................................................... 266
12.2.2 CHn — FTM channel (n) I/O pin.................................................................................................................... 266
12.3 Memory map and register definition...............................................................................................................................266
12.3.1 Module memory map.......................................................................................................................................266
12.3.2 Register descriptions........................................................................................................................................266
12.3.3
Status and Control (FTMx_SC)....................................................................................................................... 269
12.3.4
Counter High (FTMx_CNTH)......................................................................................................................... 270
12.3.5
Counter Low (FTMx_CNTL).......................................................................................................................... 271
12.3.6
Modulo High (FTMx_MODH)........................................................................................................................ 271
12.3.7
Modulo Low (FTMx_MODL)......................................................................................................................... 272
12.3.8
Channel Status and Control (FTMx_CnSC).................................................................................................... 272
12.3.9
Channel Value High (FTMx_CnVH)...............................................................................................................274
12.3.10
Channel Value Low (FTMx_CnVL)................................................................................................................275
12.4 Functional Description....................................................................................................................................................275
12.4.1 Clock Source....................................................................................................................................................276
12.4.1.1 Counter Clock Source...................................................................................................................... 276
12.4.2 Prescaler...........................................................................................................................................................277
12.4.3 Counter.............................................................................................................................................................277
12.4.3.1 Up counting......................................................................................................................................277
12.4.3.2 Up-down counting............................................................................................................................278
12.4.3.3 Free running counter........................................................................................................................ 279
12.4.3.4 Counter reset.................................................................................................................................... 279
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12.4.4 Input capture mode...........................................................................................................................................279
12.4.5 Output compare mode......................................................................................................................................280
12.4.6 Edge-aligned PWM (EPWM) mode................................................................................................................ 282
12.4.7 Center-aligned PWM (CPWM) mode..............................................................................................................283
12.4.8 Update of the registers with write buffers........................................................................................................285
12.4.8.1 MODH:L registers........................................................................................................................... 285
12.4.8.2 CnVH:L registers............................................................................................................................. 286
12.4.9 BDM mode.......................................................................................................................................................286
12.5 Reset overview................................................................................................................................................................286
12.6 FTM Interrupts................................................................................................................................................................288
12.6.1 Timer overflow interrupt..................................................................................................................................288
12.6.2 Channel (n) interrupt........................................................................................................................................288
Chapter 13
8-bit modulo timer (MTIM)
13.1 Introduction.....................................................................................................................................................................289
13.2 Features...........................................................................................................................................................................289
13.3 Modes of operation......................................................................................................................................................... 289
13.3.1 MTIM in wait mode.........................................................................................................................................290
13.3.2 MTIM in stop mode......................................................................................................................................... 290
13.3.3 MTIM in active background mode.................................................................................................................. 290
13.4 Block diagram.................................................................................................................................................................290
13.5 External signal description..............................................................................................................................................291
13.6 Register definition...........................................................................................................................................................291
13.6.1
MTIM Status and Control Register (MTIMx_SC).......................................................................................... 291
13.6.2
MTIM Clock Configuration Register (MTIMx_CLK).................................................................................... 292
13.6.3
MTIM Counter Register (MTIMx_CNT)........................................................................................................ 293
13.6.4
MTIM Modulo Register (MTIMx_MOD)....................................................................................................... 294
13.7 Functional description.....................................................................................................................................................294
13.7.1 MTIM operation example................................................................................................................................ 295
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Chapter 14
Real-time counter (RTC)
14.1 Introduction.....................................................................................................................................................................297
14.2 Features...........................................................................................................................................................................297
14.2.1 Modes of operation.......................................................................................................................................... 297
14.2.1.1 Wait mode........................................................................................................................................297
14.2.1.2 Stop modes.......................................................................................................................................298
14.2.2 Block diagram..................................................................................................................................................298
14.3 External signal description..............................................................................................................................................298
14.4 Register definition...........................................................................................................................................................299
14.4.1 RTC Status and Control Register 1 (RTC_SC1)............................................................................................. 299
14.4.2 RTC Status and Control Register 2 (RTC_SC2)............................................................................................. 300
14.4.3 RTC Modulo Register: High (RTC_MODH).................................................................................................. 301
14.4.4 RTC Modulo Register: Low (RTC_MODL)................................................................................................... 301
14.4.5 RTC Counter Register: High (RTC_CNTH)................................................................................................... 302
14.4.6 RTC Counter Register: Low (RTC_CNTL).................................................................................................... 302
14.5 Functional description.....................................................................................................................................................303
14.5.1 RTC operation example................................................................................................................................... 304
14.6 Initialization/application information............................................................................................................................. 305
Chapter 15
Serial communications interface (SCI)
15.1 Introduction.....................................................................................................................................................................307
15.1.1 Features............................................................................................................................................................ 307
15.1.2 Modes of operation.......................................................................................................................................... 307
15.1.3 Block diagram..................................................................................................................................................308
15.2 SCI signal descriptions................................................................................................................................................... 310
15.2.1 Detailed signal descriptions............................................................................................................................. 310
15.3 Register definition...........................................................................................................................................................310
15.3.1
SCI Baud Rate Register: High (SCIx_BDH)................................................................................................... 311
MC9S08 PL60 Reference Manual, Rev. 4, 08/2019
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Section number Title Page
15.3.2
SCI Baud Rate Register: Low (SCIx_BDL).................................................................................................... 312
15.3.3
SCI Control Register 1 (SCIx_C1)...................................................................................................................313
15.3.4
SCI Control Register 2 (SCIx_C2)...................................................................................................................314
15.3.5
SCI Status Register 1 (SCIx_S1)..................................................................................................................... 315
15.3.6
SCI Status Register 2 (SCIx_S2)..................................................................................................................... 317
15.3.7
SCI Control Register 3 (SCIx_C3)...................................................................................................................319
15.3.8
SCI Data Register (SCIx_D)............................................................................................................................320
15.4 Functional description.....................................................................................................................................................321
15.4.1 Baud rate generation........................................................................................................................................ 321
15.4.2 Transmitter functional description...................................................................................................................322
15.4.2.1 Send break and queued idle............................................................................................................. 322
15.4.3 Receiver functional description....................................................................................................................... 323
15.4.3.1 Data sampling technique..................................................................................................................324
15.4.3.2 Receiver wake-up operation.............................................................................................................325
15.4.4 Interrupts and status flags................................................................................................................................ 326
15.4.5 Baud rate tolerance...........................................................................................................................................327
15.4.5.1 Slow data tolerance.......................................................................................................................... 328
15.4.5.2 Fast data tolerance............................................................................................................................329
15.4.6 Additional SCI functions................................................................................................................................. 330
15.4.6.1 8- and 9-bit data modes....................................................................................................................330
15.4.6.2 Stop mode operation........................................................................................................................ 330
15.4.6.3 Loop mode....................................................................................................................................... 331
15.4.6.4 Single-wire operation.......................................................................................................................331
Chapter 16
Analog-to-digital converter (ADC)
16.1 Introduction.....................................................................................................................................................................333
16.1.1 Features............................................................................................................................................................ 333
16.1.2 Block Diagram................................................................................................................................................. 334
16.2 External Signal Description............................................................................................................................................ 334
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NXP Semiconductors 17
Section number Title Page
16.2.1 Analog Power (VDDA)................................................................................................................................... 334
16.2.2 Analog Ground (VSSA)...................................................................................................................................334
16.2.3 Voltage Reference High (VREFH)..................................................................................................................334
16.2.4 Voltage Reference Low (VREFL)................................................................................................................... 335
16.2.5 Analog Channel Inputs (ADx)......................................................................................................................... 335
16.3 ADC Control Registers...................................................................................................................................................335
16.3.1 Status and Control Register 1 (ADC_SC1)......................................................................................................336
16.3.2 Status and Control Register 2 (ADC_SC2)......................................................................................................337
16.3.3 Status and Control Register 3 (ADC_SC3)......................................................................................................338
16.3.4 Status and Control Register 4 (ADC_SC4)......................................................................................................339
16.3.5 Conversion Result High Register (ADC_RH).................................................................................................340
16.3.6 Conversion Result Low Register (ADC_RL).................................................................................................. 341
16.3.7 Compare Value High Register (ADC_CVH)...................................................................................................342
16.3.8 Compare Value Low Register (ADC_CVL)....................................................................................................342
16.3.9 Pin Control 1 Register (ADC_APCTL1).........................................................................................................343
16.3.10 Pin Control 2 Register (ADC_APCTL2).........................................................................................................344
16.4 Functional description.....................................................................................................................................................345
16.4.1 Clock select and divide control........................................................................................................................346
16.4.2 Input select and pin control..............................................................................................................................346
16.4.3 Hardware trigger.............................................................................................................................................. 347
16.4.4 Conversion control...........................................................................................................................................347
16.4.4.1 Initiating conversions.......................................................................................................................347
16.4.4.2 Completing conversions...................................................................................................................348
16.4.4.3 Aborting conversions....................................................................................................................... 348
16.4.4.4 Power control................................................................................................................................... 349
16.4.4.5 Sample time and total conversion time............................................................................................349
16.4.5 Automatic compare function............................................................................................................................350
16.4.6 FIFO operation.................................................................................................................................................351
16.4.7 MCU wait mode operation...............................................................................................................................354
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Section number Title Page
16.4.8 MCU Stop mode operation.............................................................................................................................. 355
16.4.8.1 Stop mode with ADACK disabled...................................................................................................355
16.4.8.2 Stop mode with ADACK enabled....................................................................................................355
16.5 Initialization information................................................................................................................................................ 356
16.5.1 ADC module initialization example................................................................................................................ 356
16.5.1.1 Initialization sequence......................................................................................................................356
16.5.1.2 Pseudo-code example.......................................................................................................................357
16.5.2 ADC FIFO module initialization example.......................................................................................................357
16.5.2.1 Pseudo-code example.......................................................................................................................358
16.6 Application information..................................................................................................................................................359
16.6.1 External pins and routing................................................................................................................................. 359
16.6.1.1 Analog supply pins...........................................................................................................................359
16.6.1.2 Analog reference pins...................................................................................................................... 359
16.6.1.3 Analog input pins.............................................................................................................................360
16.6.2 Sources of error................................................................................................................................................361
16.6.2.1 Sampling error..................................................................................................................................361
16.6.2.2 Pin leakage error.............................................................................................................................. 361
16.6.2.3 Noise-induced errors........................................................................................................................361
16.6.2.4 Code width and quantization error...................................................................................................362
16.6.2.5 Linearity errors.................................................................................................................................363
16.6.2.6 Code jitter, non-monotonicity, and missing codes...........................................................................363
Chapter 17
Analog comparator (ACMP)
17.1 Introduction.....................................................................................................................................................................365
17.1.1 Features............................................................................................................................................................ 365
17.1.2 Modes of operation.......................................................................................................................................... 365
17.1.2.1 Operation in Wait mode...................................................................................................................366
17.1.2.2 Operation in Stop mode................................................................................................................... 366
17.1.2.3 Operation in Debug mode................................................................................................................366
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Section number Title Page
17.1.3 Block diagram..................................................................................................................................................366
17.2 External signal description..............................................................................................................................................367
17.3 Memory map and register definition...............................................................................................................................367
17.3.1 ACMP Control and Status Register (ACMP_CS)........................................................................................... 368
17.3.2 ACMP Control Register 0 (ACMP_C0).......................................................................................................... 369
17.3.3 ACMP Control Register 1 (ACMP_C1).......................................................................................................... 369
17.3.4 ACMP Control Register 2 (ACMP_C2).......................................................................................................... 370
17.4 Functional description.....................................................................................................................................................370
17.5 Setup and operation of ACMP........................................................................................................................................371
17.6 Resets..............................................................................................................................................................................372
17.7 Interrupts.........................................................................................................................................................................372
Chapter 18
Cyclic redundancy check (CRC)
18.1 Introduction.....................................................................................................................................................................373
18.2 Features...........................................................................................................................................................................373
18.3 Block diagram.................................................................................................................................................................373
18.4 Modes of operation......................................................................................................................................................... 374
18.5 Register definition...........................................................................................................................................................374
18.5.1 CRC Data 0 Register (CRC_D0)..................................................................................................................... 375
18.5.2 CRC Data 1 Register (CRC_D1)..................................................................................................................... 375
18.5.3 CRC Data 2 Register (CRC_D2)..................................................................................................................... 376
18.5.4 CRC Data 3 Register (CRC_D3)..................................................................................................................... 377
18.5.5 CRC Polynomial 0 Register (CRC_P0)...........................................................................................................377
18.5.6 CRC Polynomial 1 Register (CRC_P1)...........................................................................................................378
18.5.7 CRC Polynomial 2 Register (CRC_P2)...........................................................................................................378
18.5.8 CRC Polynomial 3 Register (CRC_P3)...........................................................................................................379
18.5.9 CRC Control Register (CRC_CTRL).............................................................................................................. 379
18.6 Functional description.....................................................................................................................................................380
18.6.1 16-bit CRC calculation.....................................................................................................................................380
MC9S08 PL60 Reference Manual, Rev. 4, 08/2019
20 NXP Semiconductors
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