MC9S08PL16S Reference Manual
Supports: MC9S08PL16SCTJ MC9S08PL16SCTG
MC9S08PL16SCSC MC9S08PL8SCTJ MC9S08PL8SCTG
MC9S08PL8SCSC
Document Number: MC9S08PL16SRM
Rev. 2, 10/2019
MC9S08PL16S Reference Manual, Rev. 2, 10/2019
2 NXP Semiconductors
Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.........................................................................................................................................................................25
1.1.1 Purpose.............................................................................................................................................................25
1.1.2 Audience.......................................................................................................................................................... 25
1.2 Conventions.................................................................................................................................................................... 25
1.2.1 Numbering systems..........................................................................................................................................25
1.2.2 Typographic notation....................................................................................................................................... 26
1.2.3 Special terms....................................................................................................................................................26
Chapter 2
Introduction
2.1 Introduction.....................................................................................................................................................................27
2.2 Module functional categories..........................................................................................................................................27
2.2.1 S08L core modules...........................................................................................................................................28
2.2.2 System modules............................................................................................................................................... 28
2.2.3 Memories and memory interfaces....................................................................................................................29
2.2.4 Clocks...............................................................................................................................................................29
2.2.5 Security and integrity modules........................................................................................................................ 29
2.2.6 Analog modules............................................................................................................................................... 30
2.2.7 Timer modules................................................................................................................................................. 30
2.2.8 Communication interfaces............................................................................................................................... 31
2.2.9 Human-machine interfaces.............................................................................................................................. 31
2.3 MCU block diagram....................................................................................................................................................... 31
2.4 Orderable part numbers...................................................................................................................................................32
Chapter 3
Pins and connections
3.1 Device pin assignment.................................................................................................................................................... 35
3.2 Pin functions................................................................................................................................................................... 36
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3.2.1 Power (VDD, VSS)..........................................................................................................................................36
3.2.2 Analog power supply and reference pins (VDDA/VREFH and VSSA/VREFL)............................................36
3.2.3 Oscillator (XTAL, EXTAL)............................................................................................................................ 37
3.2.4 External reset pin (RESET) and interrupt pin (IRQ)....................................................................................... 38
3.2.5 Background/mode select (BKGD/MS)............................................................................................................ 39
3.2.6 Port A input/output (I/O) pins (PTA5-PTA0)..................................................................................................40
3.2.7 Port B input/output (I/O) pins (PTB7–PTB0)..................................................................................................40
3.2.8 Port C input/output (I/O) pins (PTC7–PTC0)..................................................................................................40
3.3 Peripheral pinouts........................................................................................................................................................... 41
Chapter 4
Power management
4.1 Introduction.....................................................................................................................................................................43
4.2 Features...........................................................................................................................................................................43
4.2.1 Run mode......................................................................................................................................................... 43
4.2.2 Wait mode........................................................................................................................................................44
4.2.3 Stop3 mode...................................................................................................................................................... 44
4.2.4 Active BDM enabled in stop3 mode................................................................................................................44
4.2.5 LVD enabled in stop mode.............................................................................................................................. 45
4.2.6 Power modes behaviors................................................................................................................................... 45
4.3 Low voltage detect (LVD) system..................................................................................................................................46
4.3.1 Power-on reset (POR) operation......................................................................................................................47
4.3.2 LVD reset operation.........................................................................................................................................47
4.3.3 Low-voltage warning (LVW).......................................................................................................................... 47
4.4 Power management control bits and registers................................................................................................................ 48
4.4.1 System Power Management Status and Control 1 Register (PMC_SPMSC1)................................................48
4.4.2 System Power Management Status and Control 2 Register (PMC_SPMSC2)................................................50
Chapter 5
Memory map
5.1 Memory map...................................................................................................................................................................51
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5.2 Peripheral register addresses...........................................................................................................................................52
5.3 Random-access memory (RAM).................................................................................................................................... 54
5.4 Flash memory..................................................................................................................................................................55
Chapter 6
Interrupt
6.1 Interrupts.........................................................................................................................................................................57
6.1.1 Interrupt stack frame........................................................................................................................................ 58
6.1.2 Interrupt vectors, sources, and local masks......................................................................................................59
6.1.3 Hardware nested interrupt................................................................................................................................61
6.1.3.1 Interrupt priority level register.....................................................................................................63
6.1.3.2 Interrupt priority level comparator set......................................................................................... 63
6.1.3.3 Interrupt priority mask update and restore mechanism................................................................63
6.1.3.4 Integration and application of the IPC......................................................................................... 64
6.2 IRQ..................................................................................................................................................................................65
6.2.1 Features............................................................................................................................................................ 65
6.2.1.1 Pin configuration options.............................................................................................................66
6.2.1.2 Edge and level sensitivity............................................................................................................ 67
6.3 Interrupt pin request register...........................................................................................................................................67
6.3.1 Interrupt Pin Request Status and Control Register (IRQ_SC).........................................................................67
6.4 Interrupt priority control register.................................................................................................................................... 69
6.4.1 IPC Status and Control Register (IPC_SC)......................................................................................................69
6.4.2 Interrupt Priority Mask Pseudo Stack Register (IPC_IPMPS)........................................................................ 70
6.4.3
Interrupt Level Setting Registers n (IPC_ILRSn)............................................................................................71
Chapter 7
System control
7.1 System device identification (SDID)..............................................................................................................................73
7.2 Universally unique identification (UUID)......................................................................................................................73
7.3 Reset and system initialization........................................................................................................................................73
7.4 System options................................................................................................................................................................74
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7.4.1 BKGD pin enable.............................................................................................................................................74
7.4.2 RESET pin enable............................................................................................................................................74
7.4.3 SCI0 pin reassignment..................................................................................................................................... 74
7.4.4 FTM0 channels pin reassignment.................................................................................................................... 74
7.5 System interconnection...................................................................................................................................................75
7.5.1 ACMP output selection....................................................................................................................................75
7.5.2 SCI0 TxD modulation......................................................................................................................................75
7.5.3 SCI0 RxD capture............................................................................................................................................ 76
7.5.4 SCI0 RxD filter................................................................................................................................................ 76
7.5.5 RTC capture..................................................................................................................................................... 77
7.5.6 ADC hardware trigger......................................................................................................................................77
7.6 FTM software controlled output..................................................................................................................................... 78
7.7 System Control Registers................................................................................................................................................79
7.7.1 System Reset Status Register (SYS_SRS).......................................................................................................79
7.7.2 System Background Debug Force Reset Register (SYS_SBDFR)..................................................................81
7.7.3 System Device Identification Register: High (SYS_SDIDH)......................................................................... 82
7.7.4 System Device Identification Register: Low (SYS_SDIDL).......................................................................... 83
7.7.5 System Options Register 1 (SYS_SOPT1)...................................................................................................... 83
7.7.6 System Options Register 2 (SYS_SOPT2)...................................................................................................... 84
7.7.7 System Options Register 3 (SYS_SOPT3)...................................................................................................... 86
7.7.8 System Options Register 4 (SYS_SOPT4)...................................................................................................... 87
7.7.9 System Options Register 5 (SYS_SOPT5)...................................................................................................... 87
7.7.10 System Options Register 6 (SYS_SOPT6)...................................................................................................... 88
7.7.11 System Options Register 7 (SYS_SOPT7)...................................................................................................... 89
7.7.12 System Options Register 8 (SYS_SOPT8)...................................................................................................... 90
7.7.13 System Clock Gating Control 1 Register (SYS_SCGC1)............................................................................... 91
7.7.14 System Clock Gating Control 2 Register (SYS_SCGC2)............................................................................... 92
7.7.15 System Clock Gating Control 3 Register (SYS_SCGC3)............................................................................... 93
7.7.16 System Clock Gating Control 4 Register (SYS_SCGC4)............................................................................... 94
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7.7.17 Illegal Address Register: High (SYS_ILLAH)................................................................................................95
7.7.18 Illegal Address Register: Low (SYS_ILLAL).................................................................................................96
7.7.19 Universally Unique Identifier Register 1 (SYS_UUID1)................................................................................97
7.7.20 Universally Unique Identifier Register 2 (SYS_UUID2)................................................................................97
7.7.21 Universally Unique Identifier Register 3 (SYS_UUID3)................................................................................98
7.7.22 Universally Unique Identifier Register 4 (SYS_UUID4)................................................................................98
7.7.23 Universally Unique Identifier Register 5 (SYS_UUID5)................................................................................99
7.7.24 Universally Unique Identifier Register 6 (SYS_UUID6)................................................................................99
7.7.25 Universally Unique Identifier Register 7 (SYS_UUID7)................................................................................100
7.7.26 Universally Unique Identifier Register 8 (SYS_UUID8)................................................................................100
Chapter 8
Clock management
8.1 Clock module..................................................................................................................................................................101
8.2 System clock distribution................................................................................................................................................101
8.3 Internal clock source (ICS)............................................................................................................................................. 103
8.4 Oscillator (OSC)............................................................................................................................................................. 104
8.5 Peripheral clock gating................................................................................................................................................... 104
Chapter 9
Central processor unit
9.1 Introduction.....................................................................................................................................................................107
9.1.1 Features............................................................................................................................................................ 107
9.2 Programmer's Model and CPU Registers....................................................................................................................... 108
9.2.1 Accumulator (A).............................................................................................................................................. 108
9.2.2 Index Register (H:X)........................................................................................................................................109
9.2.3 Stack Pointer (SP)............................................................................................................................................ 109
9.2.4 Program Counter (PC)..................................................................................................................................... 110
9.2.5 Condition Code Register (CCR)...................................................................................................................... 110
9.3 Addressing Modes.......................................................................................................................................................... 111
9.3.1 Inherent Addressing Mode (INH)....................................................................................................................112
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9.3.2 Relative Addressing Mode (REL)....................................................................................................................112
9.3.3 Immediate Addressing Mode (IMM)...............................................................................................................112
9.3.4 Direct Addressing Mode (DIR)........................................................................................................................113
9.3.5 Extended Addressing Mode (EXT)..................................................................................................................113
9.3.6 Indexed Addressing Mode............................................................................................................................... 114
9.3.6.1 Indexed, No Offset (IX)...............................................................................................................114
9.3.6.2 Indexed, No Offset with Post Increment (IX+)............................................................................114
9.3.6.3 Indexed, 8-Bit Offset (IX1)..........................................................................................................114
9.3.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+)...................................................................... 115
9.3.6.5 Indexed, 16-Bit Offset (IX2)........................................................................................................115
9.3.6.6 SP-Relative, 8-Bit Offset (SP1)................................................................................................... 115
9.3.6.7 SP-Relative, 16-Bit Offset (SP2)................................................................................................. 116
9.3.7 Memory to memory Addressing Mode............................................................................................................116
9.3.7.1 Direct to Direct.............................................................................................................................116
9.3.7.2 Immediate to Direct..................................................................................................................... 116
9.3.7.3 Indexed to Direct, Post Increment................................................................................................116
9.3.7.4 Direct to Indexed, Post-Increment............................................................................................... 117
9.4 Operation modes............................................................................................................................................................. 117
9.4.1 Stop mode........................................................................................................................................................ 117
9.4.2 Wait mode........................................................................................................................................................117
9.4.3 Background mode............................................................................................................................................ 118
9.4.4 Security mode.................................................................................................................................................. 119
9.5 HCS08 V6 Opcodes........................................................................................................................................................121
9.6 Special Operations.......................................................................................................................................................... 121
9.6.1 Reset Sequence................................................................................................................................................ 121
9.6.2 Interrupt Sequence........................................................................................................................................... 121
9.7 Instruction Set Summary.................................................................................................................................................122
Chapter 10
Flash Memory Module (FTMRH)
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10.1 Introduction.....................................................................................................................................................................135
10.2 Feature.............................................................................................................................................................................135
10.2.1 Flash memory features.....................................................................................................................................135
10.2.2 Other flash module features............................................................................................................................. 136
10.3 Functional description.....................................................................................................................................................136
10.3.1 Modes of operation.......................................................................................................................................... 136
10.3.1.1 Wait mode....................................................................................................................................136
10.3.1.2 Stop mode.................................................................................................................................... 136
10.3.2 Flash block read access....................................................................................................................................136
10.3.3 Flash memory map...........................................................................................................................................137
10.3.4 Flash initialization after system reset...............................................................................................................137
10.3.5 Flash command operations...............................................................................................................................137
10.3.5.1 Writing the FCLKDIV register....................................................................................................138
10.3.5.2 Command write sequence............................................................................................................ 140
10.3.6 Flash interrupts.................................................................................................................................................142
10.3.6.1 Description of flash interrupt operation.......................................................................................142
10.3.7 Protection......................................................................................................................................................... 142
10.3.8 Security............................................................................................................................................................ 145
10.3.8.1 Unsecuring the MCU using backdoor key access........................................................................146
10.3.8.2 Unsecuring the MCU using BDM............................................................................................... 147
10.3.8.3 Mode and security effects on flash command availability...........................................................147
10.3.9 Flash commands...............................................................................................................................................147
10.3.9.1 Flash commands...........................................................................................................................147
10.3.10 Flash command summary................................................................................................................................ 148
10.3.10.1 Erase Verify All Blocks command.............................................................................................. 149
10.3.10.2 Erase Verify Block command......................................................................................................149
10.3.10.3 Erase Verify Flash Section command..........................................................................................150
10.3.10.4 Read once command.................................................................................................................... 151
10.3.10.5 Program Flash command............................................................................................................. 152
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10.3.10.6 Program Once command..............................................................................................................153
10.3.10.7 Erase All Blocks command..........................................................................................................154
10.3.10.8 Erase flash block command......................................................................................................... 154
10.3.10.9 Erase flash sector command.........................................................................................................155
10.3.10.10 Unsecure flash command.............................................................................................................156
10.3.10.11 Verify backdoor access key command.........................................................................................157
10.3.10.12 Set user margin level command...................................................................................................157
10.3.10.13 Set factory margin level command.............................................................................................. 159
10.4 Memory map and register definition...............................................................................................................................160
10.4.1 Flash Clock Divider Register (FTMRH_FCLKDIV)...................................................................................... 161
10.4.2 Flash Security Register (FTMRH_FSEC)....................................................................................................... 162
10.4.3 Flash CCOB Index Register (FTMRH_FCCOBIX)........................................................................................163
10.4.4 Flash Configuration Register (FTMRH_FCNFG)...........................................................................................163
10.4.5 Flash Status Register (FTMRH_FSTAT)........................................................................................................ 164
10.4.6 Flash Protection Register (FTMRH_FPROT)................................................................................................. 165
10.4.7 Flash Common Command Object Register:High (FTMRH_FCCOBHI)........................................................166
10.4.8 Flash Common Command Object Register: Low (FTMRH_FCCOBLO)...................................................... 167
10.4.9 Flash Option Register (FTMRH_FOPT)......................................................................................................... 167
Chapter 11
Port Control (PORT)
11.1 Introduction.....................................................................................................................................................................169
11.2 Port data and data direction.............................................................................................................................................170
11.3 Internal pullup enable..................................................................................................................................................... 171
11.4 Input glitch filter setting..................................................................................................................................................171
11.5 Pin behavior in stop mode...............................................................................................................................................171
11.6 Port data registers............................................................................................................................................................172
11.6.1 Port A Data Register (PORT_PTAD)..............................................................................................................172
11.6.2 Port B Data Register (PORT_PTBD).............................................................................................................. 173
11.6.3 Port C Data Register (PORT_PTCD).............................................................................................................. 173
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11.6.4 Port A Output Enable Register (PORT_PTAOE)............................................................................................174
11.6.5 Port B Output Enable Register (PORT_PTBOE)............................................................................................ 175
11.6.6 Port C Output Enable Register (PORT_PTCOE)............................................................................................ 176
11.6.7 Port A Input Enable Register (PORT_PTAIE)................................................................................................177
11.6.8 Port B Input Enable Register (PORT_PTBIE)................................................................................................ 178
11.6.9 Port C Input Enable Register (PORT_PTCIE)................................................................................................ 179
11.6.10 Port Filter Register 0 (PORT_IOFLT0)...........................................................................................................180
11.6.11 Port Filter Register 2 (PORT_IOFLT2)...........................................................................................................181
11.6.12 Port Clock Division Register (PORT_FCLKDIV).......................................................................................... 182
11.6.13 Port A Pullup Enable Register (PORT_PTAPE)............................................................................................. 183
11.6.14 Port B Pullup Enable Register (PORT_PTBPE)..............................................................................................184
11.6.15 Port C Pullup Enable Register (PORT_PTCPE)..............................................................................................185
Chapter 12
Keyboard Interrupts (KBI)
12.1 Introduction.....................................................................................................................................................................187
12.1.1 Features............................................................................................................................................................ 187
12.1.2 Modes of Operation......................................................................................................................................... 187
12.1.2.1 KBI in Wait mode........................................................................................................................187
12.1.2.2 KBI in Stop modes.......................................................................................................................188
12.1.3 Block Diagram................................................................................................................................................. 188
12.2 External signals description............................................................................................................................................ 188
12.3 Register definition...........................................................................................................................................................189
12.4 Memory Map and Registers............................................................................................................................................189
12.4.1
KBI Status and Control Register (KBIx_SC).................................................................................................. 190
12.4.2
KBI Pin Enable Register (KBIx_PE)...............................................................................................................191
12.4.3
KBI Edge Select Register (KBIx_ES)............................................................................................................. 191
12.5 Functional Description....................................................................................................................................................192
12.5.1 Edge-only sensitivity........................................................................................................................................192
12.5.2 Edge and level sensitivity................................................................................................................................ 192
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12.5.3 KBI Pullup Resistor......................................................................................................................................... 192
12.5.4 KBI initialization..............................................................................................................................................193
Chapter 13
Internal Clock Source (ICS)
13.1 Chip specific ICS information........................................................................................................................................ 195
13.2 Introduction.....................................................................................................................................................................195
13.2.1 Features............................................................................................................................................................ 195
13.2.2 Block diagram..................................................................................................................................................196
13.2.3 Modes of operation.......................................................................................................................................... 196
13.2.3.1 FLL engaged internal (FEI)......................................................................................................... 196
13.2.3.2 FLL engaged external (FEE)........................................................................................................197
13.2.3.3 FLL bypassed internal (FBI)........................................................................................................197
13.2.3.4 FLL bypassed internal low power (FBILP)................................................................................. 197
13.2.3.5 FLL bypassed external (FBE)......................................................................................................197
13.2.3.6 FLL bypassed external low power (FBELP)............................................................................... 197
13.2.3.7 Stop (STOP).................................................................................................................................197
13.3 External signal description..............................................................................................................................................198
13.4 Register definition...........................................................................................................................................................198
13.4.1 ICS Control Register 1 (ICS_C1).................................................................................................................... 198
13.4.2 ICS Control Register 2 (ICS_C2).................................................................................................................... 199
13.4.3 ICS Control Register 3 (ICS_C3).................................................................................................................... 200
13.4.4 ICS Control Register 4 (ICS_C4).................................................................................................................... 201
13.4.5 ICS Status Register (ICS_S)............................................................................................................................ 201
13.5 Functional description.....................................................................................................................................................202
13.5.1 Operational modes........................................................................................................................................... 202
13.5.1.1 FLL engaged internal (FEI)......................................................................................................... 203
13.5.1.2 FLL engaged external (FEE)........................................................................................................203
13.5.1.3 FLL bypassed internal (FBI)........................................................................................................204
13.5.1.4 FLL bypassed internal low power (FBILP)................................................................................. 204
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13.5.1.5 FLL bypassed external (FBE)......................................................................................................204
13.5.1.6 FLL bypassed external low power (FBELP)............................................................................... 205
13.5.1.7 Stop.............................................................................................................................................. 205
13.5.2 Mode switching................................................................................................................................................205
13.5.3 Bus frequency divider...................................................................................................................................... 206
13.5.4 Low-power field usage.....................................................................................................................................206
13.5.5 Internal reference clock....................................................................................................................................206
13.5.6 Fixed frequency clock......................................................................................................................................207
13.5.7 FLL lock and clock monitor.............................................................................................................................207
13.5.7.1 FLL clock lock.............................................................................................................................207
13.5.7.2 External reference clock monitor.................................................................................................208
Chapter 14
Oscillator (OSC)
14.1 Chip specific OSC information.......................................................................................................................................209
14.2 Introduction.....................................................................................................................................................................209
14.2.1 Overview..........................................................................................................................................................209
14.2.2 Features and modes..........................................................................................................................................209
14.2.3 Block diagram..................................................................................................................................................209
14.3 Signal description............................................................................................................................................................210
14.4 External crystal / resonator connections......................................................................................................................... 211
14.5 External clock connections............................................................................................................................................. 212
14.6 Memory map and register descriptions...........................................................................................................................213
14.6.1 OSC Control Register (OSC_CR)....................................................................................................................213
14.7 Functional description.....................................................................................................................................................214
14.7.1 OSC module states...........................................................................................................................................214
14.7.1.1 Off................................................................................................................................................ 215
14.7.1.2 Oscillator startup..........................................................................................................................216
14.7.1.3 Oscillator stable............................................................................................................................216
14.7.1.4 External clock mode.....................................................................................................................216
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14.7.2 OSC module modes......................................................................................................................................... 216
14.7.2.1 Low-frequency, high-gain mode..................................................................................................217
14.7.2.2 Low-frequency, low-power mode................................................................................................217
14.7.2.3 High-frequency, high-gain mode................................................................................................. 217
14.7.2.4 High-frequency, low-power mode............................................................................................... 218
14.7.3 Counter.............................................................................................................................................................218
14.7.4 Reference clock pin requirements....................................................................................................................218
Chapter 15
FlexTimer Module (FTM)
15.1 Chip specific FTM information...................................................................................................................................... 219
15.2 Introduction.....................................................................................................................................................................220
15.2.1 FlexTimer philosophy......................................................................................................................................220
15.2.2 Features............................................................................................................................................................ 220
15.2.3 Modes of operation.......................................................................................................................................... 221
15.2.4 Block diagram..................................................................................................................................................221
15.3 Signal description............................................................................................................................................................222
15.3.1 EXTCLK — FTM external clock.................................................................................................................... 223
15.3.2 CHn — FTM channel (n) I/O pin.................................................................................................................... 223
15.4 Memory map and register definition...............................................................................................................................223
15.4.1 Module memory map.......................................................................................................................................223
15.4.2 Register descriptions........................................................................................................................................223
15.4.3
Status and Control (FTMx_SC)....................................................................................................................... 225
15.4.4
Counter High (FTMx_CNTH)......................................................................................................................... 226
15.4.5
Counter Low (FTMx_CNTL).......................................................................................................................... 227
15.4.6
Modulo High (FTMx_MODH)........................................................................................................................ 227
15.4.7
Modulo Low (FTMx_MODL)......................................................................................................................... 228
15.4.8
Channel Status and Control (FTMx_CnSC).................................................................................................... 229
15.4.9
Channel Value High (FTMx_CnVH)...............................................................................................................230
15.4.10
Channel Value Low (FTMx_CnVL)................................................................................................................231
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15.5 Functional Description....................................................................................................................................................232
15.5.1 Clock Source....................................................................................................................................................232
15.5.1.1 Counter Clock Source.................................................................................................................. 232
15.5.2 Prescaler...........................................................................................................................................................233
15.5.3 Counter.............................................................................................................................................................233
15.5.3.1 Up counting..................................................................................................................................234
15.5.3.2 Up-down counting........................................................................................................................234
15.5.3.3 Free running counter.................................................................................................................... 235
15.5.3.4 Counter reset................................................................................................................................ 235
15.5.4 Input capture mode...........................................................................................................................................235
15.5.5 Output compare mode......................................................................................................................................236
15.5.6 Edge-aligned PWM (EPWM) mode................................................................................................................ 238
15.5.7 Center-aligned PWM (CPWM) mode..............................................................................................................239
15.5.8 Update of the registers with write buffers........................................................................................................241
15.5.8.1 MODH:L registers....................................................................................................................... 241
15.5.8.2 CnVH:L registers......................................................................................................................... 242
15.5.9 BDM mode.......................................................................................................................................................242
15.6 Reset overview................................................................................................................................................................242
15.7 FTM Interrupts................................................................................................................................................................244
15.7.1 Timer overflow interrupt..................................................................................................................................244
15.7.2 Channel (n) interrupt........................................................................................................................................244
Chapter 16
8-bit modulo timer (MTIM)
16.1 Chip specific MTIM information....................................................................................................................................245
16.2 Introduction.....................................................................................................................................................................245
16.3 Features...........................................................................................................................................................................246
16.4 Modes of operation......................................................................................................................................................... 246
16.4.1 MTIM in wait mode.........................................................................................................................................246
16.4.2 MTIM in stop mode......................................................................................................................................... 246
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16.4.3 MTIM in active background mode.................................................................................................................. 247
16.5 Block diagram.................................................................................................................................................................247
16.6 External signal description..............................................................................................................................................247
16.7 Register definition...........................................................................................................................................................248
16.7.1
MTIM Status and Control Register (MTIMx_SC).......................................................................................... 248
16.7.2
MTIM Clock Configuration Register (MTIMx_CLK).................................................................................... 249
16.7.3
MTIM Counter Register (MTIMx_CNT)........................................................................................................ 250
16.7.4
MTIM Modulo Register (MTIMx_MOD)....................................................................................................... 250
16.8 Functional description.....................................................................................................................................................251
16.8.1 MTIM operation example................................................................................................................................ 252
Chapter 17
Real-time counter (RTC)
17.1 Chip specific RTC information.......................................................................................................................................253
17.2 Introduction.....................................................................................................................................................................253
17.3 Features...........................................................................................................................................................................253
17.3.1 Modes of operation.......................................................................................................................................... 254
17.3.1.1 Wait mode....................................................................................................................................254
17.3.1.2 Stop modes...................................................................................................................................254
17.3.2 Block diagram..................................................................................................................................................254
17.4 Register definition...........................................................................................................................................................255
17.4.1 RTC Status and Control Register 1 (RTC_SC1)............................................................................................. 256
17.4.2 RTC Status and Control Register 2 (RTC_SC2)............................................................................................. 256
17.4.3 RTC Modulo Register: High (RTC_MODH).................................................................................................. 257
17.4.4 RTC Modulo Register: Low (RTC_MODL)................................................................................................... 258
17.4.5 RTC Counter Register: High (RTC_CNTH)................................................................................................... 258
17.4.6 RTC Counter Register: Low (RTC_CNTL).................................................................................................... 259
17.5 Functional description.....................................................................................................................................................259
17.5.1 RTC operation example................................................................................................................................... 260
17.6 Initialization/application information............................................................................................................................. 261
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Chapter 18
Serial communications interface (SCI)
18.1 Chip specific SCI information........................................................................................................................................ 263
18.2 Introduction.....................................................................................................................................................................263
18.2.1 Features............................................................................................................................................................ 263
18.2.2 Modes of operation.......................................................................................................................................... 264
18.2.3 Block diagram..................................................................................................................................................264
18.3 SCI signal descriptions................................................................................................................................................... 267
18.3.1 Detailed signal descriptions............................................................................................................................. 267
18.4 Register definition...........................................................................................................................................................267
18.4.1
SCI Baud Rate Register: High (SCIx_BDH)................................................................................................... 268
18.4.2
SCI Baud Rate Register: Low (SCIx_BDL).................................................................................................... 269
18.4.3
SCI Control Register 1 (SCIx_C1)...................................................................................................................269
18.4.4
SCI Control Register 2 (SCIx_C2)...................................................................................................................271
18.4.5
SCI Status Register 1 (SCIx_S1)..................................................................................................................... 272
18.4.6
SCI Status Register 2 (SCIx_S2)..................................................................................................................... 274
18.4.7
SCI Control Register 3 (SCIx_C3)...................................................................................................................275
18.4.8
SCI Data Register (SCIx_D)............................................................................................................................277
18.5 Functional description.....................................................................................................................................................277
18.5.1 Baud rate generation........................................................................................................................................ 278
18.5.2 Transmitter functional description...................................................................................................................278
18.5.2.1 Send break and queued idle......................................................................................................... 279
18.5.3 Receiver functional description....................................................................................................................... 280
18.5.3.1 Data sampling technique..............................................................................................................281
18.5.3.2 Receiver wake-up operation.........................................................................................................282
18.5.4 Interrupts and status flags................................................................................................................................ 283
18.5.5 Baud rate tolerance...........................................................................................................................................284
18.5.5.1 Slow data tolerance...................................................................................................................... 284
18.5.5.2 Fast data tolerance........................................................................................................................286
MC9S08PL16S Reference Manual, Rev. 2, 10/2019
NXP Semiconductors 17
Section number Title Page
18.5.6 Additional SCI functions................................................................................................................................. 287
18.5.6.1 8- and 9-bit data modes................................................................................................................287
18.5.6.2 Stop mode operation.................................................................................................................... 287
18.5.6.3 Loop mode................................................................................................................................... 287
18.5.6.4 Single-wire operation...................................................................................................................288
Chapter 19
Analog-to-digital converter (ADC)
19.1 Chip specific ADC information......................................................................................................................................289
19.1.1 Channel assignments........................................................................................................................................289
19.1.2 Alternate clock................................................................................................................................................. 290
19.1.3 Hardware trigger.............................................................................................................................................. 290
19.1.4 Temperature sensor..........................................................................................................................................291
19.2 Introduction.....................................................................................................................................................................291
19.2.1 Features............................................................................................................................................................ 292
19.2.2 Block Diagram................................................................................................................................................. 292
19.3 External Signal Description............................................................................................................................................ 293
19.3.1 Analog Power (VDDA)................................................................................................................................... 294
19.3.2 Analog Ground (VSSA)...................................................................................................................................294
19.3.3 Voltage Reference High (VREFH)..................................................................................................................294
19.3.4 Voltage Reference Low (VREFL)................................................................................................................... 294
19.3.5 Analog Channel Inputs (ADx)......................................................................................................................... 294
19.4 ADC Control Registers...................................................................................................................................................295
19.4.1 Status and Control Register 1 (ADC_SC1)......................................................................................................295
19.4.2 Status and Control Register 2 (ADC_SC2)......................................................................................................296
19.4.3 Status and Control Register 3 (ADC_SC3)......................................................................................................298
19.4.4 Status and Control Register 4 (ADC_SC4)......................................................................................................299
19.4.5 Conversion Result High Register (ADC_RH).................................................................................................300
19.4.6 Conversion Result Low Register (ADC_RL).................................................................................................. 301
19.4.7 Compare Value High Register (ADC_CVH)...................................................................................................301
MC9S08PL16S Reference Manual, Rev. 2, 10/2019
18 NXP Semiconductors
Section number Title Page
19.4.8 Compare Value Low Register (ADC_CVL)....................................................................................................302
19.4.9 Pin Control 1 Register (ADC_APCTL1).........................................................................................................302
19.4.10 Pin Control 2 Register (ADC_APCTL2).........................................................................................................304
19.5 Functional description.....................................................................................................................................................304
19.5.1 Clock select and divide control........................................................................................................................305
19.5.2 Input select and pin control..............................................................................................................................306
19.5.3 Hardware trigger.............................................................................................................................................. 306
19.5.4 Conversion control...........................................................................................................................................306
19.5.4.1 Initiating conversions...................................................................................................................306
19.5.4.2 Completing conversions...............................................................................................................307
19.5.4.3 Aborting conversions................................................................................................................... 307
19.5.4.4 Power control............................................................................................................................... 308
19.5.4.5 Sample time and total conversion time........................................................................................308
19.5.5 Automatic compare function............................................................................................................................310
19.5.6 FIFO operation.................................................................................................................................................310
19.5.7 MCU wait mode operation...............................................................................................................................313
19.5.8 MCU Stop mode operation.............................................................................................................................. 314
19.5.8.1 Stop mode with ADACK disabled...............................................................................................314
19.5.8.2 Stop mode with ADACK enabled................................................................................................314
19.6 Initialization information................................................................................................................................................ 315
19.6.1 ADC module initialization example................................................................................................................ 315
19.6.1.1 Initialization sequence..................................................................................................................315
19.6.1.2 Pseudo-code example...................................................................................................................316
19.6.2 ADC FIFO module initialization example.......................................................................................................316
19.6.2.1 Pseudo-code example...................................................................................................................317
19.7 Application information..................................................................................................................................................318
19.7.1 External pins and routing................................................................................................................................. 318
19.7.1.1 Analog supply pins.......................................................................................................................318
19.7.1.2 Analog reference pins.................................................................................................................. 318
MC9S08PL16S Reference Manual, Rev. 2, 10/2019
NXP Semiconductors 19
Section number Title Page
19.7.1.3 Analog input pins.........................................................................................................................319
19.7.2 Sources of error................................................................................................................................................320
19.7.2.1 Sampling error..............................................................................................................................320
19.7.2.2 Pin leakage error.......................................................................................................................... 320
19.7.2.3 Noise-induced errors....................................................................................................................320
19.7.2.4 Code width and quantization error...............................................................................................321
19.7.2.5 Linearity errors.............................................................................................................................322
19.7.2.6 Code jitter, non-monotonicity, and missing codes.......................................................................322
Chapter 20
Analog comparator (ACMP)
20.1 Chip specific ACMP information...................................................................................................................................325
20.1.1 ACMP configuration information....................................................................................................................325
20.1.2 ACMP in Stop3 mode......................................................................................................................................325
20.1.3 ACMP0 for SCI0 RXD Filter.......................................................................................................................... 325
20.1.4 ACMP0 output as FTM2CH0 input capture....................................................................................................326
20.1.5 ACMP0 for ADC trigger..................................................................................................................................326
20.2 Introduction.....................................................................................................................................................................326
20.2.1 Features............................................................................................................................................................ 326
20.2.2 Modes of operation.......................................................................................................................................... 327
20.2.2.1 Operation in Wait mode...............................................................................................................327
20.2.2.2 Operation in Stop mode............................................................................................................... 327
20.2.2.3 Operation in Debug mode............................................................................................................327
20.2.3 Block diagram..................................................................................................................................................327
20.3 External signal description..............................................................................................................................................328
20.4 Memory map and register definition...............................................................................................................................328
20.4.1
ACMP Control and Status Register (ACMPx_CS)..........................................................................................329
20.4.2
ACMP Control Register 0 (ACMPx_C0)........................................................................................................ 330
20.4.3
ACMP Control Register 1 (ACMPx_C1)........................................................................................................ 330
20.4.4
ACMP Control Register 2 (ACMPx_C2)........................................................................................................ 331
MC9S08PL16S Reference Manual, Rev. 2, 10/2019
20 NXP Semiconductors
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