MC9S08 PL16 Reference Manual
Supports: MC9S08PL16 and MC9S08PL8
Document Number: MC9S08PL16RM
Rev. 4, 08/2019
MC9S08 PL16 Reference Manual, Rev. 4, 08/2019
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Contents
Section number Title Page
Chapter 1
Device Overview
1.1 Introduction.....................................................................................................................................................................25
1.2 MCU block diagram....................................................................................................................................................... 26
1.3 System clock distribution................................................................................................................................................27
Chapter 2
Pins and connections
2.1 Device pin assignment.................................................................................................................................................... 31
2.2 Pin functions................................................................................................................................................................... 34
2.2.1 Power (VDD, VSS)..........................................................................................................................................34
2.2.2 Oscillator (XTAL, EXTAL)............................................................................................................................ 35
2.2.3 External reset pin (RESET) and interrupt pin (IRQ)....................................................................................... 36
2.2.4 Background/mode select (BKGD/MS)............................................................................................................ 37
2.2.5 Port A input/output (I/O) pins (PTA7–PTA0)................................................................................................. 38
2.2.6 Port B input/output (I/O) pins (PTB7–PTB0)..................................................................................................38
2.2.7 Port C input/output (I/O) pins (PTC7–PTC0)..................................................................................................38
2.2.8 Port D input/output (I/O) pins (PTD7–PTD0)................................................................................................. 38
2.2.9 Port E input/Output (I/O) pins (PTE4-PTE0).................................................................................................. 39
2.2.10 True open drain pins (PTA3–PTA2)................................................................................................................39
2.3 Peripheral pinouts........................................................................................................................................................... 39
Chapter 3
Power management
3.1 Introduction.....................................................................................................................................................................43
3.2 Features...........................................................................................................................................................................43
3.2.1 Run mode......................................................................................................................................................... 43
3.2.2 Wait mode........................................................................................................................................................44
3.2.3 Stop3 mode...................................................................................................................................................... 44
3.2.4 Active BDM enabled in stop3 mode................................................................................................................44
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3.2.5 LVD enabled in stop mode.............................................................................................................................. 45
3.2.6 Power modes behaviors................................................................................................................................... 45
3.3 Low voltage detect (LVD) system..................................................................................................................................46
3.3.1 Power-on reset (POR) operation......................................................................................................................47
3.3.2 LVD reset operation.........................................................................................................................................47
3.3.3 Low-voltage warning (LVW).......................................................................................................................... 47
3.4 Bandgap reference.......................................................................................................................................................... 48
3.5 Power management control bits and registers................................................................................................................ 48
3.5.1 System Power Management Status and Control 1 Register (PMC_SPMSC1)................................................48
3.5.2 System Power Management Status and Control 2 Register (PMC_SPMSC2)................................................50
Chapter 4
Memory map
4.1 Memory map...................................................................................................................................................................51
4.2 Reset and interrupt vector assignments...........................................................................................................................52
4.3 Register addresses and bit assignments.......................................................................................................................... 53
4.4 Random-access memory (RAM).................................................................................................................................... 62
4.5 Flash and EEPROM........................................................................................................................................................62
4.5.1 Overview..........................................................................................................................................................62
4.5.2 Function descriptions....................................................................................................................................... 65
4.5.2.1 Modes of operation.......................................................................................................................... 65
4.5.2.2 Flash and EEPROM memory map...................................................................................................65
4.5.2.3 Flash and EEPROM initialization after system reset.......................................................................65
4.5.2.4 Flash and EEPROM command operations.......................................................................................66
4.5.2.5 Flash and EEPROM interrupts.........................................................................................................71
4.5.2.6 Protection......................................................................................................................................... 72
4.5.2.7 Security............................................................................................................................................ 75
4.5.2.8 Flash and EEPROM commands.......................................................................................................77
4.5.2.9 Flash and EEPROM command summary........................................................................................ 79
4.6 Flash and EEPROM registers descriptions.....................................................................................................................93
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4.6.1 Flash Clock Divider Register (NVM_FCLKDIV)...........................................................................................93
4.6.2 Flash Security Register (NVM_FSEC)............................................................................................................94
4.6.3 Flash CCOB Index Register (NVM_FCCOBIX)............................................................................................ 95
4.6.4 Flash Configuration Register (NVM_FCNFG)............................................................................................... 95
4.6.5 Flash Error Configuration Register (NVM_FERCNFG).................................................................................96
4.6.6 Flash Status Register (NVM_FSTAT).............................................................................................................97
4.6.7 Flash Error Status Register (NVM_FERSTAT).............................................................................................. 98
4.6.8 Flash Protection Register (NVM_FPROT)......................................................................................................99
4.6.9 EEPROM Protection Register (NVM_EEPROT)............................................................................................100
4.6.10 Flash Common Command Object Register:High (NVM_FCCOBHI)............................................................101
4.6.11 Flash Common Command Object Register: Low (NVM_FCCOBLO)...........................................................102
4.6.12 Flash Option Register (NVM_FOPT)..............................................................................................................102
Chapter 5
Interrupt
5.1 Interrupts.........................................................................................................................................................................105
5.1.1 Interrupt stack frame........................................................................................................................................ 106
5.1.2 Interrupt vectors, sources, and local masks......................................................................................................107
5.1.3 Hardware nested interrupt................................................................................................................................109
5.1.3.1 Interrupt priority level register.........................................................................................................111
5.1.3.2 Interrupt priority level comparator set............................................................................................. 112
5.1.3.3 Interrupt priority mask update and restore mechanism....................................................................112
5.1.3.4 Integration and application of the IPC............................................................................................. 113
5.2 IRQ..................................................................................................................................................................................113
5.2.1 Features............................................................................................................................................................ 114
5.2.1.1 Pin configuration options.................................................................................................................114
5.2.1.2 Edge and level sensitivity................................................................................................................ 115
5.3 Interrupt pin request register...........................................................................................................................................115
5.3.1 Interrupt Pin Request Status and Control Register (IRQ_SC).........................................................................116
5.4 Interrupt priority control register.................................................................................................................................... 117
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5.4.1 IPC Status and Control Register (IPC_SC)......................................................................................................118
5.4.2 Interrupt Priority Mask Pseudo Stack Register (IPC_IPMPS)........................................................................ 119
5.4.3
Interrupt Level Setting Registers n (IPC_ILRSn)............................................................................................119
Chapter 6
System control
6.1 System device identification (SDID)..............................................................................................................................121
6.2 Universally unique identification (UUID)......................................................................................................................121
6.3 Reset and system initialization........................................................................................................................................121
6.4 System options................................................................................................................................................................122
6.4.1 BKGD pin enable.............................................................................................................................................122
6.4.2 RESET pin enable............................................................................................................................................122
6.4.3 SCI0 pin reassignment..................................................................................................................................... 122
6.4.4 FTM0 channels pin reassignment.................................................................................................................... 123
6.4.5 FTM2 channels pin reassignment.................................................................................................................... 123
6.4.6 Bus clock output pin enable.............................................................................................................................123
6.5 System interconnection...................................................................................................................................................123
6.5.1 SCI0 TxD modulation......................................................................................................................................124
6.5.2 SCI0 RxD capture............................................................................................................................................ 125
6.5.3 SCI0 RxD filter................................................................................................................................................ 125
6.5.4 ADC hardware trigger......................................................................................................................................125
6.6 System Control Registers................................................................................................................................................126
6.6.1 System Reset Status Register (SYS_SRS).......................................................................................................127
6.6.2 System Background Debug Force Reset Register (SYS_SBDFR)..................................................................128
6.6.3 System Device Identification Register: High (SYS_SDIDH)......................................................................... 129
6.6.4 System Device Identification Register: Low (SYS_SDIDL).......................................................................... 130
6.6.5 System Options Register 1 (SYS_SOPT1)...................................................................................................... 130
6.6.6 System Options Register 2 (SYS_SOPT2)...................................................................................................... 131
6.6.7 System Options Register 3 (SYS_SOPT3)...................................................................................................... 132
6.6.8 Illegal Address Register: High (SYS_ILLAH)................................................................................................133
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6.6.9 Illegal Address Register: Low (SYS_ILLAL).................................................................................................134
6.6.10 Universally Unique Identifier Register 1 (SYS_UUID1)................................................................................135
6.6.11 Universally Unique Identifier Register 2 (SYS_UUID2)................................................................................135
6.6.12 Universally Unique Identifier Register 3 (SYS_UUID3)................................................................................136
6.6.13 Universally Unique Identifier Register 4 (SYS_UUID4)................................................................................136
6.6.14 Universally Unique Identifier Register 5 (SYS_UUID5)................................................................................137
6.6.15 Universally Unique Identifier Register 6 (SYS_UUID6)................................................................................137
6.6.16 Universally Unique Identifier Register 7 (SYS_UUID7)................................................................................138
6.6.17 Universally Unique Identifier Register 8 (SYS_UUID8)................................................................................138
Chapter 7
Parallel input/output
7.1 Introduction.....................................................................................................................................................................139
7.2 Port data and data direction.............................................................................................................................................140
7.3 Internal pullup enable..................................................................................................................................................... 141
7.4 Input glitch filter setting..................................................................................................................................................141
7.5 Pin behavior in stop mode...............................................................................................................................................142
7.6 Port data registers............................................................................................................................................................142
7.6.1 Port A Data Register (PORT_PTAD)..............................................................................................................143
7.6.2 Port B Data Register (PORT_PTBD).............................................................................................................. 143
7.6.3 Port C Data Register (PORT_PTCD).............................................................................................................. 144
7.6.4 Port D Data Register (PORT_PTDD)..............................................................................................................144
7.6.5 Port E Data Register (PORT_PTED)...............................................................................................................145
7.6.6 Port A Output Enable Register (PORT_PTAOE)............................................................................................145
7.6.7 Port B Output Enable Register (PORT_PTBOE)............................................................................................ 147
7.6.8 Port C Output Enable Register (PORT_PTCOE)............................................................................................ 148
7.6.9 Port D Output Enable Register (PORT_PTDOE)............................................................................................149
7.6.10 Port E Output Enable Register (PORT_PTEOE).............................................................................................150
7.6.11 Port A Input Enable Register (PORT_PTAIE)................................................................................................151
7.6.12 Port B Input Enable Register (PORT_PTBIE)................................................................................................ 152
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7.6.13 Port C Input Enable Register (PORT_PTCIE)................................................................................................ 154
7.6.14 Port D Input Enable Register (PORT_PTDIE)................................................................................................155
7.6.15 Port E Input Enable Register (PORT_PTEIE).................................................................................................156
7.6.16 Port Filter Register 0 (PORT_IOFLT0)...........................................................................................................157
7.6.17 Port Filter Register 1 (PORT_IOFLT1)...........................................................................................................158
7.6.18 Port Filter Register 2 (PORT_IOFLT2)...........................................................................................................158
7.6.19 Port Clock Division Register (PORT_FCLKDIV).......................................................................................... 159
7.6.20 Port A Pullup Enable Register (PORT_PTAPE)............................................................................................. 160
7.6.21 Port B Pullup Enable Register (PORT_PTBPE)..............................................................................................161
7.6.22 Port C Pullup Enable Register (PORT_PTCPE)..............................................................................................163
7.6.23 Port D Pullup Enable Register (PORT_PTDPE)............................................................................................. 164
7.6.24 Port E Pullup Enable Register (PORT_PTEPE)..............................................................................................165
Chapter 8
Clock management
8.1 Clock module..................................................................................................................................................................167
8.2 Internal clock source (ICS)............................................................................................................................................. 167
8.2.1 Function description.........................................................................................................................................168
8.2.1.1 Bus frequency divider...................................................................................................................... 169
8.2.1.2 Low power bit usage........................................................................................................................169
8.2.1.3 Internal reference clock (ICSIRCLK)..............................................................................................169
8.2.1.4 Fixed frequency clock (ICSFFCLK)................................................................................................170
8.2.1.5 BDC clock........................................................................................................................................171
8.2.2 Modes of operation.......................................................................................................................................... 171
8.2.2.1 FLL engaged internal (FEI)............................................................................................................. 172
8.2.2.2 FLL engaged external (FEE)............................................................................................................173
8.2.2.3 FLL bypassed internal (FBI)............................................................................................................173
8.2.2.4 FLL bypassed internal low power (FBILP)..................................................................................... 173
8.2.2.5 FLL bypassed external (FBE)..........................................................................................................174
8.2.2.6 FLL bypassed external low power (FBELP)................................................................................... 174
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8.2.2.7 Stop (STOP).....................................................................................................................................175
8.2.3 FLL lock and clock monitor.............................................................................................................................176
8.2.3.1 FLL clock lock.................................................................................................................................176
8.2.3.2 External reference clock monitor.....................................................................................................176
8.3 Initialization / application information........................................................................................................................... 176
8.3.1 Initializing FEI mode....................................................................................................................................... 177
8.3.2 Initializing FBI mode.......................................................................................................................................177
8.3.3 Initializing FEE mode...................................................................................................................................... 177
8.3.4 Initializing FBE mode......................................................................................................................................178
8.3.5 External oscillator (OSC).................................................................................................................................178
8.3.5.1 Bypass mode.................................................................................................................................... 179
8.3.5.2 Low-power configuration................................................................................................................ 179
8.3.5.3 High-gain configuration...................................................................................................................180
8.3.5.4 Initializing external oscillator for peripherals..................................................................................180
8.4 1 kHz low-power oscillator (LPO)................................................................................................................................. 181
8.5 Peripheral clock gating................................................................................................................................................... 181
8.6 ICS control registers....................................................................................................................................................... 181
8.6.1 ICS Control Register 1 (ICS_C1).................................................................................................................... 182
8.6.2 ICS Control Register 2 (ICS_C2).................................................................................................................... 183
8.6.3 ICS Control Register 3 (ICS_C3).................................................................................................................... 184
8.6.4 ICS Control Register 4 (ICS_C4).................................................................................................................... 184
8.6.5 ICS Status Register (ICS_S)............................................................................................................................ 185
8.6.6 OSC Status and Control Register (ICS_OSCSC)............................................................................................ 186
8.7 System clock gating control registers............................................................................................................................. 187
8.7.1 System Clock Gating Control 1 Register (SCG_C1).......................................................................................188
8.7.2 System Clock Gating Control 2 Register (SCG_C2).......................................................................................189
8.7.3 System Clock Gating Control 3 Register (SCG_C3).......................................................................................190
8.7.4 System Clock Gating Control 4 Register (SCG_C4).......................................................................................190
Chapter 9
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Chip configurations
9.1 Introduction.....................................................................................................................................................................193
9.2 Core modules.................................................................................................................................................................. 193
9.2.1 Central processor unit (CPU)...........................................................................................................................193
9.2.2 Debug module (DBG)......................................................................................................................................193
9.3 System modules.............................................................................................................................................................. 194
9.3.1 Watchdog (WDOG)......................................................................................................................................... 194
9.4 Clock module..................................................................................................................................................................194
9.5 Memory...........................................................................................................................................................................194
9.5.1 Random-access-memory (RAM)..................................................................................................................... 194
9.5.2 Non-volatile memory (NVM).......................................................................................................................... 195
9.6 Power modules................................................................................................................................................................195
9.7 Security........................................................................................................................................................................... 195
9.7.1 Cyclic redundancy check (CRC)......................................................................................................................195
9.8 Timers............................................................................................................................................................................. 196
9.8.1 FlexTimer module (FTM)................................................................................................................................196
9.8.1.1 FTM0 interconnection......................................................................................................................196
9.8.1.2 FTM2 interconnection......................................................................................................................197
9.8.2 8-bit modulo timer (MTIM).............................................................................................................................197
9.8.2.1 MTIM0 as ADC hardware trigger................................................................................................... 197
9.8.3 Real-time counter (RTC)................................................................................................................................. 197
9.9 Communication interfaces.............................................................................................................................................. 198
9.9.1 Serial communications interface (SCI)............................................................................................................198
9.9.1.1 SCI0 infrared functions....................................................................................................................198
9.10 Analog.............................................................................................................................................................................199
9.10.1 Analog-to-digital converter (ADC)..................................................................................................................199
9.10.1.1 ADC block diagram......................................................................................................................... 199
9.10.1.2 ADC channel assignments............................................................................................................... 200
9.10.1.3 Alternate clock................................................................................................................................. 201
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9.10.1.4 Hardware trigger.............................................................................................................................. 202
9.10.1.5 Temperature sensor..........................................................................................................................202
9.10.2 Analog comparator (ACMP)............................................................................................................................203
9.10.2.1 ACMP configuration information....................................................................................................203
9.10.2.2 ACMP in stop3 mode.......................................................................................................................204
9.10.2.3 ACMP for SCI0 RXD filter............................................................................................................. 204
9.11 Human-machine interfaces HMI.....................................................................................................................................204
9.11.1 Keyboard interrupts (KBI)...............................................................................................................................204
Chapter 10
Central processor unit
10.1 Introduction.....................................................................................................................................................................205
10.1.1 Features............................................................................................................................................................ 205
10.2 Programmer's Model and CPU Registers....................................................................................................................... 206
10.2.1 Accumulator (A).............................................................................................................................................. 206
10.2.2 Index Register (H:X)........................................................................................................................................207
10.2.3 Stack Pointer (SP)............................................................................................................................................ 207
10.2.4 Program Counter (PC)..................................................................................................................................... 208
10.2.5 Condition Code Register (CCR)...................................................................................................................... 208
10.3 Addressing Modes.......................................................................................................................................................... 209
10.3.1 Inherent Addressing Mode (INH)....................................................................................................................210
10.3.2 Relative Addressing Mode (REL)....................................................................................................................210
10.3.3 Immediate Addressing Mode (IMM)...............................................................................................................210
10.3.4 Direct Addressing Mode (DIR)........................................................................................................................211
10.3.5 Extended Addressing Mode (EXT)..................................................................................................................211
10.3.6 Indexed Addressing Mode............................................................................................................................... 212
10.3.6.1 Indexed, No Offset (IX)...................................................................................................................212
10.3.6.2 Indexed, No Offset with Post Increment (IX+)................................................................................212
10.3.6.3 Indexed, 8-Bit Offset (IX1)..............................................................................................................212
10.3.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+).......................................................................... 213
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10.3.6.5 Indexed, 16-Bit Offset (IX2)............................................................................................................213
10.3.6.6 SP-Relative, 8-Bit Offset (SP1)....................................................................................................... 213
10.3.6.7 SP-Relative, 16-Bit Offset (SP2)..................................................................................................... 214
10.3.7 Memory to memory Addressing Mode............................................................................................................214
10.3.7.1 Direct to Direct.................................................................................................................................214
10.3.7.2 Immediate to Direct......................................................................................................................... 214
10.3.7.3 Indexed to Direct, Post Increment....................................................................................................214
10.3.7.4 Direct to Indexed, Post-Increment................................................................................................... 215
10.4 Operation modes............................................................................................................................................................. 215
10.4.1 Stop mode........................................................................................................................................................ 215
10.4.2 Wait mode........................................................................................................................................................215
10.4.3 Background mode............................................................................................................................................ 216
10.4.4 Security mode.................................................................................................................................................. 217
10.5 HCS08 V6 Opcodes........................................................................................................................................................219
10.6 Special Operations.......................................................................................................................................................... 219
10.6.1 Reset Sequence................................................................................................................................................ 219
10.6.2 Interrupt Sequence........................................................................................................................................... 219
10.7 Instruction Set Summary.................................................................................................................................................220
Chapter 11
Keyboard Interrupts (KBI)
11.1 Introduction.....................................................................................................................................................................233
11.1.1 Features............................................................................................................................................................ 233
11.1.2 Modes of Operation......................................................................................................................................... 233
11.1.2.1 KBI in Wait mode............................................................................................................................233
11.1.2.2 KBI in Stop modes...........................................................................................................................234
11.1.2.3 KBI in Active Background mode.....................................................................................................234
11.1.3 Block Diagram................................................................................................................................................. 234
11.2 External signals description............................................................................................................................................ 235
11.3 Register definition...........................................................................................................................................................235
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11.4 Memory Map and Registers............................................................................................................................................235
11.4.1
KBI Status and Control Register (KBIx_SC).................................................................................................. 236
11.4.2
KBI Pin Enable Register (KBIx_PE)...............................................................................................................237
11.4.3
KBI Edge Select Register (KBIx_ES)............................................................................................................. 237
11.5 Functional Description....................................................................................................................................................238
11.5.1 Edge-only sensitivity........................................................................................................................................238
11.5.2 Edge and level sensitivity................................................................................................................................ 238
11.5.3 KBI Pullup Resistor......................................................................................................................................... 239
11.5.4 KBI initialization..............................................................................................................................................239
Chapter 12
FlexTimer Module (FTM)
12.1 Introduction.....................................................................................................................................................................241
12.1.1 FlexTimer philosophy......................................................................................................................................241
12.1.2 Features............................................................................................................................................................ 241
12.1.3 Modes of operation.......................................................................................................................................... 242
12.1.4 Block diagram..................................................................................................................................................242
12.2 Signal description............................................................................................................................................................243
12.2.1 EXTCLK — FTM external clock.................................................................................................................... 244
12.2.2 CHn — FTM channel (n) I/O pin.................................................................................................................... 244
12.3 Memory map and register definition...............................................................................................................................244
12.3.1 Module memory map.......................................................................................................................................244
12.3.2 Register descriptions........................................................................................................................................244
12.3.3
Status and Control (FTMx_SC)....................................................................................................................... 246
12.3.4
Counter High (FTMx_CNTH)......................................................................................................................... 247
12.3.5
Counter Low (FTMx_CNTL).......................................................................................................................... 248
12.3.6
Modulo High (FTMx_MODH)........................................................................................................................ 248
12.3.7
Modulo Low (FTMx_MODL)......................................................................................................................... 249
12.3.8
Channel Status and Control (FTMx_CnSC).................................................................................................... 250
12.3.9
Channel Value High (FTMx_CnVH)...............................................................................................................251
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12.3.10
Channel Value Low (FTMx_CnVL)................................................................................................................252
12.4 Functional Description....................................................................................................................................................253
12.4.1 Clock Source....................................................................................................................................................253
12.4.1.1 Counter Clock Source...................................................................................................................... 253
12.4.2 Prescaler...........................................................................................................................................................254
12.4.3 Counter.............................................................................................................................................................254
12.4.3.1 Up counting......................................................................................................................................255
12.4.3.2 Up-down counting............................................................................................................................255
12.4.3.3 Free running counter........................................................................................................................ 256
12.4.3.4 Counter reset.................................................................................................................................... 256
12.4.4 Input capture mode...........................................................................................................................................256
12.4.5 Output compare mode......................................................................................................................................257
12.4.6 Edge-aligned PWM (EPWM) mode................................................................................................................ 259
12.4.7 Center-aligned PWM (CPWM) mode..............................................................................................................260
12.4.8 Update of the registers with write buffers........................................................................................................262
12.4.8.1 MODH:L registers........................................................................................................................... 262
12.4.8.2 CnVH:L registers............................................................................................................................. 263
12.4.9 BDM mode.......................................................................................................................................................263
12.5 Reset overview................................................................................................................................................................263
12.6 FTM Interrupts................................................................................................................................................................265
12.6.1 Timer overflow interrupt..................................................................................................................................265
12.6.2 Channel (n) interrupt........................................................................................................................................265
Chapter 13
8-bit modulo timer (MTIM)
13.1 Introduction.....................................................................................................................................................................267
13.2 Features...........................................................................................................................................................................267
13.3 Modes of operation......................................................................................................................................................... 267
13.3.1 MTIM in wait mode.........................................................................................................................................268
13.3.2 MTIM in stop mode......................................................................................................................................... 268
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13.3.3 MTIM in active background mode.................................................................................................................. 268
13.4 Block diagram.................................................................................................................................................................268
13.5 External signal description..............................................................................................................................................269
13.6 Register definition...........................................................................................................................................................269
13.6.1
MTIM Status and Control Register (MTIMx_SC).......................................................................................... 269
13.6.2
MTIM Clock Configuration Register (MTIMx_CLK).................................................................................... 270
13.6.3
MTIM Counter Register (MTIMx_CNT)........................................................................................................ 271
13.6.4
MTIM Modulo Register (MTIMx_MOD)....................................................................................................... 272
13.7 Functional description.....................................................................................................................................................272
13.7.1 MTIM operation example................................................................................................................................ 273
Chapter 14
Real-time counter (RTC)
14.1 Introduction.....................................................................................................................................................................275
14.2 Features...........................................................................................................................................................................275
14.2.1 Modes of operation.......................................................................................................................................... 275
14.2.1.1 Wait mode........................................................................................................................................275
14.2.1.2 Stop modes.......................................................................................................................................276
14.2.2 Block diagram..................................................................................................................................................276
14.3 External signal description..............................................................................................................................................276
14.4 Register definition...........................................................................................................................................................277
14.4.1 RTC Status and Control Register 1 (RTC_SC1)............................................................................................. 277
14.4.2 RTC Status and Control Register 2 (RTC_SC2)............................................................................................. 278
14.4.3 RTC Modulo Register: High (RTC_MODH).................................................................................................. 279
14.4.4 RTC Modulo Register: Low (RTC_MODL)................................................................................................... 279
14.4.5 RTC Counter Register: High (RTC_CNTH)................................................................................................... 280
14.4.6 RTC Counter Register: Low (RTC_CNTL).................................................................................................... 280
14.5 Functional description.....................................................................................................................................................281
14.5.1 RTC operation example................................................................................................................................... 282
14.6 Initialization/application information............................................................................................................................. 283
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Chapter 15
Serial communications interface (SCI)
15.1 Introduction.....................................................................................................................................................................285
15.1.1 Features............................................................................................................................................................ 285
15.1.2 Modes of operation.......................................................................................................................................... 285
15.1.3 Block diagram..................................................................................................................................................286
15.2 SCI signal descriptions................................................................................................................................................... 288
15.2.1 Detailed signal descriptions............................................................................................................................. 288
15.3 Register definition...........................................................................................................................................................288
15.3.1
SCI Baud Rate Register: High (SCIx_BDH)................................................................................................... 289
15.3.2
SCI Baud Rate Register: Low (SCIx_BDL).................................................................................................... 290
15.3.3
SCI Control Register 1 (SCIx_C1)...................................................................................................................291
15.3.4
SCI Control Register 2 (SCIx_C2)...................................................................................................................292
15.3.5
SCI Status Register 1 (SCIx_S1)..................................................................................................................... 293
15.3.6
SCI Status Register 2 (SCIx_S2)..................................................................................................................... 295
15.3.7
SCI Control Register 3 (SCIx_C3)...................................................................................................................297
15.3.8
SCI Data Register (SCIx_D)............................................................................................................................298
15.4 Functional description.....................................................................................................................................................299
15.4.1 Baud rate generation........................................................................................................................................ 299
15.4.2 Transmitter functional description...................................................................................................................300
15.4.2.1 Send break and queued idle............................................................................................................. 300
15.4.3 Receiver functional description....................................................................................................................... 301
15.4.3.1 Data sampling technique..................................................................................................................302
15.4.3.2 Receiver wake-up operation.............................................................................................................303
15.4.4 Interrupts and status flags................................................................................................................................ 304
15.4.5 Baud rate tolerance...........................................................................................................................................305
15.4.5.1 Slow data tolerance.......................................................................................................................... 306
15.4.5.2 Fast data tolerance............................................................................................................................307
15.4.6 Additional SCI functions................................................................................................................................. 308
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16 NXP Semiconductors
Section number Title Page
15.4.6.1 8- and 9-bit data modes....................................................................................................................308
15.4.6.2 Stop mode operation........................................................................................................................ 308
15.4.6.3 Loop mode....................................................................................................................................... 309
15.4.6.4 Single-wire operation.......................................................................................................................309
Chapter 16
Analog-to-digital converter (ADC)
16.1 Introduction.....................................................................................................................................................................311
16.1.1 Features............................................................................................................................................................ 311
16.1.2 Block Diagram................................................................................................................................................. 312
16.2 External Signal Description............................................................................................................................................ 312
16.2.1 Analog Power (VDDA)................................................................................................................................... 312
16.2.2 Analog Ground (VSSA)...................................................................................................................................312
16.2.3 Voltage Reference High (VREFH)..................................................................................................................312
16.2.4 Voltage Reference Low (VREFL)................................................................................................................... 313
16.2.5 Analog Channel Inputs (ADx)......................................................................................................................... 313
16.3 ADC Control Registers...................................................................................................................................................313
16.3.1 Status and Control Register 1 (ADC_SC1)......................................................................................................314
16.3.2 Status and Control Register 2 (ADC_SC2)......................................................................................................315
16.3.3 Status and Control Register 3 (ADC_SC3)......................................................................................................316
16.3.4 Status and Control Register 4 (ADC_SC4)......................................................................................................317
16.3.5 Conversion Result High Register (ADC_RH).................................................................................................318
16.3.6 Conversion Result Low Register (ADC_RL).................................................................................................. 319
16.3.7 Compare Value High Register (ADC_CVH)...................................................................................................320
16.3.8 Compare Value Low Register (ADC_CVL)....................................................................................................320
16.3.9 Pin Control 1 Register (ADC_APCTL1).........................................................................................................321
16.3.10 Pin Control 2 Register (ADC_APCTL2).........................................................................................................322
16.4 Functional description.....................................................................................................................................................323
16.4.1 Clock select and divide control........................................................................................................................323
16.4.2 Input select and pin control..............................................................................................................................324
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NXP Semiconductors 17
Section number Title Page
16.4.3 Hardware trigger.............................................................................................................................................. 324
16.4.4 Conversion control...........................................................................................................................................325
16.4.4.1 Initiating conversions.......................................................................................................................325
16.4.4.2 Completing conversions...................................................................................................................325
16.4.4.3 Aborting conversions....................................................................................................................... 326
16.4.4.4 Power control................................................................................................................................... 326
16.4.4.5 Sample time and total conversion time............................................................................................327
16.4.5 Automatic compare function............................................................................................................................328
16.4.6 FIFO operation.................................................................................................................................................329
16.4.7 MCU wait mode operation...............................................................................................................................332
16.4.8 MCU Stop mode operation.............................................................................................................................. 333
16.4.8.1 Stop mode with ADACK disabled...................................................................................................333
16.4.8.2 Stop mode with ADACK enabled....................................................................................................333
16.5 Initialization information................................................................................................................................................ 334
16.5.1 ADC module initialization example................................................................................................................ 334
16.5.1.1 Initialization sequence......................................................................................................................334
16.5.1.2 Pseudo-code example.......................................................................................................................335
16.5.2 ADC FIFO module initialization example.......................................................................................................335
16.5.2.1 Pseudo-code example.......................................................................................................................336
16.6 Application information..................................................................................................................................................337
16.6.1 External pins and routing................................................................................................................................. 337
16.6.1.1 Analog supply pins...........................................................................................................................337
16.6.1.2 Analog reference pins...................................................................................................................... 337
16.6.1.3 Analog input pins.............................................................................................................................338
16.6.2 Sources of error................................................................................................................................................339
16.6.2.1 Sampling error..................................................................................................................................339
16.6.2.2 Pin leakage error.............................................................................................................................. 339
16.6.2.3 Noise-induced errors........................................................................................................................339
16.6.2.4 Code width and quantization error...................................................................................................340
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16.6.2.5 Linearity errors.................................................................................................................................341
16.6.2.6 Code jitter, non-monotonicity, and missing codes...........................................................................341
Chapter 17
Analog comparator (ACMP)
17.1 Introduction.....................................................................................................................................................................343
17.1.1 Features............................................................................................................................................................ 343
17.1.2 Modes of operation.......................................................................................................................................... 343
17.1.2.1 Operation in Wait mode...................................................................................................................344
17.1.2.2 Operation in Stop mode................................................................................................................... 344
17.1.2.3 Operation in Debug mode................................................................................................................344
17.1.3 Block diagram..................................................................................................................................................344
17.2 External signal description..............................................................................................................................................345
17.3 Memory map and register definition...............................................................................................................................345
17.3.1 ACMP Control and Status Register (ACMP_CS)........................................................................................... 346
17.3.2 ACMP Control Register 0 (ACMP_C0).......................................................................................................... 347
17.3.3 ACMP Control Register 1 (ACMP_C1).......................................................................................................... 347
17.3.4 ACMP Control Register 2 (ACMP_C2).......................................................................................................... 348
17.4 Functional description.....................................................................................................................................................348
17.5 Setup and operation of ACMP........................................................................................................................................349
17.6 Resets..............................................................................................................................................................................350
17.7 Interrupts.........................................................................................................................................................................350
Chapter 18
Cyclic redundancy check (CRC)
18.1 Introduction.....................................................................................................................................................................351
18.2 Features...........................................................................................................................................................................351
18.3 Block diagram.................................................................................................................................................................351
18.4 Modes of operation......................................................................................................................................................... 352
18.5 Register definition...........................................................................................................................................................352
18.5.1 CRC Data 0 Register (CRC_D0)..................................................................................................................... 353
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Section number Title Page
18.5.2 CRC Data 1 Register (CRC_D1)..................................................................................................................... 353
18.5.3 CRC Data 2 Register (CRC_D2)..................................................................................................................... 354
18.5.4 CRC Data 3 Register (CRC_D3)..................................................................................................................... 355
18.5.5 CRC Polynomial 0 Register (CRC_P0)...........................................................................................................355
18.5.6 CRC Polynomial 1 Register (CRC_P1)...........................................................................................................356
18.5.7 CRC Polynomial 2 Register (CRC_P2)...........................................................................................................356
18.5.8 CRC Polynomial 3 Register (CRC_P3)...........................................................................................................357
18.5.9 CRC Control Register (CRC_CTRL).............................................................................................................. 357
18.6 Functional description.....................................................................................................................................................358
18.6.1 16-bit CRC calculation.....................................................................................................................................358
18.6.2 32-bit CRC calculation.....................................................................................................................................358
18.6.3 Bit reverse........................................................................................................................................................ 359
18.6.4 Result complement...........................................................................................................................................359
18.6.5 CCITT compliant CRC example......................................................................................................................359
Chapter 19
Watchdog (WDOG)
19.1 Introduction.....................................................................................................................................................................361
19.1.1 Features............................................................................................................................................................ 361
19.1.2 Block diagram..................................................................................................................................................362
19.2 Memory map and register definition...............................................................................................................................363
19.2.1 Watchdog Control and Status Register 1 (WDOG_CS1)................................................................................ 363
19.2.2 Watchdog Control and Status Register 2 (WDOG_CS2)................................................................................ 365
19.2.3 Watchdog Counter Register: High (WDOG_CNTH)......................................................................................366
19.2.4 Watchdog Counter Register: Low (WDOG_CNTL).......................................................................................366
19.2.5 Watchdog Timeout Value Register: High (WDOG_TOVALH)..................................................................... 367
19.2.6 Watchdog Timeout Value Register: Low (WDOG_TOVALL)...................................................................... 367
19.2.7 Watchdog Window Register: High (WDOG_WINH).....................................................................................368
19.2.8 Watchdog Window Register: Low (WDOG_WINL)...................................................................................... 368
19.3 Functional description.....................................................................................................................................................369
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20 NXP Semiconductors
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