NXP MPC821 User guide

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PowerPC

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MPC821

Portable Systems Microprocessor

User’s Manual

❊

In Memory of

Roland Hernandez

❊

MOTOROLA

MPC821 USER’S MANUAL

iii

TABLE OF CONTENTS

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Section 1

Overview

1.1 MPC821 Features ................................................................................1-1

1.2 MPC821 Architecture Overview ...........................................................1-4

1.3 Upgrading Designs From the MC68360 QUICC ..................................1-6

1.4 MPC821 Glueless System Design .......................................................1-6

Section 2

External Signals

2.1 Signals Description ...............................................................................2-1

2.1.1 System Bus Signals ...................................................................2-5

Section 3

Memory Map

Section 4

Reset

4.1 Reset Operation ...................................................................................4-1

4.1.1 Reset Causes .............................................................................4-1

4.1.1.1 Power-On Reset .............................................................4-1

4.1.1.2 Loss of Lock ....................................................................4-2

4.1.1.3 Software Watchdog Reset ..............................................4-2

4.1.1.4 Checkstop Reset ............................................................4-2

4.1.1.5 Debug Port Hard Reset ..................................................4-2

4.1.1.6 Debug Port Soft Reset ....................................................4-2

4.1.1.7 JTAG Reset ....................................................................4-2

4.1.2 Reset Actions .............................................................................4-3

4.1.3 Power-On Reset Flow ................................................................4-3

4.1.4 External HRESET

Flow ..............................................................4-3

4.1.5 Internal HRESET

Flow ...............................................................4-4

4.1.6 External SRESET

Flow ..............................................................4-4

4.1.7 Internal SRESET

Flow ...............................................................4-4

4.2 Reset Status Register ..........................................................................4-4

4.3 Reset Configuration ..............................................................................4-6

4.3.1 Hard Reset Configuration ...........................................................4-6

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4.3.1.1 Hard Reset Configuration Word ...................................4-10

4.3.2 Soft Reset Configuration ..........................................................4-11

Section 5

Clocks and Power Control

5.1 Overview ..............................................................................................5-1

5.2 Clock Unit Description ..........................................................................5-4

5.3 On-Chip Oscillators and External Clock Input ......................................5-7

5.4 System PLL ..........................................................................................5-8

5.4.1 Frequency Multiplication ............................................................5-8

5.4.2 Skew Elimination ........................................................................5-8

5.4.3 PLL Block Diagram ....................................................................5-8

5.5 Low Power Divider ...............................................................................5-9

5.6 Internal Clock Signals ..........................................................................5-9

5.6.1 General System Clocks ............................................................5-10

5.7 PLL Pins .............................................................................................5-14

5.8 System Clock Control .........................................................................5-15

5.9 PLL, Low Power, and Reset Control Register ....................................5-19

5.10 Basic Power Structure ........................................................................5-24

5.11 Keep Alive Power ...............................................................................5-25

5.11.1 Keep Alive Power Configuration ..............................................5-25

5.11.2 Keep Alive Power Registers Lock Mechanism .........................5-26

Section 6

Core

6.1 Overview ..............................................................................................6-1

6.2 Features ...............................................................................................6-1

6.2.1 General Core Structure ..............................................................6-2

6.2.2 Instruction Flow Within the Core ................................................6-2

6.2.3 Basic Instruction Pipeline ...........................................................6-4

6.3 Sequencer Unit ....................................................................................6-4

6.3.1 Overview ....................................................................................6-4

6.3.2 Flow Control ...............................................................................6-4

6.3.3 Instruction Issue .........................................................................6-6

6.3.4 Interrupts ....................................................................................6-6

6.3.5 Precise Exception Model Implementation ..................................6-8

6.3.5.1 Restartability After An Interrupt ......................................6-9

6.3.6 Interrupt Timing ........................................................................6-11

6.3.7 Serialization ..............................................................................6-12

6.3.7.1 Serialization Latency ....................................................6-12

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6.3.8 External Interrupt ......................................................................6-12

6.3.8.1 External Interrupt Latency ............................................6-12

6.3.9 Interrupt Ordering .....................................................................6-13

6.4 Register Unit ......................................................................................6-14

6.4.1 Control Registers .....................................................................6-15

6.4.1.1 Physical Location of Special Registers .........................6-18

6.4.1.2 Control Registers Bit Assignment .................................6-20

6.4.1.3 Initialization of Control Registers ..................................6-21

6.5 Fixed-Point Unit ..................................................................................6-22

6.5.1 XER Update In Divide Instructions ...........................................6-22

6.6 Load/Store Unit ..................................................................................6-22

6.6.1 Load/Store Instruction Issue ....................................................6-24

6.6.2 Load/Store Synchronizing Instructions .....................................6-25

6.6.3 Instructions Issued to the Data Cache .....................................6-25

6.6.4 Store Instructions Cycles Issue ................................................6-25

6.6.5 Nonspeculative Load Instructions ............................................6-25

6.6.6 Unaligned Instructions Execution .............................................6-26

6.6.7 Little Endian Support ................................................................6-26

6.6.8 Atomic Update Primitives .........................................................6-27

6.6.9 Instruction Timing .....................................................................6-27

6.6.10 Storage Control Instructions Stall .............................................6-28

6.6.11 Off-Core Special Registers Access ..........................................6-28

6.6.12 Storage Control Instructions .....................................................6-28

6.6.13 Exceptions ................................................................................6-28

6.6.13.1 DAR, DSISR, and BAR Operation ................................6-28

Section 7

PowerPC Architecture Compliance

7.1 PowerPC User Instruction Set Architecture (Book I) ............................7-1

7.1.1 Computation Modes ...................................................................7-1

7.1.2 Reserved Fields .........................................................................7-1

7.1.3 Classes of Instructions ...............................................................7-1

7.1.4 Exceptions ..................................................................................7-2

7.1.5 The Branch Processor ...............................................................7-2

7.1.6 Instruction Fetching ....................................................................7-2

7.1.7 Branch Instructions ....................................................................7-2

7.1.7.1 Invalid Branch Instruction Forms ....................................7-2

7.1.7.2 Branch Prediction ...........................................................7-2

7.1.8 The Fixed-Point Processor .........................................................7-2

7.1.8.1 Fixed-Point Instructions ..................................................7-2

7.1.9 Load/Store Processor ................................................................7-3

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7.1.9.1 Fixed-Point Load With Update and Store With

Update Instructions .........................................................7-3

7.1.9.2 Fixed-Point Load and Store Multiple Instructions ...........7-3

7.1.9.3 Fixed-Point Load String Instructions ...............................7-3

7.1.9.4 Storage Synchronization Instructions .............................7-3

7.1.9.5 Optional Instructions .......................................................7-3

7.1.9.6 Little-Endian Byte Ordering ............................................7-4

7.2 PowerPC Virtual Environment Architecture (Book II) ...........................7-4

7.2.1 Storage Model ............................................................................7-4

7.2.1.1 Memory Coherence ........................................................7-4

7.2.1.2 Atomic Update Primitives ...............................................7-4

7.2.2 Effect of Operand Placement on Performance ..........................7-4

7.2.3 Storage Control Instructions .......................................................7-5

7.2.3.1 Instruction Cache Block Invalidate (icbi) Instruction .......7-5

7.2.3.2 Instruction Synchronize (isync) Instruction .....................7-5

7.2.3.3 Data Cache Block Touch (dcbt) Instruction ....................7-5

7.2.3.4 Data Cache Block Touch for Store (dcbtst) Instruction ..7-5

7.2.3.5 Data Cache Block Set to Zero (dcbz) Instruction ...........7-5

7.2.3.6 Data Cache Block Store (dcbst) Instruction ....................7-5

7.2.3.7 Data Cache Block Invalidate (dcbi) Instruction ...............7-5

7.2.3.8 Data Cache Block Flush (dcbf) Instruction .....................7-5

7.2.3.9 Enforce In-Order Execution of I/O (eieio) Instruction ......7-5

7.2.4 Timebase ...................................................................................7-5

7.3 PowerPC Operating Environment Architecture (Book III) ....................7-6

7.3.1 Branch Processor .......................................................................7-6

7.3.1.1 Branch Processor Registers ...........................................7-6

7.3.1.2 Branch Processors Instructions ......................................7-6

7.3.2 Fixed-Point Processor ................................................................7-6

7.3.2.1 Special Purpose Registers .............................................7-6

7.3.3 Storage Model ............................................................................7-7

7.3.3.1 Address Translation ........................................................7-7

7.3.4 Reference and Change Bits .......................................................7-7

7.3.5 Storage Protection .....................................................................7-7

7.3.6 Storage Control Instructions .......................................................7-7

7.3.6.1 Data Cache Block Invalidate (dcbi) Instruction ...............7-7

7.3.6.2 TLB Invalidate Entry (tlbie) Instruction ............................7-7

7.3.6.3 TLB Invalidate All (tlbia) Instruction ................................7-7

7.3.6.4 TLB Synchronize (tlbsync) Instruction ............................7-8

7.3.7 Interrupts ....................................................................................7-8

7.3.7.1 Interrupt Classes ............................................................7-8

7.3.7.2 Interrupt Processing .......................................................7-8

7.3.7.3 Interrupt Definitions ........................................................7-8

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7.3.7.4 Partially Executed Instructions .....................................7-17

7.3.8 Timer Facilities .........................................................................7-17

7.3.9 Optional Facilities and Instructions ..........................................7-17

Section 8

Instruction Execution Timing

8.1 Instructions Timing List ........................................................................8-1

8.2 Instruction Execution Timing Examples ...............................................8-4

8.2.1 Load From Data Cache Example ...............................................8-4

8.2.2 Writeback Examples ..................................................................8-5

8.2.2.1 Writeback Arbitration Examples .....................................8-5

8.2.2.2 Load Private Writeback Bus ...........................................8-6

8.2.3 Fastest External Load (Data Cache Miss) Example ..................8-7

8.2.4 History Buffer Full Example ........................................................8-8

8.2.5 Branch Folding Example ............................................................8-9

8.2.6 Branch Prediction Example ......................................................8-10

Section 9

Instruction Cache

9.1 Overview ..............................................................................................9-1

9.2 Features ...............................................................................................9-1

9.3 Programming Model .............................................................................9-4

9.4 Instruction Cache Regular Operation ...................................................9-5

9.4.1 Instruction Cache Hit ..................................................................9-5

9.4.2 Instruction Cache Miss ...............................................................9-5

9.4.3 Instruction Fetch On A Predicted Path .......................................9-6

9.5 Instruction Cache Commands ..............................................................9-6

9.5.1 Instruction Cache Invalidate Commands ...................................9-7

9.5.1.1 Instruction Cache Block Invalidate .................................9-7

9.5.1.2 Invalidate All Instruction Cache ......................................9-7

9.5.2 Load & Lock ...............................................................................9-7

9.5.3 Unlock Line ................................................................................9-8

9.5.4 Unlock All ...................................................................................9-8

9.5.5 Instruction Cache Inhibit .............................................................9-8

9.5.6 Instruction Cache Read ..............................................................9-9

9.5.7 Instruction Cache Write ............................................................9-10

9.6 Restrictions ........................................................................................9-10

9.7 Instruction Cache Coherency .............................................................9-10

9.8 Updating Code And Memory Regions Attributes ...............................9-10

9.9 Reset Sequence .................................................................................9-11

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9.10 Debug Support ...................................................................................9-11

9.10.1 General ....................................................................................9-11

9.10.2 Instruction Fetch From The Development Port ........................9-11

Section 10

Data Cache

10.1 Overview ............................................................................................10-1

10.2 Features .............................................................................................10-1

10.3 Data Cache Organization ...................................................................10-2

10.4 Programming Model ...........................................................................10-3

10.4.1 PowerPC Architecture Instructions ..........................................10-3

10.4.2 Implementation Specific Operations ........................................10-3

10.4.3 Data Cache Special Registers .................................................10-3

10.5 Data Cache Operation .......................................................................10-6

10.5.1 Data Cache Read .....................................................................10-6

10.5.2 Data Cache Write .....................................................................10-7

10.5.3 Data Cache-Inhibited Accesses ...............................................10-8

10.5.4 Data Cache Freeze ..................................................................10-8

10.5.5 Data Cache Coherency Support ..............................................10-9

10.6 Data Cache Control ............................................................................10-9

10.6.1 Data Cache Flushing And Invalidation .....................................10-9

10.6.2 Data Cache Disabling ..............................................................10-9

10.6.3 Data Cache Locking ...............................................................10-10

10.6.4 Data Cache Control Instructions ............................................10-10

10.6.4.1 dcbi, dcbst, dcbf And dcbz Instructions ......................10-10

10.6.4.2 Touch Instructions ......................................................10-10

10.6.4.3 Storage Synchronization/Reservation

Implementation ...........................................................10-10

10.6.5 Data Cache Structures Read .................................................10-10

Section 11

Memory Management Unit

11.1 Overview ............................................................................................11-1

11.2 Features .............................................................................................11-1

11.3 Address Translation ...........................................................................11-2

11.3.1 Translation Lookaside Buffer Operation ...................................11-3

11.3.1.1 MainStream Operation .................................................11-3

11.4 Protection ...........................................................................................11-4

11.5 Storage Attributes ..............................................................................11-4

11.5.1 Reference and Change Bit Updates ........................................11-4

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11.5.2 Storage Control Attributes ........................................................11-5

11.6 Translation Table Structure ................................................................11-5

11.6.1 Level One Descriptor ...............................................................11-9

11.6.2 Level Two Descriptor ...............................................................11-9

11.7 Programming Model .........................................................................11-12

11.8 Memory Management Unit Interrupts ...............................................11-29

11.8.1 Implementation Specific Instruction TLB Miss Interrupt .........11-29

11.8.2 Implementation Specific Data TLB Miss Interrupt ..................11-29

11.8.3 Implementation Specific Instruction TLB Error Interrupt ........11-30

11.8.4 Implementation Specific Data TLB Error Interrupt .................11-30

11.9 TLB Manipulation .............................................................................11-30

11.9.1 TLB Reload ............................................................................11-30

11.9.1.1 Translation Reload Examples .....................................11-31

11.9.2 TLB Replacement Counter .....................................................11-32

11.9.3 TLB Invalidation .....................................................................11-32

11.9.4 Loading the Reserved TLB Entries ........................................11-32

11.10 Requirements For Accessing The MMU Control Registers .............11-33

Section 12

System Interface Unit

12.1 Introduction ........................................................................................12-1

12.2 System Configuration and Protection .................................................12-2

12.2.1 System Configuration ...............................................................12-3

12.2.1.1 SIU Interrupt Configuration ...........................................12-3

12.2.1.2 SIU Interrupt Sources Priority .......................................12-4

12.2.1.3 SIU Interrupt Controller Programming Model ...............12-5

12.2.2 Bus Monitor ..............................................................................12-8

12.2.3 PowerPC Decrementer ............................................................12-8

12.2.4 PowerPC Timebase .................................................................12-9

12.2.5 Real-Time Clock .....................................................................12-10

12.2.6 Periodic Interrupt Timer ..........................................................12-11

12.2.7 Software Watchdog Timer ......................................................12-12

12.2.8 Freeze Operation ...................................................................12-13

12.2.9 Low Power Stop Operation ....................................................12-13

12.3 SIU Pins Multiplexing .......................................................................12-14

12.4 Programming Model .........................................................................12-15

12.4.1 System Configuration and Protection Registers ....................12-15

12.4.1.1 SIU Module Configuration Register ............................12-15

12.4.1.2 Internal Memory Map Register ...................................12-19

12.4.1.3 System Protection Control Register ...........................12-20

12.4.1.4 Software Service Register ..........................................12-21

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12.4.1.5 Transfer Error Status Register ....................................12-22

12.4.2 System Timer Registers .........................................................12-23

12.4.3 Decrementer Register ............................................................12-23

12.4.4 Timebase Registers ...............................................................12-23

12.4.4.1 Timebase Register .....................................................12-23

12.4.4.2 Timebase Reference Registers ..................................12-23

12.4.4.3 Timebase Control and Status Register .......................12-24

12.4.5 Real-Time Clock Registers ....................................................12-25

12.4.5.1 Real-Time Clock Status and Control Register ............12-25

12.4.5.2 Real-Time Clock Register............................................12-26

12.4.5.3 Real-Time Clock Alarm Register ................................12-26

12.4.6 Periodic Interrupt Registers ....................................................12-27

12.4.6.1 Periodic Interrupt Status and Control Register ...........12-27

12.4.6.2 Periodic Interrupt Timer Count ...................................12-28

12.4.6.3 Periodic Interrupt Timer Register ................................12-28

Section 13

External Bus Interface

13.1 Overview ............................................................................................13-1

13.2 Features .............................................................................................13-1

13.3 Bus Transfer Signals ..........................................................................13-1

13.3.1 Bus Control Signals ..................................................................13-2

13.4 Bus Interface Signal Descriptions ......................................................13-4

13.5 Bus Operations ..................................................................................13-8

13.5.1 Basic Transfer Protocol ............................................................13-9

13.5.2 Single Beat Transfer ................................................................13-9

13.5.2.1 Single Beat Read Flow ...............................................13-10

13.5.2.2 Single Beat Write Flow ...............................................13-13

13.5.3 Burst Transfer ........................................................................13-16

13.5.4 Burst Mechanism ...................................................................13-17

13.5.5 Alignment and Packaging on Transfers .................................13-26

13.5.6 Arbitration Phase ....................................................................13-29

13.5.6.1 Bus Request ...............................................................13-30

13.5.6.2 Bus Grant ...................................................................13-30

13.5.6.3 Bus Busy ....................................................................13-31

13.5.7 Address Transfer Phase-Related Signals ..............................13-33

13.5.7.1 Transfer Start ..............................................................13-33

13.5.7.2 Address Bus ...............................................................13-34

13.5.7.3 Transfer Attributes ......................................................13-34

13.5.8 Termination Signals ...............................................................13-38

13.5.8.1 Transfer Acknowledge ................................................13-38

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13.5.8.2 Burst Inhibit .................................................................13-38

13.5.8.3 Transfer Error Acknowledge .......................................13-38

13.5.8.4 Termination Signals Protocol ......................................13-38

13.5.9 Storage Reservation ..............................................................13-40

13.5.10 Bus Exception Control Cycles ................................................13-43

13.5.10.1 RETRY .......................................................................13-43

Section 14

Endian Modes

14.1 Overview ............................................................................................14-1

14.2 Little Endian Features ........................................................................14-3

14.3 Big-Endian System Features .............................................................14-5

14.4 PowerPC Little-Endian System Features ...........................................14-5

14.5 Setting Endian Mode Of Operation ....................................................14-5

Section 15

Memory Controller

15.1 Introduction ........................................................................................15-1

15.2 Features .............................................................................................15-1

15.3 Memory Controller Architecture .........................................................15-4

15.3.1 General Overview ....................................................................15-4

15.3.1.1 Associated Registers ....................................................15-7

15.3.1.2 8-, 16-, and 32-Bit Port Size Configuration ...................15-8

15.3.1.3 Write-Protect Configuration ..........................................15-8

15.3.1.4 Address and Address Space Checking ........................15-8

15.3.1.5 Parity Generation and Checking ...................................15-8

15.3.1.6 Transfer Error Acknowledge Generation ......................15-8

15.3.2 General-Purpose Chip-Select Machine ....................................15-8

15.3.2.1 Programmable Wait State Configuration ....................15-15

15.3.2.2 Extended Hold Time on Read Accesses ....................15-15

15.3.2.3 Global (boot) Chip-Select Operation ..........................15-19

15.3.2.4 SRAM Interface ..........................................................15-20

15.3.2.5 GPCM- External Asynchronous Master Support ........15-21

15.4 User-Programmable Machine ..........................................................15-23

15.4.0.6 RAM Word Structure and Timing Specification ..........15-29

15.4.0.7 CS Lines .....................................................................15-32

15.4.0.8 Byte Selects ................................................................15-33

15.4.0.9 General-Purpose Lines ...............................................15-34

15.4.0.10 Loop Control Bit ..........................................................15-35

15.4.0.11 Exception Handling .....................................................15-35

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15.4.0.12 Address Control Bits ...................................................15-36

15.4.0.13 Disable Timer Mechanism ..........................................15-39

15.4.0.14 Transfer Acknowledge And Data Sample Control ......15-40

15.4.0.15 WAIT Mechanism .......................................................15-41

15.4.0.16 Last Bit ........................................................................15-42

15.4.0.17 UPM Start Addresses Location ..................................15-43

15.4.0.18 Example DRAM Interface ...........................................15-43

15.4.0.19 EDO Interface Example ..............................................15-56

15.5 Memory Controller External Master Support ....................................15-63

15.6 Programming Model .........................................................................15-71

Section 16

Communication Processor Module

16.1 Introduction ........................................................................................16-1

16.2 Features .............................................................................................16-1

16.3 Serial Configurations ..........................................................................16-3

16.4 RISC Microcontroller ..........................................................................16-4

16.4.1 Overview ..................................................................................16-4

16.4.2 Features ...................................................................................16-5

16.4.3 CPU Interface ...........................................................................16-6

16.4.4 Peripheral Interface ..................................................................16-6

16.4.5 Execution From RAM ...............................................................16-7

16.4.6 RISC Controller Configuration Register ...................................16-7

16.4.7 RISC Microcode Revision Number ..........................................16-9

16.5 Command Set ....................................................................................16-9

16.5.1 CPM Command Register .........................................................16-9

16.5.2 Command Register Examples ...............................................16-13

16.5.3 Command Execution Latency ................................................16-13

16.6 Dual-Port RAM .................................................................................16-13

16.6.1 Buffer Descriptors ..................................................................16-15

16.6.2 Parameter RAM .....................................................................16-15

16.7 RISC Timer Tables ...........................................................................16-17

16.7.1 RISC Timer Table Parameter RAM ........................................16-17

16.7.2 RISC Timer Table Entries ......................................................16-20

16.7.3 PWM Mode ............................................................................16-20

16.7.4 RISC Timer Event Register ....................................................16-21

16.7.5 RISC Timer Mask Register ....................................................16-21

16.7.6 SET TIMER Command ..........................................................16-21

16.7.7 RISC Timer Initialization Sequence .......................................16-22

16.7.8 RISC Timer Initialization Example ..........................................16-22

16.7.9 RISC Timer Interrupt Handling ...............................................16-23

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16.7.10 RISC Timer Table Algorithm ..................................................16-23

16.7.11 RISC Timer Table Application: Track the RISC Loading .......16-23

16.8 Digital Signal Processing Capabilities ..............................................16-24

16.8.1 Features .................................................................................16-24

16.8.2 DSP Functionality Overview ...................................................16-25

16.8.2.1 The Hardware .............................................................16-25

16.8.2.2 The Firmware .............................................................16-25

16.8.3 Programming Model ...............................................................16-26

16.8.3.1 Data Representation ...................................................16-27

16.8.3.2 Modulo Addressing .....................................................16-28

16.8.3.3 DSP Function Descriptor ............................................16-28

16.8.3.4 DSP Parameter RAM .................................................16-29

16.8.3.5 DSP Command Set ....................................................16-30

16.8.3.6 DSP Event Register ....................................................16-30

16.8.3.7 DSP Mask Register ....................................................16-31

16.8.4 Example of DSP Implementation ...........................................16-31

16.8.4.1 CPU Only Implementation ..........................................16-32

16.8.4.2 CPU+CPM Implementation ........................................16-33

16.8.5 FIR1–Real C, Real X, and Real Y ..........................................16-34

16.8.5.1 Description ..................................................................16-34

16.8.5.2 Coefficients and Sample Data Buffers ........................16-34

16.8.5.3 FIR1 Function Descriptor ............................................16-35

16.8.5.4 FIR1 Parameter Packet ..............................................16-36

16.8.5.5 Applications ................................................................16-37

16.8.6 FIR2–Real C, Complex X, and Complex Y ............................16-37

16.8.6.1 Description ..................................................................16-37

16.8.6.2 Coefficients and Sample Data Buffers ........................16-37

16.8.6.3 FIR2 Function Descriptor ............................................16-38

16.8.6.4 FIR2 Parameter Packet ..............................................16-39

16.8.6.5 Applications ................................................................16-40

16.8.7 FIR3–Complex C, Complex X, and Real/Complex Y .............16-40

16.8.7.1 Description ..................................................................16-40

16.8.7.2 Coefficients and Sample Data Buffers ........................16-40

16.8.7.3 FIR3 Function Descriptor ............................................16-41

16.8.7.4 FIR3 Parameter Packet ..............................................16-43

16.8.7.5 Applications ................................................................16-43

16.8.8 FIR5–Complex C, Complex X, and Complex Y .....................16-44

16.8.8.1 Description ..................................................................16-44

16.8.8.2 Coefficients and Sample Data Buffers ........................16-44

16.8.8.3 FIR5 Function Descriptor ............................................16-45

16.8.8.4 FIR5 Parameter Packet ..............................................16-47

16.8.8.5 Applications ................................................................16-47

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16.8.9 FIR6–Complex C, Real X, and Complex Y ............................16-48

16.8.9.1 Description ..................................................................16-48

16.8.9.2 Coefficients and Sample Data Buffers ........................16-48

16.8.9.3 FIR6 Function Descriptor ............................................16-49

16.8.9.4 FIR6 Parameter Packet ..............................................16-51

16.8.10 IIR–Real C, Real X, Real Y ....................................................16-51

16.8.10.1 Description ..................................................................16-51

16.8.10.2 Coefficients and Sample Data Buffers ........................16-51

16.8.10.3 IIR Function Descriptor ...............................................16-52

16.8.10.4 Applications ................................................................16-53

16.8.11 MOD–Real Sin, Real Cos, Complex X, and

Real/Complex Y ......................................................................16-54

16.8.11.1 Description ..................................................................16-54

16.8.11.2 Modulation Table and Sample Data Buffers ...............16-54

16.8.11.3 MOD Function Descriptor ...........................................16-55

16.8.11.4 MOD Parameter Packet .............................................16-56

16.8.11.5 Applications ................................................................16-56

16.8.12 DEMOD–Real Sin; Real Cos, Real X, Complex Y .................16-56

16.8.12.1 Description ..................................................................16-56

16.8.12.2 Modulation Table, Sample Data Buffers, and

AGC Constant ............................................................16-57

16.8.12.3 DEMOD Function Descriptor ......................................16-57

16.8.12.4 DEMOD Parameter Packet ........................................16-58

16.8.12.5 Applications ................................................................16-58

16.8.13 LMS1–Complex Coefficients, Complex Samples,

and Real/Complex Scalar .......................................................16-59

16.8.13.1 Description ..................................................................16-59

16.8.13.2 Coefficients and Sample Data Buffers ........................16-59

16.8.13.3 LMS1 Function Descriptor ..........................................16-60

16.8.13.4 LMS1 Parameter Packet ............................................16-61

16.8.13.5 Applications ................................................................16-61

16.8.14 LMS2–Complex Coefficients, Complex Samples,

and Real/Complex Scalar .......................................................16-61

16.8.14.1 Description ..................................................................16-61

16.8.14.2 Coefficients and Sample Data Buffers ........................16-62

16.8.14.3 LMS2 Function Descriptor ..........................................16-62

16.8.14.4 LMS2 Parameter Packet ............................................16-63

16.8.14.5 Applications ................................................................16-64

16.8.15 Weighted Vector Addition (WADD)–Real X, Real Y ...............16-64

16.8.15.1 Description ..................................................................16-64

16.8.15.2 Coefficients and Sample Data Buffers ........................16-64

16.8.15.3 WADD Function Descriptor ........................................16-65

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16.8.15.4 WADD Parameter Packet ...........................................16-66

16.8.15.5 Applications ................................................................16-66

16.8.16 DSP Execution Times ............................................................16-67

16.9 Timers ..............................................................................................16-67

16.9.1 Features .................................................................................16-68

16.9.2 General-Purpose Timer Units ................................................16-69

16.9.2.1 Cascaded Mode .........................................................16-70

16.9.2.2 Timer Global Configuration Register ..........................16-71

16.9.2.3 Timer Mode Register ..................................................16-72

16.9.2.4 Timer Reference Registers .........................................16-73

16.9.2.5 Timer Capture Registers ............................................16-73

16.9.2.6 Timer Counter .............................................................16-73

16.9.2.7 Timer Event Registers ................................................16-74

16.9.3 Timer Examples .....................................................................16-74

16.10 SDMA Channels ...............................................................................16-75

16.10.1 SDMA Bus Arbitration and Bus Transfers ..............................16-77

16.10.2 SDMA Registers .....................................................................16-77

16.10.2.1 SDMA Configuration Register ....................................16-78

16.10.2.2 SDMA Status Register ................................................16-79

16.10.2.3 SDMA Mask Register .................................................16-80

16.10.2.4 SDMA Address Register .............................................16-80

16.11 IDMA Emulation ...............................................................................16-80

16.11.1 Features .................................................................................16-80

16.11.2 IDMA Interface Signals ..........................................................16-81

16.11.2.1 DREQ and SDACK .....................................................16-81

16.11.3 IDMA Operation .....................................................................16-81

16.11.3.1 Auto Buffer and Buffer Chaining .................................16-82

16.11.3.2 IDMA Parameter RAM ................................................16-83

16.11.3.3 DMA Channel Mode Register .....................................16-84

16.11.3.4 IDMA Status Register .................................................16-85

16.11.3.5 IDMA Mask Register ...................................................16-85

16.11.3.6 IDMA Buffer Descriptors .............................................16-86

16.11.3.7 IDMA Commands .......................................................16-90

16.11.3.8 Starting the IDMA. ......................................................16-90

16.11.3.9 Requesting IDMA Transfers .......................................16-90

16.11.3.10 Level-Sensitive Mode .................................................16-90

16.11.3.11 Edge-Sensitive Mode .................................................16-91

16.11.3.12 IDMA Operand Transfers ...........................................16-91

16.11.3.13 Single Address Mode .................................................16-92

16.11.3.14 Bus Exceptions ...........................................................16-94

16.12 Serial Interface with Time-Slot Assigner ..........................................16-95

16.12.1 Features .................................................................................16-97

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16.12.2 Overview ................................................................................16-97

16.12.3 Enabling Connections to the Time-Slot Assigner .................16-101

16.12.4 Serial Interface RAM ............................................................16-101

16.12.4.1 One Multiplexed Channel with Static Frames ...........16-102

16.12.4.2 One Multiplexed Channel With Dynamic Frames .....16-103

16.12.4.3 Two Multiplexed Channels With Static Frames ........16-104

16.12.4.4 Two Multiplexed Channels With Dynamic Frames....16-105

16.12.4.5 Programming SI RAM Entries ..................................16-106

16.12.4.6 SI RAM Programming Example ................................16-108

16.12.4.7 SI RAM Dynamic Changes .......................................16-109

16.12.5 Serial Interface Registers .....................................................16-112

16.12.5.1 SI Global Mode Register ..........................................16-112

16.12.5.2 SI Mode Register ......................................................16-113

16.12.5.3 SI Clock Route Register ...........................................16-120

16.12.5.4 SI Command Register ..............................................16-121

16.12.5.5 SI Status Register .....................................................16-122

16.12.5.6 SI RAM Pointers .......................................................16-123

16.12.6 Serial Interface IDL Interface Support ..................................16-125

16.12.6.1 IDL Interface Example ..............................................16-126

16.12.6.2 IDL Interface Programming ......................................16-129

16.12.7 Serial Interface GCI Support ................................................16-131

16.12.7.1 SI GCI Activation/Deactivation Procedure ................16-133

16.12.7.2 Serial Interface GCI Programming ...........................16-133

16.12.8 NMSI Configuration ..............................................................16-135

16.13 Baud Rate Generators ...................................................................16-138

16.13.1 Autobaud Support ................................................................16-139

16.13.2 Baud Rate Generator Configuration Register ......................16-140

16.13.3 UART Baud Rate Examples .................................................16-142

16.14 Serial Communication Controllers ..................................................16-145

16.14.1 Overview ..............................................................................16-146

16.14.2 General SCC Mode Register ...............................................16-147

16.14.2.1 General SCC Mode Register High ...........................16-147

16.14.2.2 General SCC Mode Register Low ............................16-152

16.14.3 SCC Protocol-Specific Mode Register .................................16-158

16.14.4 SCC Data Synchronization Register ....................................16-158

16.14.5 SCC Transmit-on-Demand Register ....................................16-158

16.14.6 SCC Buffer Descriptors ........................................................16-159

16.14.7 SCC Parameter RAM ...........................................................16-162

16.14.7.1 Buffer Descriptor Table Pointer ................................16-163

16.14.7.2 SCC Function Code Registers .................................16-164

16.14.7.3 Maximum Receive Buffer Length Register ...............16-165

16.14.7.4 Receiver BD Pointer .................................................16-166

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16.14.7.5 Transmitter BD Pointer .............................................16-166

16.14.7.6 Other General Parameters .......................................16-166

16.14.8 Interrupts from the SCCs .....................................................16-167

16.14.8.1 SCC Event Register .................................................16-167

16.14.8.2 SCC Mask Register ..................................................16-167

16.14.8.3 SCC Status Register ................................................16-167

16.14.9 SCC Initialization ..................................................................16-168

16.14.10 SCC Interrupt Handling ........................................................16-168

16.14.11 SCC Timing Control .............................................................16-169

16.14.11.1 Synchronous Protocols .............................................16-169

16.14.11.2 Asynchronous Protocols ...........................................16-172

16.14.12 Digital Phase-Locked Loop ..................................................16-173

16.14.12.1 Data Encoding ..........................................................16-173

16.14.12.2 DPLL Operation ........................................................16-174

16.14.12.3 Serial Infra-Red Encoder/Decoder ...........................16-177

16.14.13 Clock Glitch Detection ..........................................................16-178

16.14.14 Disabling the SCCs On-the-Fly ............................................16-178

16.14.14.1 SCC Transmitter Full Sequence ...............................16-179

16.14.14.2 SCC Transmitter Shortcut Sequence .......................16-179

16.14.14.3 SCC Receiver Full Sequence ...................................16-180

16.14.14.4 SCC Receiver Shortcut Sequence ...........................16-180

16.14.14.5 Switching Protocols ..................................................16-180

16.14.15 Saving Power .......................................................................16-180

16.14.16 UART Controller ...................................................................16-181

16.14.16.1 Features ...................................................................16-182

16.14.16.2 Normal Asynchronous Mode ....................................16-183

16.14.16.3 Synchronous Mode ...................................................16-183

16.14.16.4 UART Memory Map ..................................................16-184

16.14.16.5 UART Programming Model ......................................16-186

16.14.16.6 Command Set ...........................................................16-187

16.14.16.7 UART Address Recognition ......................................16-188

16.14.16.8 UART Control Characters (Receiver) .......................16-190

16.14.16.9 Wake-Up Timer (Receiver) .......................................16-191

16.14.16.10 BREAK Support (Receiver) ......................................16-191

16.14.16.11 Send Break (Transmitter) .........................................16-193

16.14.16.12 Sending a Preamble (Transmitter) ...........................16-193

16.14.16.13 Fractional Stop Bits (Transmitter) .............................16-193

16.14.16.14 UART Error-Handling Procedure ..............................16-195

16.14.16.15 UART Mode Register ...............................................16-197

16.14.16.16 UART Receive Buffer Descriptor ..............................16-200

16.14.16.17 UART Transmit Buffer Descriptor .............................16-204

16.14.16.18 UART Event Register ...............................................16-206

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16.14.16.19 UART Mask Register ................................................16-208

16.14.16.20 SCC Status Register ................................................16-209

16.14.16.21 SCC UART Example ................................................16-209

16.14.16.22 S-Records Programming Example ...........................16-211

16.14.17 HDLC Controller ...................................................................16-211

16.14.17.1 Features ...................................................................16-212

16.14.17.2 HDLC Channel Frame Transmission Processing .....16-213

16.14.17.3 HDLC Channel Frame Reception Processing ..........16-213

16.14.17.4 HDLC Memory Map ..................................................16-214

16.14.17.5 Programming Model .................................................16-216

16.14.17.6 Command Set ...........................................................16-217

16.14.17.7 HDLC Error-Handling Procedure ..............................16-218

16.14.17.8 HDLC Mode Register ................................................16-221

16.14.17.9 HDLC Receive Buffer Descriptor...............................16-222

16.14.17.10 HDLC Transmit Buffer Descriptor..............................16-226

16.14.17.11 HDLC Event Register................................................16-228

16.14.17.12 HDLC Mask Register.................................................16-230

16.14.17.13 SCC Status Register .................................................16-230

16.14.17.14 SCC HDLC Example #1............................................16-231

16.14.17.15 SCC HDLC Example #2............................................16-233

16.14.18 HDLC Bus Controller.............................................................16-233

16.14.18.1 Features ....................................................................16-235

16.14.18.2 HDLC Bus Operation.................................................16-235

16.14.18.3 HDLC Bus Memory Map and Programming..............16-239

16.14.19 ASYNC HDLC Controller ......................................................16-240

16.14.19.1 Features ....................................................................16-240

16.14.19.2 ASYNC HDLC Channel Frame Transmission

Processing ................................................................16-241

16.14.19.3 ASYNC HDLC Channel Frame Reception

Processing ................................................................16-241

16.14.19.4 Transmitter Transparency Encoding .........................16-242

16.14.19.5 Receiver Transparency Decoding.............................16-242

16.14.19.6 Cases Not Covered By RFC 1549.............................16-243

16.14.19.7 Implementation Specifics Related to

Asynchronous HDLC.................................................16-244

16.14.19.8 ASYNC HDLC Memory Map .....................................16-244

16.14.19.9 Configuring the General SCC Parameters................16-246

16.14.19.10 Programming Model..................................................16-247

16.14.19.11 ASYNC HDLC Command Set ...................................16-247

16.14.19.12 ASYNC HDLC Error Handling Procedure..................16-248

16.14.19.13 ASYNC HDLC Registers...........................................16-250

16.14.19.14 ASYNC HDLC Rx Buffer Descriptor..........................16-252

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16.14.19.15 ASYNC HDLC Tx Buffer Descriptor ..........................16-255

16.14.19.16 Differences Between HDLC and ASYNC HDLC .......16-256

16.14.19.17 Programming Example..............................................16-257

16.14.20 AppleTalk Controller..............................................................16-258

16.14.20.1 LocalTalk Bus Operation...........................................16-258

16.14.20.2 Features ....................................................................16-259

16.14.20.3 AppleTalk Hardware Connection...............................16-259

16.14.20.4 AppleTalk Memory Map and Programming Model....16-260

16.14.21 BISYNC Controller................................................................16-261

16.14.21.1 Features ....................................................................16-263

16.14.21.2 BISYNC Channel Frame Transmission.....................16-263

16.14.21.3 BISYNC Channel Frame Reception..........................16-264

16.14.21.4 BISYNC Memory Map...............................................16-265

16.14.21.5 Command Set............................................................16-266

16.14.21.6 BISYNC Control Character Recognition....................16-268

16.14.21.7 BSYNC-BISYNC SYNC Register..............................16-270

16.14.21.8 BDLE-BISYNC DLE Register....................................16-270

16.14.21.9 Transmitting and Receiving the Synchronization

Sequence ..................................................................16-271

16.14.21.10 BISYNC Error-Handling Procedure...........................16-271

16.14.21.11 BISYNC Mode Register.............................................16-272

16.14.21.12 BISYNC Receive Buffer Descriptor...........................16-275

16.14.21.13 BISYNC Transmit Buffer Descriptor..........................16-277

16.14.21.14 BISYNC Event Register.............................................16-280

16.14.21.15 BISYNC Mask Register.............................................16-281

16.14.21.16 SCC Status Register .................................................16-281

16.14.21.17 Programming the BISYNC Controller........................16-282

16.14.21.18 SCC BISYNC Example..............................................16-283

16.14.22 Transparent Controller..........................................................16-284

16.14.22.1 Features ....................................................................16-285

16.14.22.2 Transparent Channel Frame Transmission

Processing ................................................................16-285

16.14.22.3 Transparent Channel Frame Reception

Processing ................................................................16-286

16.14.22.4 Achieving Synchronization in Transparent Mode......16-287

16.14.22.5 Transparent Memory Map.........................................16-289

16.14.22.6 Command Set............................................................16-289

16.14.22.7 Transparent Error-Handling Procedure.....................16-291

16.14.22.8 Transparent Mode Register.......................................16-291

16.14.22.9 Transparent Receive Buffer Descriptor.....................16-292

16.14.22.10 Transparent Transmit Buffer Descriptor....................16-294

16.14.22.11 Transparent Event Register.......................................16-296

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16.14.22.12 Transparent Mask Register.......................................16-297

16.14.22.13 SCC Status Register .................................................16-297

16.14.22.14 SCC Transparent Example........................................16-298

16.14.23 RAM Microcodes...................................................................16-299

16.14.24 Ethernet Controller................................................................16-299

16.14.24.1 Ethernet On the MPC821..........................................16-300

16.14.24.2 Features ....................................................................16-301

16.14.24.3 Learning Ethernet on the MPC821............................16-302

16.14.24.4 Connecting the MPC821 to Ethernet.........................16-303

16.14.24.5 Ethernet Channel Frame Transmission.....................16-304

16.14.24.6 Ethernet Channel Frame Reception..........................16-306

16.14.24.7 CAM Interface............................................................16-307

16.14.24.8 Ethernet Memory Map...............................................16-310

16.14.24.9 Programming Model..................................................16-315

16.14.24.10 Ethernet Command Set.............................................16-315

16.14.24.11 Ethernet Address Recognition...................................16-317

16.14.24.12 Hash Table Algorithm................................................16-319

16.14.24.13 Interpacket Gap Time................................................16-320

16.14.24.14 Collision Handling......................................................16-320

16.14.24.15 Internal and External Loopback.................................16-320

16.14.24.16 Ethernet Error-Handling Procedure...........................16-321

16.14.24.17 Ethernet Mode Register.............................................16-322

16.14.24.18 Ethernet Receive Buffer Descriptor...........................16-324

16.14.24.19 Ethernet Transmit Buffer Descriptor..........................16-328

16.14.24.20 Ethernet Event Register ............................................16-330

16.14.24.21 Ethernet Mask Register.............................................16-332

16.14.24.22 Ethernet Status Register ...........................................16-332

16.14.24.23 SCC Ethernet Example .............................................16-332

16.15 Serial Management Controllers.......................................................16-334

16.15.1 Overview...............................................................................16-334

16.15.2 General SMC Mode Register................................................16-335

16.15.3 SMC Buffer Descriptors ........................................................16-336

16.15.4 SMC Parameter RAM ...........................................................16-336

16.15.4.1 BD Table Pointer.......................................................16-338

16.15.4.2 SMC Function Code Registers..................................16-338

16.15.4.3 Maximum Receive Buffer Length Register................16-339

16.15.4.4 Receiver Buffer Descriptor Pointer............................16-340

16.15.4.5 Transmitter Buffer Descriptor Pointer........................16-340

16.15.4.6 Other General Parameters........................................16-340

16.15.5 Disabling the SMCs On-the-Fly.............................................16-341

16.15.5.1 SMC Transmitter Full Sequence ...............................16-341

16.15.5.2 SMC Transmitter Shortcut Sequence........................16-342

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NXP MPC821 User guide

NXP MPC821 User guide

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