Contents
xiii
CONTENTS
Paragraph
Number
Title
Page
Number
7.2.6 Data Bus Arbitration Signals.........................................................................7-21
7.2.6.1 Data Bus Grant (DBG
)—Input..................................................................7-21
7.2.6.2 Data Bus Write Only (DBWO
)—Input.....................................................7-22
7.2.6.3 Data Bus Busy (DBB
) ...............................................................................7-22
7.2.6.3.1 Data Bus Busy (DBB
)—Output ............................................................ 7-22
7.2.6.3.2 Data Bus Busy (DBB
)—Input...............................................................7-23
7.2.7 Data Transfer Signals.....................................................................................7-23
7.2.7.1 Data Bus (DH[0–31], DL[0–31]) ..............................................................7-23
7.2.7.1.1 Data Bus (DH[0–31], DL[0–31])—Output ...........................................7-24
7.2.7.1.2 Data Bus (DH[0–31], DL[0–31])—Input..............................................7-24
7.2.7.2 Data Bus Parity (DP[0–7])......................................................................... 7-24
7.2.7.2.1 Data Bus Parity (DP[0–7])—Output .....................................................7-24
7.2.7.2.2 Data Bus Parity (DP[0–7])—Input........................................................ 7-25
7.2.7.3 Data Parity Error (DPE
)—Output .............................................................7-25
7.2.7.4 Data Bus Disable (DBDIS
)—Input ........................................................... 7-26
7.2.8 Data Transfer Termination Signals................................................................7-26
7.2.8.1 Transfer Acknowledge (TA
)—Input.........................................................7-26
7.2.8.2 Data Retry (DRTRY
)—Input .................................................................... 7-27
7.2.8.3 Transfer Error Acknowledge (TEA
)—Input ............................................. 7-27
7.2.9 System Interrupt, Checkstop, and Reset Signals ...........................................7-28
7.2.9.1 Interrupt (INT
)—Input............................................................................... 7-28
7.2.9.2 System Management Interrupt (SMI
)—Input ...........................................7-29
7.2.9.3 Machine Check Interrupt (MCP
)—Input................................................... 7-29
7.2.9.4 Checkstop Input(CKSTP_IN
)—Input ....................................................... 7-30
7.2.9.5 Checkstop Output (CKSTP_OUT
)—Output.............................................7-30
7.2.9.6 Reset Signals..............................................................................................7-30
7.2.9.6.1 Hard Reset (HRESET
)—Input..............................................................7-30
7.2.9.6.2 Soft Reset (SRESET
)—Input................................................................7-31
7.2.10 Processor Configuration Signals....................................................................7-31
7.2.10.1 Drive Mode (DRVMOD)—Input..............................................................7-31
7.2.10.2 Timebase Enable (TBEN)—Input.............................................................7-31
7.2.10.3 Reservation (RSRV
)—Output...................................................................7-32
7.2.10.4 L2 Intervention (L2_INT)—Input.............................................................7-32
7.2.10.5 Run (RUN)—Input....................................................................................7-32
7.2.10.6 Halted (HALTED) —Output.....................................................................7-33
7.2.11 COP/Scan Interface........................................................................................7-33
7.2.12 Clock Signals.................................................................................................7-34
7.2.13 Power Management .......................................................................................7-34
7.2.13.1 State Transition from Normal Mode to Doze Mode..................................7-35
7.2.13.2 State Transition from Doze Mode to Nap Mode ....................................... 7-35
7.2.13.3 State Transition from Nap Mode to Doze Mode ....................................... 7-35
7.2.13.4 State Transition from Nap Mode to Normal Mode ...................................7-35
7.2.13.5 State Transition from Doze Mode to Normal Mode..................................7-36
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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