NXP MPC8309 Reference guide

MPC8309 PowerQUICC II Pro

Integrated Communications

Processor Reference Manual

MPC8309RM

Rev. 2

10/2014

Freescale, the Freescale logo, CodeWarrior, ColdFire, PowerQUICC,

StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,

Reg. U.S. Pat. & Tm. Off. CoreNet, QorIQ, QUICC Engine, and VortiQa are

trademarks of Freescale Semiconductor, Inc. All other product or service

names are the property of their respective owners. The Power Architecture

and Power.org word marks and the Power and Power.org logos and related

marks are trademarks and service marks licensed by Power.org.

Information in this document is provided solely to enable system and software

implementers to use Freescale Semiconductor products. There are no express or

implied copyright licenses granted hereunder to design or fabricate any integrated

circuits or integrated circuits based on the information in this document.

Freescale Semiconductor reserves the right to make changes without further notice to

any products herein. Freescale Semiconductor makes no warranty, representation or

guarantee regarding the suitability of its products for any particular purpose, nor does

Freescale Semiconductor assume any liability arising out of the application or use of

any product or circuit, and specifically disclaims any and all liability, including without

limitation consequential or incidental damages. “Typical” parameters which may be

provided in Freescale Semiconductor data sheets and/or specifications can and do

vary in different applications and actual performance may vary over time. All operating

parameters, including “Typicals” must be validated for each customer application by

customer’s technical experts. Freescale Semiconductor does not convey any license

under its patent rights nor the rights of others. Freescale Semiconductor products are

not designed, intended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to support or sustain life,

or for any other application in which the failure of the Freescale Semiconductor product

could create a situation where personal injury or death may occur. Should Buyer

purchase or use Freescale Semiconductor products for any such unintended or

unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor

and its officers, employees, subsidiaries, affiliates, and distributors harmless against all

claims, costs, damages, and expenses, and reasonable attorney fees arising out of,

directly or indirectly, any claim of personal injury or death associated with such

unintended or unauthorized use, even if such claim alleges that Freescale

Semiconductor was negligent regarding the design or manufacture of the part.

How to Reach Us:

Home Page:

www.freescale.com

Web Support:

http://www.freescale.com/support

USA/Europe or Locations Not Listed:

Freescale Semiconductor, Inc.

Technical Information Center, EL516

2100 East Elliot Road

Tempe, Arizona 85284

+1-800-521-6274 or

+1-480-768-2130

www.freescale.com/support

Europe, Middle East, and Africa:

Freescale Halbleiter Deutschland GmbH

Technical Information Center

Schatzbogen 7

81829 Muenchen, Germany

+44 1296 380 456 (English)

+46 8 52200080 (English)

+49 89 92103 559 (German)

+33 1 69 35 48 48 (French)

www.freescale.com/support

Japan:

Freescale Semiconductor Japan Ltd.

Headquarters

ARCO Tower 15F

1-8-1, Shimo-Meguro, Meguro-ku

Tokyo 153-0064

Japan

0120 191014 or

+81 3 5437 9125

suppor[email protected]

Asia/Pacific:

Freescale Semiconductor China Ltd.

Exchange Building 23F

No. 118 Jianguo Road

Chaoyang District

Beijing 100022

China

+86 010 5879 8000

suppor[email protected]

For Literature Requests Only:

Freescale Semiconductor

Literature Distribution Center

+1-800 441-2447 or

+1-303-675-2140

Fax: +1-303-675-2150

LDCForFreescaleSemiconductor

@hibbertgroup.com

Document Number: MPC8309RM

Rev. 2, 10/2014

MPC8309 PowerQUICC II Pro Integrated Communications Processor Reference Manual, Rev. 2

Freescale Semiconductor i

Contents

Paragraph

Number Title

Page

Number

Contents

About This Book

Organization....................................................................................................................xlix

Suggested Reading.............................................................................................................. li

General Information........................................................................................................ li

Related Documentation................................................................................................... li

Conventions ....................................................................................................................... lii

Signal Conventions...........................................................................................................liii

Acronyms and Abbreviations ...........................................................................................liii

Chapter 1

Overview

1.1 MPC8309 PowerQUICC II Pro Processor Overview...................................................... 1-1

1.2 Features............................................................................................................................ 1-2

1.3 MPC8309 Architecture Overview ................................................................................... 1-7

1.3.1 Power Architecture Core ............................................................................................. 1-7

1.3.2 QUICC Engine Block................................................................................................ 1-10

1.3.3 DDR2 Memory Controller......................................................................................... 1-14

1.3.4 PCI Bus Interface....................................................................................................... 1-14

1.3.5 I/O Sequencer ............................................................................................................ 1-15

1.3.6 Enhanced Local Bus Controller (eLBC).................................................................... 1-15

1.3.7 Integrated Programmable Interrupt Controller (IPIC)............................................... 1-17

1.3.8 Enhanced Secure Digital Host Controller (eSDHC).................................................. 1-17

1.3.9 Universal Serial Bus (USB) 2.0................................................................................. 1-18

1.3.10 FlexCAN Module ...................................................................................................... 1-19

1.3.11 Dual I

2

C Interfaces ....................................................................................................1-20

1.3.12 DMA Engine 1........................................................................................................... 1-20

1.3.13 DMA Engine 2........................................................................................................... 1-21

1.3.14 Dual Universal Asynchronous Receiver/Transmitter (DUART)............................... 1-21

1.3.15 Serial Peripheral Interface (SPI)................................................................................1-22

1.3.16 System Timers ........................................................................................................... 1-22

1.3.17 Real Time Clock........................................................................................................1-22

Chapter 2

Memory Map

2.1 Internal Memory Mapped Registers ................................................................................ 2-1

MPC8309 PowerQUICC II Pro Integrated Communications Processor Reference Manual, Rev. 2

ii Freescale Semiconductor

Contents

Paragraph

Number Title

Page

Number

2.2 Accessing IMMR Memory from the Local Processor..................................................... 2-1

2.3 IMMR Address Map........................................................................................................ 2-1

Chapter 3

Signal Descriptions

3.1 Signals Overview.............................................................................................................3-1

3.2 Output Signal States During Reset ................................................................................ 3-20

Chapter 4

Reset, Clocking, and Initialization

4.1 External Signals............................................................................................................... 4-1

4.1.1 Reset Signals................................................................................................................ 4-1

4.1.2 Clock Signals............................................................................................................... 4-2

4.2 Functional Description..................................................................................................... 4-4

4.2.1 Reset Operations.......................................................................................................... 4-4

4.2.2 Power-On Reset Flow.................................................................................................. 4-6

4.2.3 Hard Reset Flow .......................................................................................................... 4-7

4.3 Reset Configuration......................................................................................................... 4-8

4.3.1 Reset Configuration Signals ........................................................................................ 4-8

4.3.2 Reset Configuration Words........................................................................................ 4-10

4.3.3 Loading the Reset Configuration Words ................................................................... 4-17

4.4 Clocking ........................................................................................................................ 4-25

4.4.1 System Clock Domains.............................................................................................. 4-26

4.5 Memory Map/Register Definitions................................................................................ 4-27

4.5.1 Reset Configuration Register Descriptions................................................................ 4-27

4.5.2 Clock Configuration Registers................................................................................... 4-31

Chapter 5

System Boot

5.1 Booting from On Chip ROM........................................................................................... 5-1

5.2 eSDHC Boot .................................................................................................................... 5-1

5.2.1 Overview...................................................................................................................... 5-2

5.2.2 Features........................................................................................................................ 5-2

5.2.3 SD/MMC Card Data Structure .................................................................................... 5-3

5.2.4 eSDHC Controller Initial Configuration...................................................................... 5-7

5.2.5 eSDHC Controller Boot Sequence .............................................................................. 5-7

5.2.6 eSDHC Boot Error Handling....................................................................................... 5-8

5.3 SPI Boot ROM.................................................................................................................5-9

MPC8309 PowerQUICC II Pro Integrated Communications Processor Reference Manual, Rev. 2

Freescale Semiconductor iii

Contents

Paragraph

Number Title

Page

Number

5.3.1 Overview.................................................................................................................... 5-10

5.3.2 Features...................................................................................................................... 5-10

5.3.3 EEPROM Data Structure........................................................................................... 5-10

5.3.4 SPI Controller Configuration..................................................................................... 5-13

Chapter 6

System Configuration

6.1 Introduction...................................................................................................................... 6-1

6.2 Local Memory Map Overview and Example .................................................................. 6-1

6.2.1 Address Translation and Mapping............................................................................... 6-3

6.2.2 Window into Configuration Space............................................................................... 6-4

6.2.3 Local Access Windows................................................................................................ 6-4

6.2.4 Local Access Register Descriptions ............................................................................ 6-6

6.2.5 Precedence of Local Access Windows ...................................................................... 6-14

6.2.6 Configuring Local Access Windows ......................................................................... 6-14

6.2.7 Distinguishing Local Access Windows from Other Mapping Functions.................. 6-14

6.2.8 hashasOutbound Address Translation and Mapping Windows................................. 6-15

6.2.9 Inbound Address Translation and Mapping Windows .............................................. 6-15

6.2.10 hasInternal Memory Map........................................................................................... 6-15

6.2.11 Accessing Internal Memory from External Masters.................................................. 6-16

6.3 System Configuration .................................................................................................... 6-16

6.3.1 System Configuration Register Memory Map........................................................... 6-16

6.3.2 System Configuration Registers ................................................................................ 6-17

6.3.3 Multisite Muxing ....................................................................................................... 6-39

6.4 Software Watchdog Timer (WDT).................................................................................6-40

6.4.1 WDT Overview.......................................................................................................... 6-40

6.4.2 WDT Features............................................................................................................ 6-41

6.4.3 WDT Modes of Operation......................................................................................... 6-41

6.4.4 WDT Memory Map/Register Definition ................................................................... 6-41

6.4.5 Functional Description............................................................................................... 6-44

6.4.6 Initialization/Application Information (WDT Programming Guidelines)................. 6-46

6.5 Real Time Clock Module (RTC).................................................................................... 6-47

6.5.1 Overview.................................................................................................................... 6-47

6.5.2 Features...................................................................................................................... 6-47

6.5.3 Modes of Operation................................................................................................... 6-48

6.5.4 External Signal Description....................................................................................... 6-48

6.5.5 RTC Memory Map/Register Definition..................................................................... 6-48

6.5.6 Functional Description............................................................................................... 6-52

6.5.7 RTC Initialization Sequence...................................................................................... 6-53

6.6 Periodic Interval Timer (PIT) ........................................................................................ 6-54

MPC8309 PowerQUICC II Pro Integrated Communications Processor Reference Manual, Rev. 2

iv Freescale Semiconductor

Contents

Paragraph

Number Title

Page

Number

6.6.1 PIT Overview............................................................................................................. 6-54

6.6.2 PIT Features...............................................................................................................6-54

6.6.3 PIT Modes of Operation............................................................................................ 6-54

6.6.4 PIT External Signal Description................................................................................ 6-55

6.6.5 PIT Memory Map/Register Definition ...................................................................... 6-55

6.6.6 Functional Description............................................................................................... 6-58

6.6.7 PIT Programming Guidelines.................................................................................... 6-59

6.7 General-Purpose Timers (GTMs) .................................................................................. 6-60

6.7.1 GTM Overview.......................................................................................................... 6-60

6.7.2 GTM Features............................................................................................................ 6-60

6.7.3 GTM Modes of Operation ......................................................................................... 6-61

6.7.4 GTM External Signal Description............................................................................. 6-62

6.7.5 GTM Memory Map/Register Definition....................................................................6-64

6.7.6 Functional Description............................................................................................... 6-73

6.7.7 Initialization/Application Information (Programming Guidelines for GTM Registers) ...

6-76

6.8 Power Management Control (PMC).............................................................................. 6-76

6.8.1 External Signal Description....................................................................................... 6-77

6.8.2 PMC Memory Map/Register Definition.................................................................... 6-77

6.8.3 Functional Description............................................................................................... 6-78

Chapter 7

Arbiter and Bus Monitor

7.1 Overview.......................................................................................................................... 7-1

7.1.1 Coherent System Bus Overview.................................................................................. 7-1

7.2 Arbiter Memory Map/Register Definition....................................................................... 7-2

7.2.1 Arbiter Configuration Register (ACR)........................................................................ 7-3

7.2.2 Arbiter Timers Register (ATR).................................................................................... 7-4

7.2.3 Arbiter Event Register (AER)...................................................................................... 7-5

7.2.4 Arbiter Interrupt Definition Register (AIDR).............................................................. 7-6

7.2.5 Arbiter Mask Register (AMR)..................................................................................... 7-7

7.2.6 Arbiter Event Attributes Register (AEATR)................................................................ 7-8

7.2.7 Arbiter Event Address Register (AEADR).................................................................. 7-9

7.2.8 Arbiter Event Response Register (AERR)................................................................. 7-10

7.3 Functional Description................................................................................................... 7-11

7.3.1 Arbitration Policy ...................................................................................................... 7-11

7.3.2 Bus Error Detection................................................................................................... 7-14

7.4 Initialization/Applications Information ......................................................................... 7-17

7.4.1 Initialization Sequence............................................................................................... 7-17

7.4.2 Error Handling Sequence........................................................................................... 7-17

MPC8309 PowerQUICC II Pro Integrated Communications Processor Reference Manual, Rev. 2

Freescale Semiconductor v

Contents

Paragraph

Number Title

Page

Number

Chapter 8

e300 Processor Core Overview

8.1 Overview.......................................................................................................................... 8-1

8.1.1 Features........................................................................................................................ 8-3

8.1.2 Instruction Unit............................................................................................................ 8-6

8.1.3 Independent Execution Units....................................................................................... 8-7

8.1.4 Completion Unit .......................................................................................................... 8-8

8.1.5 Memory Subsystem Support........................................................................................ 8-8

8.1.6 Bus Interface Unit (BIU) ........................................................................................... 8-10

8.1.7 System Support Functions......................................................................................... 8-11

8.2 e300 Processor and System Version Numbers............................................................... 8-13

8.3 PowerPC Architecture Implementation......................................................................... 8-13

8.4 Implementation-Specific Information............................................................................ 8-14

8.4.1 Register Model........................................................................................................... 8-14

8.4.2 Instruction Set and Addressing Modes...................................................................... 8-26

8.4.3 Cache Implementation............................................................................................... 8-29

8.4.4 Interrupt Model.......................................................................................................... 8-31

8.4.5 Memory Management................................................................................................ 8-35

8.4.6 Instruction Timing .....................................................................................................8-36

8.4.7 Core Interface ............................................................................................................ 8-37

8.4.8 Debug Features ......................................................................................................... 8-39

8.5 Differences Between Cores........................................................................................... 8-40

Chapter 9

Integrated Programmable Interrupt Controller (IPIC)

9.1 Introduction...................................................................................................................... 9-1

9.2 Features............................................................................................................................ 9-4

9.3 Modes of Operation ......................................................................................................... 9-4

9.3.1 Core Enable Mode....................................................................................................... 9-4

9.3.2 Core Disable Mode...................................................................................................... 9-4

9.4 External Signal Description............................................................................................. 9-5

9.4.1 Overview...................................................................................................................... 9-5

9.4.2 Detailed Signal Descriptions ....................................................................................... 9-5

9.5 Memory Map/Register Definition ................................................................................... 9-5

9.5.1 System Global Interrupt Configuration Register (SICFR).......................................... 9-7

9.5.2 System Global Interrupt Vector Register (SIVCR)...................................................... 9-8

9.5.3 System Internal Interrupt Pending Registers (SIPNR_H and SIPNR_L).................. 9-11

9.5.4 System Internal Interrupt Group A Priority Register (SIPRR_A)............................. 9-14

9.5.5 System Internal Interrupt Group B Priority Register (SIPRR_B) ............................. 9-15

MPC8309 PowerQUICC II Pro Integrated Communications Processor Reference Manual, Rev. 2

vi Freescale Semiconductor

Contents

Paragraph

Number Title

Page

Number

9.5.6 System Internal Interrupt Group C Priority Register (SIPRR_C) ............................. 9-15

9.5.7 System Internal Interrupt Group D Priority Register (SIPRR_D)............................. 9-16

9.5.8 System Internal Interrupt Mask Register (SIMSR_H and SIMSR_L)...................... 9-17

9.5.9 System Internal Interrupt Control Register (SICNR)................................................ 9-18

9.5.10 System External Interrupt Pending Register (SEPNR).............................................. 9-20

9.5.11 System Mixed Interrupt Group A Priority Register (SMPRR_A)............................. 9-21

9.5.12 System Mixed Interrupt Group B Priority Register (SMPRR_B)............................. 9-22

9.5.13 System External Interrupt Mask Register (SEMSR)................................................. 9-22

9.5.14 System External Interrupt Control Register (SECNR).............................................. 9-23

9.5.15 System Error Status Register (SERSR) ..................................................................... 9-25

9.5.16 System Error Mask Register (SERMR)..................................................................... 9-26

9.5.17 System Error Control Register (SERCR) .................................................................. 9-27

9.5.18 System External interrupt Polarity Control Register (SEPCR)................................. 9-27

9.5.19 System Internal Interrupt Force Registers (SIFCR_H and SIFCR_L)...................... 9-28

9.5.20 System External Interrupt Force Register (SEFCR).................................................. 9-30

9.5.21 System Error Force Register (SERFR)...................................................................... 9-30

9.5.22 System Critical Interrupt Vector Register (SCVCR)................................................. 9-31

9.5.23 System Management Interrupt Vector Register (SMVCR) ....................................... 9-31

9.5.24 QUICC Engine Ports Interrupt Event Register (CEPIER) ........................................ 9-32

9.5.25 QUICC Engine Ports Interrupt Mask Register (CEPIMR)........................................ 9-33

9.5.26 QUICC Engine Ports Interrupt Control Register (CEPICR)..................................... 9-35

9.6 Functional Description................................................................................................... 9-35

9.6.1 Interrupt Types........................................................................................................... 9-35

9.6.2 Interrupt Configuration.............................................................................................. 9-36

9.6.3 Internal Interrupts Group Relative Priority................................................................ 9-37

9.6.4 Mixed Interrupts Group Relative Priority.................................................................. 9-37

9.6.5 Highest Priority Interrupt........................................................................................... 9-38

9.6.6 Interrupt Source Priorities.......................................................................................... 9-38

9.6.7 Masking Interrupt Sources......................................................................................... 9-42

9.6.8 Interrupt Vector Generation and Calculation............................................................. 9-42

9.6.9 Machine Check Interrupts.......................................................................................... 9-43

Chapter 10

DDR Memory Controller

10.1 Introduction.................................................................................................................... 10-1

10.2 Features.......................................................................................................................... 10-2

10.2.1 Modes of Operation................................................................................................... 10-3

10.3 External Signal Descriptions ......................................................................................... 10-3

10.3.1 Signals Overview....................................................................................................... 10-3

10.3.2 Detailed Signal Descriptions ..................................................................................... 10-6

MPC8309 PowerQUICC II Pro Integrated Communications Processor Reference Manual, Rev. 2

Freescale Semiconductor vii

Contents

Paragraph

Number Title

Page

Number

10.4 Memory Map/Register Definition ................................................................................. 10-9

10.4.1 Register Descriptions............................................................................................... 10-11

10.5 Functional Description................................................................................................. 10-38

10.5.1 DDR SDRAM Interface Operation.......................................................................... 10-42

10.5.2 DDR SDRAM Address Multiplexing...................................................................... 10-43

10.5.3 JEDEC Standard DDR SDRAM Interface Commands........................................... 10-45

10.5.4 DDR SDRAM Interface Timing.............................................................................. 10-47

10.5.5 DDR SDRAM Mode-Set Command Timing........................................................... 10-51

10.5.6 DDR SDRAM Registered DIMM Mode................................................................. 10-51

10.5.7 DDR SDRAM Write Timing Adjustments.............................................................. 10-52

10.5.8 DDR SDRAM Refresh ............................................................................................ 10-53

10.5.9 DDR Data Beat Ordering......................................................................................... 10-56

10.5.10 Page Mode and Logical Bank Retention ................................................................. 10-57

10.5.11 Error Checking and Correcting (ECC) .................................................................... 10-58

10.5.12 Error Management................................................................................................... 10-60

10.6 Initialization/Application Information......................................................................... 10-60

10.6.1 DDR SDRAM Initialization Sequence.................................................................... 10-62

Chapter 11

Enhanced Local Bus Controller

11.1 Introduction.................................................................................................................... 11-1

11.1.1 Overview.................................................................................................................... 11-2

11.1.2 Features...................................................................................................................... 11-2

11.1.3 Modes of Operation................................................................................................... 11-3

11.2 External Signal Descriptions ......................................................................................... 11-4

11.3 Memory Map/Register Definition ................................................................................. 11-8

11.3.1 Register Descriptions................................................................................................. 11-9

11.4 Functional Description................................................................................................. 11-38

11.4.1 Basic Architecture.................................................................................................... 11-40

11.4.2 General-Purpose Chip-Select Machine (GPCM)..................................................... 11-43

11.4.3 Flash Control Machine (FCM) ................................................................................ 11-55

11.4.4 User-Programmable Machines (UPMs)................................................................... 11-71

11.5 Initialization/Application Information......................................................................... 11-87

11.5.1 Interfacing to Peripherals in Different Address Modes........................................... 11-87

11.5.2 Bus Turnaround ....................................................................................................... 11-89

11.5.3 Interface to Different Port-Size Devices.................................................................. 11-90

11.5.4 Command Sequence Examples for NAND Flash EEPROM................................... 11-91

11.5.5 Interfacing to Fast-Page Mode DRAM Using UPM ............................................... 11-95

11.5.6 Interfacing to ZBT SRAM Using UPM................................................................. 11-100

MPC8309 PowerQUICC II Pro Integrated Communications Processor Reference Manual, Rev. 2

viii Freescale Semiconductor

Contents

Paragraph

Number Title

Page

Number

Chapter 12

Enhanced Secure Digital Host Controller

12.1 Overview........................................................................................................................ 12-1

12.2 Features.......................................................................................................................... 12-3

12.2.1 Data Transfer Modes.................................................................................................. 12-4

12.3 External Signal Description........................................................................................... 12-4

12.4 Memory Map/Register Definition ................................................................................. 12-5

12.4.1 DMA System Address Register (DSADDR)............................................................. 12-7

12.4.2 Block Attributes Register (BLKATTR)..................................................................... 12-7

12.4.3 Command Argument Register (CMDARG).............................................................. 12-8

12.4.4 Transfer Type Register (XFERTYP).......................................................................... 12-9

12.4.5 Command Response 0–3 (CMDRSP0–3)................................................................ 12-12

12.4.6 Buffer Data Port Register (DATPORT)................................................................... 12-14

12.4.7 Present State Register (PRSSTAT) ..........................................................................12-15

12.4.8 Protocol Control Register (PROCTL) ..................................................................... 12-19

12.4.9 System Control Register (SYSCTL)........................................................................ 12-22

12.4.10 Interrupt Status Register (IRQSTAT)....................................................................... 12-24

12.4.11 Interrupt Status Enable Register (IRQSTATEN)..................................................... 12-29

12.4.12 Interrupt Signal Enable Register (IRQSIGEN) ....................................................... 12-31

12.4.13 Auto CMD12 Error Status Register (AUTOC12ERR)............................................ 12-33

12.4.14 Host Controller Capabilities (HOSTCAPBLT)....................................................... 12-35

12.4.15 Watermark Level Register (WML).......................................................................... 12-36

12.4.16 Force Event Register (FEVT).................................................................................. 12-37

12.4.17 Host Controller Version Register (HOSTVER)....................................................... 12-39

12.4.18 DMA Control Register (DCR)................................................................................. 12-39

12.5 Functional Description................................................................................................. 12-39

12.5.1 Data Buffer .............................................................................................................. 12-39

12.5.2 DMA CSB Interface ................................................................................................ 12-42

12.5.3 SD Protocol Unit...................................................................................................... 12-43

12.5.4 Clock & Reset Manager........................................................................................... 12-45

12.5.5 Clock Generator....................................................................................................... 12-45

12.5.6 SDIO Card Interrupt ................................................................................................ 12-45

12.5.7 Card Insertion and Removal Detection.................................................................... 12-47

12.5.8 Power Management ................................................................................................. 12-47

12.6 Initialization/Application Information......................................................................... 12-48

12.6.1 Command Send and Response Receive Basic Operation........................................ 12-48

12.6.2 Card Identification Mode......................................................................................... 12-49

12.6.3 Card Access ............................................................................................................. 12-53

12.6.4 Switch Function....................................................................................................... 12-58

12.6.5 Commands for MMC/SD/SDIO.............................................................................. 12-60

MPC8309 PowerQUICC II Pro Integrated Communications Processor Reference Manual, Rev. 2

Freescale Semiconductor ix

Contents

Paragraph

Number Title

Page

Number

12.7 Software Restrictions................................................................................................... 12-66

12.7.1 Initialization Active ................................................................................................. 12-66

12.7.2 Software Polling Procedure..................................................................................... 12-66

12.7.3 Suspend Operation................................................................................................... 12-66

12.7.4 Data Port Access...................................................................................................... 12-66

12.7.5 Multi-block Read..................................................................................................... 12-66

Chapter 13

DMA Engine 1

13.1 Overview........................................................................................................................ 13-2

13.1.1 Features...................................................................................................................... 13-2

13.2 DMAC Memory Map/Register Definition .................................................................... 13-2

13.2.1 DMA Control Register (DMACR)............................................................................ 13-4

13.3 DMA Error Status (DMAES) ........................................................................................ 13-5

13.3.1 DMA Enable Request Register (DMAERQ)............................................................. 13-7

13.3.2 DMA Enable Error Interrupt Register (DMAEEI).................................................... 13-8

13.3.3 DMA Set Enable Error Interrupt (DMASEEI).......................................................... 13-9

13.3.4 DMA Clear Enable Error Interrupt (DMACEEI).................................................... 13-10

13.3.5 DMA Clear Interrupt Request (DMACINT)........................................................... 13-10

13.3.6 DMA Clear Error (DMACERR).............................................................................. 13-11

13.3.7 DMA Set START Bit (DMASSRT)......................................................................... 13-12

13.3.8 DMA Clear DONE Status (DMACDNE)................................................................ 13-12

13.3.9 DMA Interrupt Request Register (DMAINT)......................................................... 13-13

13.3.10 DMA Error Register (DMAERR)............................................................................ 13-14

13.3.11 DMA General Purpose Output Register (DMAGPOR) .......................................... 13-15

13.3.12 DMA Channel n Priority (DCHPRIn), n = 0–15..................................................... 13-16

13.3.13 Transfer Control Descriptor (TCD)......................................................................... 13-17

13.4 Functional Description................................................................................................. 13-25

13.4.1 DMA Microarchitecture ..........................................................................................13-25

13.4.2 DMA Basic Data Flow ............................................................................................13-26

13.5 Initialization/Application Information......................................................................... 13-29

13.5.1 DMA Initialization................................................................................................... 13-29

13.5.2 DMA Programming Errors...................................................................................... 13-30

13.6 DMA Transfer.............................................................................................................. 13-30

13.6.1 Single Request ......................................................................................................... 13-30

13.6.2 Multiple Requests.................................................................................................... 13-31

13.7 TCD Status................................................................................................................... 13-33

13.7.1 Minor Loop Complete ............................................................................................. 13-33

13.7.2 Active Channel TCD Reads..................................................................................... 13-33

13.7.3 Preemption status..................................................................................................... 13-33

MPC8309 PowerQUICC II Pro Integrated Communications Processor Reference Manual, Rev. 2

x Freescale Semiconductor

Contents

Paragraph

Number Title

Page

Number

13.8 Channel Linking .......................................................................................................... 13-34

13.9 Programming during channel execution...................................................................... 13-34

13.9.1 Dynamic priority changing...................................................................................... 13-34

13.9.2 Dynamic channel linking and dynamic scatter/gather............................................. 13-35

Chapter 14

DMA Engine 2

14.1 DMA Features................................................................................................................ 14-1

14.2 DMA Memory Map/Register Definition....................................................................... 14-2

14.3 DMA Register Descriptions........................................................................................... 14-3

14.3.1 Outbound Message Interrupt Status Register (OMISR)............................................ 14-3

14.3.2 Outbound Message Interrupt Mask Register (OMIMR)............................................ 14-4

14.3.3 Inbound Message Registers (IMR0–IMR1) ..............................................................14-5

14.3.4 Outbound Message Registers (OMR0–OMR1)......................................................... 14-5

14.3.5 Doorbell Registers ..................................................................................................... 14-6

14.3.6 Inbound Message Interrupt Status Register (IMISR) ................................................ 14-7

14.3.7 Inbound Message Interrupt Mask Register (IMIMR)................................................ 14-8

14.3.8 DMA Registers.......................................................................................................... 14-9

14.4 Functional Description................................................................................................. 14-15

14.4.1 Message Unit ........................................................................................................... 14-15

14.4.2 DMA Controller....................................................................................................... 14-16

14.4.3 DMA Operation....................................................................................................... 14-16

14.4.4 DMA Segment Descriptors...................................................................................... 14-18

14.5 Initialization/Application Information......................................................................... 14-20

14.5.1 Initialization Steps in Direct Mode.......................................................................... 14-20

14.5.2 Initialization Steps in Chaining Mode..................................................................... 14-20

Chapter 15

FlexCAN

15.1 Introduction.................................................................................................................... 15-1

15.1.1 Overview.................................................................................................................... 15-2

15.1.2 FlexCAN Module Features........................................................................................ 15-3

15.1.3 Modes of Operation................................................................................................... 15-4

15.2 External Signal Description........................................................................................... 15-5

15.2.1 Signals Overview....................................................................................................... 15-5

15.3 Memory Map/Register Definition ................................................................................. 15-5

15.3.1 Message Buffer Structure .......................................................................................... 15-7

15.3.2 Rx FIFO Structure ................................................................................................... 15-10

15.3.3 Register Descriptions............................................................................................... 15-12

MPC8309 PowerQUICC II Pro Integrated Communications Processor Reference Manual, Rev. 2

Freescale Semiconductor xi

Contents

Paragraph

Number Title

Page

Number

15.4 Functional Description................................................................................................. 15-28

15.4.1 Overview.................................................................................................................. 15-28

15.4.2 Transmit Process...................................................................................................... 15-29

15.4.3 Arbitration process................................................................................................... 15-30

15.4.4 Receive Process ....................................................................................................... 15-30

15.4.5 Matching Process..................................................................................................... 15-32

15.4.6 Data Coherence....................................................................................................... 15-33

15.4.7 Rx FIFO................................................................................................................... 15-36

15.4.8 CAN Protocol Related Features............................................................................... 15-36

15.4.9 Modes of Operation Details..................................................................................... 15-40

15.4.10 Interrupts.................................................................................................................. 15-41

15.4.11 Bus Interface............................................................................................................ 15-42

15.5 Initialization/Application Information......................................................................... 15-42

15.5.1 FlexCAN Initialization Sequence............................................................................ 15-42

15.5.2 FlexCAN Addressing and RAM size configurations .............................................. 15-44

Chapter 16

Universal Serial Bus Interface

16.1 Introduction.................................................................................................................... 16-1

16.1.1 Overview.................................................................................................................... 16-2

16.1.2 Features...................................................................................................................... 16-2

16.1.3 Modes of Operation................................................................................................... 16-2

16.2 External Signals............................................................................................................. 16-2

16.2.1 ULPI Interface ........................................................................................................... 16-3

16.3 Memory Map/Register Definitions................................................................................ 16-4

16.3.1 Capability Registers................................................................................................... 16-6

16.3.2 Operational Registers............................................................................................... 16-10

16.4 Functional Description................................................................................................. 16-44

16.4.1 System Interface ...................................................................................................... 16-44

16.4.2 DMA Engine............................................................................................................ 16-44

16.4.3 FIFO RAM Controller............................................................................................. 16-45

16.4.4 PHY Interface.......................................................................................................... 16-45

16.5 Host Data Structures.................................................................................................... 16-45

16.5.1 Periodic Frame List.................................................................................................. 16-46

16.5.2 Asynchronous List Queue Head Pointer.................................................................. 16-47

16.5.3 Isochronous (High-Speed) Transfer Descriptor (iTD)............................................. 16-47

16.5.4 Split Transaction Isochronous Transfer Descriptor (siTD)...................................... 16-51

16.5.5 Queue Element Transfer Descriptor (qTD) ............................................................. 16-55

16.5.6 Queue Head.............................................................................................................. 16-60

16.5.7 Periodic Frame Span Traversal Node (FSTN)......................................................... 16-64

MPC8309 PowerQUICC II Pro Integrated Communications Processor Reference Manual, Rev. 2

xii Freescale Semiconductor

Contents

Paragraph

Number Title

Page

Number

16.6 Host Operations ........................................................................................................... 16-65

16.6.1 Host Controller Initialization................................................................................... 16-66

16.6.2 Power Port................................................................................................................ 16-67

16.6.3 Reporting Over-Current........................................................................................... 16-67

16.6.4 Suspend/Resume...................................................................................................... 16-67

16.6.5 Schedule Traversal Rules......................................................................................... 16-69

16.6.6 Periodic Schedule Frame Boundaries vs. Bus Frame Boundaries........................... 16-71

16.6.7 Periodic Schedule .................................................................................................... 16-73

16.6.8 Managing Isochronous Transfers Using iTDs......................................................... 16-74

16.6.9 Asynchronous Schedule........................................................................................... 16-79

16.6.10 Managing Control/Bulk/Interrupt Transfers via Queue Heads................................ 16-83

16.6.11 Ping Control............................................................................................................. 16-87

16.6.12 Split Transactions..................................................................................................... 16-88

16.6.13 Port Test Modes..................................................................................................... 16-116

16.6.14 Interrupts................................................................................................................ 16-117

16.7 Device Data Structures .............................................................................................. 16-121

16.7.1 Endpoint Queue Head............................................................................................ 16-122

16.7.2 Endpoint Transfer Descriptor (dTD) ..................................................................... 16-124

16.8 Device Operational Model.........................................................................................16-127

16.8.1 Device Controller Initialization............................................................................. 16-127

16.8.2 Port State and Control............................................................................................ 16-128

16.8.3 Managing Endpoints.............................................................................................. 16-131

16.8.4 Managing Queue Heads......................................................................................... 16-141

16.8.5 Managing Transfers with Transfer Descriptors ..................................................... 16-143

16.8.6 Servicing Interrupts................................................................................................ 16-146

16.9 Deviations from the EHCI Specifications ................................................................. 16-147

16.9.1 Embedded Transaction Translator Function.......................................................... 16-148

16.9.2 Device Operation................................................................................................... 16-151

16.9.3 Non-Zero Fields the Register File ......................................................................... 16-152

16.9.4 SOF Interrupt......................................................................................................... 16-152

16.9.5 Embedded Design.................................................................................................. 16-152

16.9.6 Miscellaneous Variations from EHCI.................................................................... 16-152

Chapter 17

I

2

C Interfaces

17.1 Introduction.................................................................................................................... 17-1

17.1.1 Features...................................................................................................................... 17-2

17.1.2 Modes of Operation................................................................................................... 17-2

17.2 External Signal Descriptions ......................................................................................... 17-3

17.2.1 Signal Overview ........................................................................................................ 17-3

MPC8309 PowerQUICC II Pro Integrated Communications Processor Reference Manual, Rev. 2

Freescale Semiconductor xiii

Contents

Paragraph

Number Title

Page

Number

17.2.2 Detailed Signal Descriptions ..................................................................................... 17-3

17.3 Memory Map/Register Definition ................................................................................. 17-4

17.3.1 Register Descriptions................................................................................................. 17-5

17.4 Functional Description................................................................................................. 17-10

17.4.1 Transaction Protocol................................................................................................ 17-10

17.4.2 Arbitration Procedure .............................................................................................. 17-14

17.4.3 Handshaking ............................................................................................................ 17-15

17.4.4 Clock Control........................................................................................................... 17-15

17.4.5 Boot Sequencer Mode.............................................................................................. 17-16

17.5 Initialization/Application Information......................................................................... 17-20

17.5.1 Interrupt Service Routine Flowchart........................................................................ 17-20

17.5.2 Initialization Sequence............................................................................................. 17-22

17.5.3 Generation of START .............................................................................................. 17-22

17.5.4 Post-Transfer Software Response............................................................................ 17-22

17.5.5 Generation of STOP................................................................................................. 17-23

17.5.6 Generation of Repeated START .............................................................................. 17-23

17.5.7 Generation of SCLn When SDAn is Negated ......................................................... 17-23

17.5.8 Slave Mode Interrupt Service Routine..................................................................... 17-23

Chapter 18

DUART

18.1 Overview........................................................................................................................ 18-1

18.1.1 Features...................................................................................................................... 18-2

18.1.2 Modes of Operation................................................................................................... 18-3

18.2 External Signal Descriptions ......................................................................................... 18-3

18.2.1 Signal Overview ........................................................................................................ 18-3

18.2.2 Detailed Signal Descriptions ..................................................................................... 18-3

18.3 Memory Map/Register Definition ................................................................................. 18-4

18.3.1 Register Descriptions................................................................................................. 18-6

18.4 Functional Description................................................................................................. 18-18

18.4.1 Serial Interface......................................................................................................... 18-19

18.4.2 Baud-Rate Generator Logic..................................................................................... 18-20

18.4.3 Local Loopback Mode............................................................................................. 18-21

18.4.4 Errors ....................................................................................................................... 18-21

18.4.5 FIFO Mode .............................................................................................................. 18-21

18.5 DUART Initialization/Application Information .......................................................... 18-23

Chapter 19

Serial Peripheral Interface

MPC8309 PowerQUICC II Pro Integrated Communications Processor Reference Manual, Rev. 2

xiv Freescale Semiconductor

Contents

Paragraph

Number Title

Page

Number

19.1 Overview........................................................................................................................ 19-1

19.2 Introduction.................................................................................................................... 19-2

19.2.1 Features...................................................................................................................... 19-2

19.2.2 SPI Transmission and Reception Process.................................................................. 19-3

19.2.3 Modes of Operation................................................................................................... 19-3

19.3 External Signal Descriptions ......................................................................................... 19-6

19.3.1 Overview.................................................................................................................... 19-7

19.3.2 Detailed Signal Descriptions ..................................................................................... 19-7

19.4 Memory Map/Register Definition ................................................................................. 19-8

19.4.1 Register Descriptions................................................................................................. 19-9

19.5 Initialization/Application Information......................................................................... 19-16

19.5.1 SPI Master Programming Example ......................................................................... 19-16

19.5.2 SPI Slave Programming Example............................................................................ 19-16

Chapter 20

JTAG/Testing Support

20.1 Overview........................................................................................................................ 20-1

20.2 JTAG Signals ................................................................................................................. 20-1

20.2.1 External Signal Descriptions ..................................................................................... 20-2

20.3 JTAG Registers and Scan Chains ..................................................................................20-3

Chapter 21

General Purpose I/O (GPIO)

21.1 Introduction.................................................................................................................... 21-1

21.1.1 Overview.................................................................................................................... 21-1

21.1.2 Features...................................................................................................................... 21-2

21.2 External Signal Description........................................................................................... 21-2

21.2.1 Signals Overview....................................................................................................... 21-2

21.3 Memory Map/Register Definition ................................................................................. 21-2

21.3.1 GPIOn Direction Register (GP1DIR–GP2DIR)........................................................ 21-3

21.3.2 GPIOn Open Drain Register (GP1ODR–GP2ODR)................................................. 21-4

21.3.3 GPIOn Data Register (GP1DAT–GP2DAT).............................................................. 21-4

21.3.4 GPIOn Interrupt Event Register (GP1IER–GP2IER)................................................ 21-5

21.3.5 GPIOn Interrupt Mask Register (GP1IMR–GP2IMR).............................................. 21-5

21.3.6 GPIOn Interrupt Control Register (GP1ICR–GP2ICR) ............................................ 21-6

Chapter 22

Sequencer

MPC8309 PowerQUICC II Pro Integrated Communications Processor Reference Manual, Rev. 2

Freescale Semiconductor xv

Contents

Paragraph

Number Title

Page

Number

22.1 Sequencer Overview...................................................................................................... 22-1

22.1.1 Sequencer Features.................................................................................................... 22-2

22.2 Sequencer External Signal Description ......................................................................... 22-2

22.3 Sequencer Memory Map/Register Definition................................................................ 22-2

22.4 Sequencer Register Descriptions ................................................................................... 22-3

22.4.1 PCI Outbound Translation Address Registers (POTARn)......................................... 22-3

22.4.2 PCI Outbound Base Address Registers (POBARn) .................................................. 22-3

22.4.3 PCI Outbound Comparison Mask Registers (POCMRn).......................................... 22-4

22.4.4 Power Management Control Register (PMCR)......................................................... 22-5

22.4.5 Discard Timer Control Register (DTCR) .................................................................. 22-6

22.5 Functional Description................................................................................................... 22-6

22.5.1 Transaction Forwarding............................................................................................. 22-6

22.5.2 PCI Outbound Address Translation........................................................................... 22-7

22.5.3 Transaction Ordering ................................................................................................. 22-8

Chapter 23

PCI Bus Interface

23.1 PCI Introduction ............................................................................................................ 23-1

23.1.1 PCI Features............................................................................................................... 23-3

23.1.2 PCI Modes of Operation............................................................................................ 23-3

23.2 PCI External Signal Description.................................................................................... 23-4

23.3 PCI Memory Map/Register Definitions....................................................................... 23-11

23.3.1 PCI Configuration Access Registers........................................................................ 23-12

23.3.2 PCI Memory-Mapped Control and Status BE Registers ......................................... 23-15

23.3.3 PCI Configuration Space Registers ......................................................................... 23-25

23.4 Functional Description................................................................................................. 23-40

23.4.1 PCI Bus Arbitration................................................................................................. 23-40

23.4.2 Bus Commands........................................................................................................ 23-43

23.4.3 PCI Protocol Fundamentals..................................................................................... 23-44

23.4.4 Other Bus Operations............................................................................................... 23-50

23.4.5 Error Functions........................................................................................................ 23-54

23.4.6 PCI Inbound Address Translation............................................................................ 23-56

23.4.7 CompactPCI Hot Swap Specification Support........................................................ 23-57

23.4.8 Byte Ordering .......................................................................................................... 23-57

23.5 Initialization/Application Information......................................................................... 23-59

23.5.1 Initialization Sequence for Host Mode.................................................................... 23-59

23.5.2 Initialization Sequence for Agent Mode.................................................................. 23-59

Chapter 24

QUICC Engine Block on the MPC8309

MPC8309 PowerQUICC II Pro Integrated Communications Processor Reference Manual, Rev. 2

xvi Freescale Semiconductor

Contents

Paragraph

Number Title

Page

Number

24.1 QUICC Engine Block.................................................................................................... 24-1

24.2 QUICC Engine Implementation Details for the MPC8309........................................... 24-2

24.2.1 System Interface ........................................................................................................ 24-4

24.2.2 Configuration – Parameter RAM............................................................................. 24-35

24.2.3 QUICC Engine Multiplexing and Timers................................................................ 24-40

24.2.4 UCC Ethernet (UEC)............................................................................................... 24-43

24.2.5 IEEE Standard 1588 Assist...................................................................................... 24-43

Appendix A

Complete List of Configuration, Control, and Status Registers

A.1 Local Access Windows.................................................................................................... 1-1

A.2 System Configuration Registers ...................................................................................... 1-2

A.3 Watchdog Timer (WDT).................................................................................................. 1-3

A.4 Real Time Clock (RTC)................................................................................................... 1-4

A.5 Periodic Interval Timer (PIT) ..........................................................................................1-4

A.6 General Purpose (Global) Timers (GTMs)...................................................................... 1-4

A.7 Integrated Programmable Interrupt Controller (IPIC)..................................................... 1-5

A.8 QUICC Engine Ports Interrupts....................................................................................... 1-7

A.9 System Arbiter................................................................................................................. 1-7

A.10 Reset Configuration.........................................................................................................1-7

A.11 Clock Configuration ........................................................................................................ 1-8

A.12 Power Management Controller (PMC)............................................................................ 1-8

A.13 General Purpose I/O (GPIO)............................................................................................ 1-8

A.14 DDR Memory Controller................................................................................................. 1-9

A.15 I

2

C Controller ................................................................................................................ 1-11

A.16 DUART.......................................................................................................................... 1-11

A.17 Enhanced Local Bus Controller (eLBC)........................................................................ 1-12

A.18 Serial Peripheral Interface (SPI).................................................................................... 1-14

A.19 DMA Engine 1............................................................................................................... 1-14

A.20 DMA Engine 2............................................................................................................... 1-15

A.21 Enhanced Secure Digital Host Controller (eSDHC)...................................................... 1-16

A.22 FlexCAN........................................................................................................................ 1-17

A.23 PCI Configuration Access Registers.............................................................................. 1-18

A.24 PCI Memory Mapped Registers .................................................................................... 1-19

A.25 Universal Serial Bus (USB) Interface............................................................................ 1-20

Appendix B

Revision History

B.1 Changes From Revision 1 to Revision 2 ......................................................................... 2-1

MPC8309 PowerQUICC II Pro Integrated Communications Processor Reference Manual, Rev. 2

Freescale Semiconductor xvii

Contents

Paragraph

Number Title

Page

Number

B.2 Changes From Revision 0 to Revision 1 ......................................................................... 2-7

MPC8309 PowerQUICC II Pro Integrated Communications Processor Reference Manual, Rev. 2

xviii Freescale Semiconductor

Contents

Paragraph

Number Title

Page

Number

Page is loading ...

NXP MPC8309 Reference guide

NXP MPC8309 Reference guide

Related papers

Other documents