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MPC8347E

NXP MPC8347E, MPC8343E, MPC8349E Reference guide

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MPC8349EA
PowerQUICC™ II Pro
Integrated Host Processor
Family Reference Manual
Supports
MPC8349EA
MPC8347EA
MPC8343EA
MPC8349EARM
Rev. 1
08/2006
Document Number: MPC8349EARM
Rev. 1, 08/2006
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Preface PRE
Overview 1
Memory Map 2
Signal Descriptions 3
Reset, Clocking, and Initialization 4
System Configuration 5
Arbiter and Bus Monitor 6
e300 Processor Core 7
Integrated Programmable Interrupt Controller (IPIC) 8
DDR Memory Controller 9
Local Bus Controller
10
Sequencer 11
DMA 12
PCI Bus Interface 13
Security Engine (SEC) 2.0 14
Three-Speed Ethernet Controllers 15
Universal Serial Bus Interface 16
I
2
C Interfaces 17
DUART 18
Serial Peripheral Interface 19
JTAG/Testing Support 20
General Purpose I/O (GPIO) 21
Delay Lock Loop (DLL) 22
Revision History APP
Glossary GLO
Register Index REG
General Index IND
PRE Preface
1 Overview
2 Memory Map
3 Signal Descriptions
4 Reset, Clocking, and Initialization
5 System Configuration
6 Arbiter and Bus Monitor
7 e300 Processor Core
8 Integrated Programmable Interrupt Controller (IPIC)
9 DDR Memory Controller
10 Local Bus Controller
11 Sequencer
12 DMA
13 PCI Bus Interface
14 Security Engine (SEC) 2.0
15 Three-Speed Ethernet Controller
16 Universal Serial Bus Interface
17 I
2
C Interface
18 DUART
19 Serial Peripheral Interface
20 JTAG/Testing Support
21 General Purpose I/O (GPIO)
22 Delay Lock Loop (DLL)
23
APP Revision History
GLO Glossary
REG Register Index
IND General Index
MPC8349EA PowerQUICC II Pro Integrated Host Processor Family Reference Manual, Rev. 1
Freescale Semiconductor v
Contents
Paragraph
Number Title
Page
Number
Co nt ents
About This Book
Audience........................................................................................................................ lxxv
Organization................................................................................................................... lxxv
Suggested Reading....................................................................................................... lxxvii
Conventions ................................................................................................................lxxviii
Signal Conventions....................................................................................................... lxxix
Acronyms and Abbreviations ....................................................................................... lxxix
Chapter 1
Overview
1.1 MPC834x-Family Product Distinctions...........................................................................1-1
1.2 MPC8349EA PowerQUICC II Pro Processor Overview ................................................ 1-2
1.3 MPC8349EA Architecture Overview.............................................................................. 1-7
1.3.1 PowerPC Core.............................................................................................................. 1-7
1.3.2 Security Engine......................................................................................................... 1-10
1.3.3 DDR Memory Controller........................................................................................... 1-10
1.3.4 Dual Three-Speed Ethernet Controllers..................................................................... 1-11
1.3.5 PCI Controllers.......................................................................................................... 1-12
1.3.5.1 PCI Bus Arbitration Unit....................................................................................... 1-12
1.3.6 Universal Serial Bus (USB) 2.0................................................................................. 1-12
1.3.6.1 USB Dual-Role Controller .................................................................................... 1-13
1.3.6.2 USB Multi-Port Host Controller............................................................................ 1-14
1.3.7 Local Bus Controller (LBC) ...................................................................................... 1-14
1.3.8 Integrated Programmable Interrupt Controller (IPIC)...............................................1-15
1.3.9 Dual I
2
C Interfaces .................................................................................................... 1-15
1.3.10 DMA Controller......................................................................................................... 1-16
1.3.11 Dual Universal Asynchronous Receiver/Transmitter (DUART)...............................1-16
1.3.12 Serial Peripheral Interface (SPI)................................................................................ 1-17
1.3.13 System Timers ........................................................................................................... 1-17
1.4 Applications...................................................................................................................1-18
1.5 Differences Between MPC8349E and MPC8349EA .................................................... 1-18
MPC8349EA PowerQUICC II Pro Integrated Host Processor Family Reference Manual, Rev. 1
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Contents
Paragraph
Number Title
Page
Number
Chapter 2
Memory Map
2.1 Internal Memory Mapped Registers ................................................................................ 2-1
2.2 Accessing IMMR Memory From the Local Processor.................................................... 2-1
2.3 Complete IMMR Map ..................................................................................................... 2-1
Chapter 3
Signal Descriptions
3.1 Signals Overview.............................................................................................................3-1
3.2 Configuration Signals Sampled at Reset ....................................................................... 3-19
3.3 Output Signal States During Reset ................................................................................ 3-19
Chapter 4
Reset, Clocking, and Initialization
4.1 External Signals ...............................................................................................................4-1
4.1.1 Reset Signals................................................................................................................4-1
4.1.2 Clock Signals...............................................................................................................4-3
4.2 Functional Description..................................................................................................... 4-3
4.2.1 Reset Operations.......................................................................................................... 4-3
4.2.1.1 Reset Causes............................................................................................................ 4-4
4.2.1.2 Reset Actions........................................................................................................... 4-4
4.2.2 Power-On Reset Flow.................................................................................................. 4-5
4.2.3 Hard Reset Flow .......................................................................................................... 4-7
4.2.4 Soft Reset Flow............................................................................................................4-8
4.3 Reset Configuration......................................................................................................... 4-8
4.3.1 Reset Configuration Signals ........................................................................................ 4-9
4.3.1.1 Reset Configuration Word Source........................................................................... 4-9
4.3.1.2 CLKIN Division .................................................................................................... 4-10
4.3.1.3 Selecting Reset Configuration Input Signals.........................................................4-10
4.3.2 Reset Configuration Words........................................................................................ 4-11
4.3.2.1 Reset Configuration Word Low Register (RCWLR)............................................. 4-11
4.3.2.1.1 System PLL Configuration................................................................................ 4-12
4.3.2.2 Reset Configuration Word High Register (RCWHR)............................................4-14
4.3.2.2.1 PCI Host/Agent Configuration.......................................................................... 4-16
4.3.2.2.2 Boot Memory Space (BMS).............................................................................. 4-16
4.3.2.2.3 Boot Sequencer Configuration .......................................................................... 4-17
4.3.2.2.4 Boot ROM Location .......................................................................................... 4-17
4.3.2.2.5 TSEC1 Mode ..................................................................................................... 4-19
MPC8349EA PowerQUICC II Pro Integrated Host Processor Family Reference Manual, Rev. 1
Freescale Semiconductor vii
Contents
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Number Title
Page
Number
4.3.2.2.6 TSEC2 Mode ..................................................................................................... 4-20
4.3.2.2.7 e300 Core True Little-Endian............................................................................ 4-20
4.3.2.2.8 LALE Configuration.......................................................................................... 4-21
4.3.2.2.9 LDP Configuration ............................................................................................ 4-21
4.3.3 Loading the Reset Configuration Words ................................................................... 4-21
4.3.3.1 Loading from Local Bus EEPROM....................................................................... 4-21
4.3.3.1.1 Local Bus EEPROM Timing.............................................................................4-23
4.3.3.2 Loading from I2C EEPROM................................................................................. 4-24
4.3.3.2.1 Using the Boot Sequencer Reset Configuration................................................4-24
4.3.3.2.2 EEPROM Calling Address................................................................................ 4-24
4.3.3.2.3 EEPROM Data Format in Reset Configuration Mode...................................... 4-24
4.3.3.2.4 Reset Configuration Load Fail .......................................................................... 4-27
4.3.3.3 Default Reset Configuration Words....................................................................... 4-27
4.3.3.3.1 Hard-Coded Reset Configuration Word Low.................................................... 4-27
4.3.3.3.2 Hard-Coded Reset Configuration Word High Fields Values............................. 4-28
4.3.3.3.3 Examples for Hard-Coded Reset Configuration Words Usage ......................... 4-29
4.4 Clocking ........................................................................................................................4-29
4.4.1 Clocking in PCI Host Mode....................................................................................... 4-30
4.4.1.1 PCI Clock Outputs (PCI_CLK_OUT[0:7])...........................................................4-30
4.4.2 Clocking In PCI Agent Mode.................................................................................... 4-30
4.4.3 System Clock Domains.............................................................................................. 4-30
4.5 Memory Map/Register Definition ................................................................................. 4-32
4.5.1 Reset Configuration Registers Descriptions.............................................................. 4-32
4.5.1.1 Reset Configuration Word Low Register (RCWLR)............................................. 4-32
4.5.1.2 Reset Configuration Word High Register (RCWHR)............................................4-32
4.5.1.3 Reset Status Register (RSR) .................................................................................. 4-33
4.5.1.4 Reset Mode Register (RMR) ................................................................................. 4-34
4.5.1.5 Reset Protection Register (RPR) ........................................................................... 4-35
4.5.1.6 Reset Control Register (RCR) ............................................................................... 4-36
4.5.1.7 Reset Control Enable Register (RCER)................................................................. 4-36
4.5.2 Clock Configuration Registers................................................................................... 4-37
4.5.2.1 System PLL Mode Register (SPMR) .................................................................... 4-37
4.5.2.2 Output Clock Control Register (OCCR)................................................................ 4-38
4.5.2.3 System Clock Control Register (SCCR)................................................................ 4-40
4.5.3 Clock Control DDR Registers ................................................................................... 4-41
4.5.3.1 MCK Enable Register (MCKENR)....................................................................... 4-41
MPC8349EA PowerQUICC II Pro Integrated Host Processor Family Reference Manual, Rev. 1
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Contents
Paragraph
Number Title
Page
Number
Chapter 5
System Configuration
5.1 Introduction...................................................................................................................... 5-1
5.2 Local Memory Map Overview and Example .................................................................. 5-1
5.2.1 Address Translation and Mapping............................................................................... 5-3
5.2.2 Window into Configuration Space............................................................................... 5-3
5.2.3 Local Access Windows................................................................................................ 5-4
5.2.3.1 Local Access Register Memory Map ...................................................................... 5-4
5.2.4 Local Access Register Descriptions ............................................................................ 5-5
5.2.4.1 Internal Memory Map Registers Base Address Register (IMMRBAR).................. 5-5
5.2.4.1.1 Updating IMMRBAR.......................................................................................... 5-6
5.2.4.2 Alternate Configuration Base Address Register (ALTCBAR)................................5-7
5.2.4.3 LBC Local Access Window n Base Address Registers
(LBLAWBAR0–LBLAWBAR3) ........................................................................ 5-7
5.2.4.3.1 LBLAWBAR0[BASE_ADDR] Reset Value.......................................................5-8
5.2.4.4 LBC Local Access Window n Attributes Registers
(LBLAWAR0–LBLAWAR3)............................................................................... 5-8
5.2.4.4.1 LBLAWAR0[EN] and LBLAWAR0[SIZE] Reset Value ....................................5-9
5.2.4.5 PCI Local Access Window n Base Address Register
(PCILAWBAR0–PCILAWBAR1)...................................................................... 5-9
5.2.4.5.1 PCILAWBAR0[BASE_ADDR] Reset Value....................................................5-10
5.2.4.6 PCI Local Access Window n Attributes Registers
(PCILAWAR0–PCILAWAR1) .......................................................................... 5-10
5.2.4.6.1 PCILAWAR0[EN] and PCILAWAR0[SIZE] Reset Value................................ 5-11
5.2.4.7 DDR Local Access Window n Base Address Registers
(DDRLAWBAR0–DDRLAWBAR1)................................................................ 5-12
5.2.4.7.1 DDRLAWBAR0[BASE_ADDR] Reset Value.................................................. 5-12
5.2.4.8 DDR Local Access Window n Attributes Registers
(DDRLAWAR0–DDRLAWAR1)...................................................................... 5-13
5.2.4.8.1 DDRLAWAR0[EN] and DDRLAWAR0[SIZE] Reset Value............................5-13
5.2.5 Precedence of Local Access Windows ...................................................................... 5-14
5.2.6 Configuring Local Access Windows ......................................................................... 5-14
5.2.7 Distinguishing Local Access Windows from Other Mapping Functions.................. 5-14
5.2.8 Outbound Address Translation and Mapping Windows............................................ 5-15
5.2.9 Inbound Address Translation and Mapping Windows .............................................. 5-15
5.2.9.1 PCI1/PCI2 Inbound Windows ...............................................................................5-15
5.2.10 Internal Memory Map................................................................................................ 5-15
5.2.11 Accessing Internal Memory from External Masters.................................................. 5-16
5.3 System Configuration .................................................................................................... 5-16
5.3.1 System Configuration Register Memory Map........................................................... 5-16
MPC8349EA PowerQUICC II Pro Integrated Host Processor Family Reference Manual, Rev. 1
Freescale Semiconductor ix
Contents
Paragraph
Number Title
Page
Number
5.3.2 System Configuration Registers ................................................................................ 5-17
5.3.2.1 System General Purpose Register Low (SGPRL) ................................................. 5-17
5.3.2.2 System General Purpose Register High (SGPRH)................................................5-17
5.3.2.3 System Part and Revision ID Register (SPRIDR).................................................5-18
5.3.2.3.1 SPRIDR[PARTID] Coding................................................................................ 5-18
5.3.2.4 System Priority and Configuration Register (SPCR) ............................................ 5-19
5.3.2.5 System I/O Configuration Register Low (SICRL)................................................ 5-21
5.3.2.6 System I/O Configuration Register High (SICRH)............................................... 5-24
5.3.2.7 Debug Configuration............................................................................................. 5-28
5.3.2.7.1 DDR Debug Configuration................................................................................5-28
5.3.2.7.2 Local Bus Debug Configuration........................................................................ 5-28
5.3.2.8 DDR Control Driver Register (DDRCDR)............................................................ 5-28
5.3.2.9 DDR Debug Status Register (DDRDSR) .............................................................. 5-30
5.4 Software Watchdog Timer (WDT)................................................................................. 5-31
5.4.1 Overview....................................................................................................................5-31
5.4.2 Features...................................................................................................................... 5-32
5.4.3 Modes of Operation ................................................................................................... 5-32
5.4.4 Memory Map/Register Definition ............................................................................. 5-33
5.4.4.1 System Watchdog Control Register (SWCRR).....................................................5-33
5.4.4.2 System Watchdog Count Register (SWCNR) .......................................................5-34
5.4.4.3 System Watchdog Service Register (SWSRR)...................................................... 5-34
5.4.5 Functional Description............................................................................................... 5-35
5.4.5.1 Software Watchdog Timer Unit............................................................................. 5-35
5.4.5.2 Modes of Operation............................................................................................... 5-37
5.4.6 Initialization/Application Information....................................................................... 5-38
5.4.6.1 WDT Programming Guidelines............................................................................. 5-38
5.5 Real Time Clock Module (RTC).................................................................................... 5-38
5.5.1 Overview....................................................................................................................5-38
5.5.2 Features...................................................................................................................... 5-39
5.5.3 Modes of Operation ................................................................................................... 5-39
5.5.4 External Signal Description....................................................................................... 5-39
5.5.4.1 Overview................................................................................................................ 5-39
5.5.4.2 Detailed Signal Descriptions ................................................................................. 5-39
5.5.5 Memory Map/Register Definition ............................................................................. 5-40
5.5.5.1 Real Time Counter Control Register (RTCNR) .................................................... 5-40
5.5.5.2 Real Time Counter Load Register (RTLDR).........................................................5-41
5.5.5.3 Real Time Counter Prescale Register (RTPSR) .................................................... 5-41
5.5.5.4 Real Time Counter Register (RTCTR).................................................................. 5-42
5.5.5.5 Real Time Counter Event Register (RTEVR)........................................................ 5-42
5.5.5.6 Real Time Counter Alarm Register (RTALR).......................................................5-43
5.5.6 Functional Description............................................................................................... 5-43
MPC8349EA PowerQUICC II Pro Integrated Host Processor Family Reference Manual, Rev. 1
x Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
5.5.6.1 Real Time Counter Unit.........................................................................................5-43
5.5.6.2 RTC Operational Modes........................................................................................ 5-44
5.5.7 RTC Programming Guidelines................................................................................... 5-45
5.6 Periodic Interval Timer (PIT) ........................................................................................ 5-45
5.6.1 Overview....................................................................................................................5-45
5.6.2 Features...................................................................................................................... 5-46
5.6.3 Modes of Operation ................................................................................................... 5-46
5.6.4 External Signal Description....................................................................................... 5-46
5.6.4.1 Overview................................................................................................................ 5-46
5.6.4.2 Detailed Signal Description................................................................................... 5-47
5.6.5 Memory Map/Register Definition ............................................................................. 5-47
5.6.5.1 Periodic Interval Timer Control Register (PTCNR)..............................................5-47
5.6.5.2 Periodic Interval Timer Load Register (PTLDR)..................................................5-48
5.6.5.3 Periodic Interval Timer Prescale Register (PTPSR)..............................................5-49
5.6.5.4 Periodic Interval Timer Counter Register (PTCTR).............................................. 5-49
5.6.5.5 Periodic Interval Timer Event Register (PTEVR) ................................................. 5-50
5.6.6 Functional Description............................................................................................... 5-50
5.6.6.1 Periodic Interval Timer Unit.................................................................................. 5-50
5.6.6.2 PIT Operational Modes.......................................................................................... 5-51
5.6.7 PIT Programming Guidelines.................................................................................... 5-51
5.7 General-Purpose Timers (GTMs)................................................................................... 5-52
5.7.1 Overview....................................................................................................................5-52
5.7.2 Features...................................................................................................................... 5-53
5.7.3 Modes of Operation ................................................................................................... 5-53
5.7.3.1 Cascaded Modes.................................................................................................... 5-53
5.7.3.2 Clock Source Modes.............................................................................................. 5-54
5.7.3.3 Reference Modes ................................................................................................... 5-54
5.7.3.4 Capture Modes....................................................................................................... 5-54
5.7.4 External Signal Description....................................................................................... 5-54
5.7.4.1 Overview................................................................................................................ 5-54
5.7.4.2 Detailed Signal Descriptions ................................................................................. 5-55
5.7.5 Memory Map/Register Definition ............................................................................. 5-56
5.7.5.1 Global Timers Configuration Registers (GTCFRn)............................................... 5-57
5.7.5.2 Global Timers Mode Registers (GTMDR1–GTMDR4)........................................ 5-60
5.7.5.3 Global Timers Reference Registers (GTRFR1–GTRFR4) .................................... 5-62
5.7.5.4 Global Timers Capture Registers (GTCPR1–GTCPR4)........................................ 5-62
5.7.5.5 Global Timers Counter Registers (GTCNR1–GTCNR4) ...................................... 5-63
5.7.5.6 Global Timers Event Registers (GTEVR1–GTEVR4) .......................................... 5-63
5.7.5.7 Global Timers Prescale Registers (GTPSR1–GTPSR4)........................................ 5-64
5.7.6 Functional Description............................................................................................... 5-65
5.7.6.1 General-Purpose Timer Units................................................................................ 5-65
MPC8349EA PowerQUICC II Pro Integrated Host Processor Family Reference Manual, Rev. 1
Freescale Semiconductor xi
Contents
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Number Title
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Number
5.7.6.2 Reference Modes ................................................................................................... 5-65
5.7.6.3 Capture Modes....................................................................................................... 5-65
5.7.6.4 Cascaded Modes.................................................................................................... 5-66
5.7.7 Initialization/Application Information....................................................................... 5-68
5.7.7.1 Programming Guidelines....................................................................................... 5-68
5.7.7.1.1 GTM Registers................................................................................................... 5-68
5.8 Power Management Control.......................................................................................... 5-68
5.8.1 Modes of Operation ................................................................................................... 5-68
5.8.2 External Signal Description....................................................................................... 5-69
5.8.3 Memory Map/Register Definition ............................................................................. 5-69
5.8.3.1 Power Management Controller Configuration Register (PMCCR)....................... 5-69
5.8.3.2 Power Management Controller Event Register (PMCER)....................................5-70
5.8.3.3 Power Management Controller Mask Register (PMCMR) ................................... 5-71
5.8.4 Functional Description............................................................................................... 5-71
5.8.4.1 Dynamic Power Management................................................................................ 5-71
5.8.4.2 Shutting Down Unused Blocks.............................................................................. 5-72
5.8.4.3 Software-Controlled Power-Down States.............................................................. 5-72
5.8.4.3.1 Entering Low Power States—Core-Only Mode................................................ 5-72
5.8.4.3.2 Entering Low Power States—Core and System Mode...................................... 5-72
5.8.4.4 Exiting Core and System Low Power States.........................................................5-73
5.8.4.4.1 Exiting Low Power States—Core-Only Mode.................................................. 5-73
5.8.4.4.2 Exiting Low Power States—Core and System Mode........................................ 5-73
5.8.5 Initialization/Application Information....................................................................... 5-74
5.8.5.1 Core Disable in Low Power Mode ........................................................................ 5-74
Chapter 6
Arbiter and Bus Monitor
6.1 Overview.......................................................................................................................... 6-1
6.1.1 Coherent System Bus Overview.................................................................................. 6-1
6.2 Arbiter Memory Map/Register Definition....................................................................... 6-2
6.2.1 Arbiter Configuration Register (ACR)........................................................................ 6-2
6.2.2 Arbiter Timers Register (ATR).................................................................................... 6-4
6.2.3 Arbiter Event Register (AER)...................................................................................... 6-5
6.2.4 Arbiter Interrupt Definition Register (AIDR).............................................................. 6-6
6.2.5 Arbiter Mask Register (AMR)..................................................................................... 6-7
6.2.6 Arbiter Event Attributes Register (AEATR)................................................................ 6-7
6.2.7 Arbiter Event Address Register (AEADR).................................................................. 6-9
6.2.8 Arbiter Event Response Register (AERR)................................................................. 6-10
6.3 Functional Description................................................................................................... 6-11
6.3.1 Arbitration Policy ...................................................................................................... 6-11
MPC8349EA PowerQUICC II Pro Integrated Host Processor Family Reference Manual, Rev. 1
xii Freescale Semiconductor
Contents
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Number Title
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Number
6.3.1.1 Address Bus Arbitration with PRIORITY[0:1]..................................................... 6-12
6.3.1.2 Address Bus Arbitration with REPEAT ................................................................ 6-13
6.3.1.3 Address Bus Arbitration after ARTRY
.................................................................. 6-13
6.3.1.4 Address Bus Parking.............................................................................................. 6-13
6.3.1.5 Data Bus Arbitration.............................................................................................. 6-13
6.3.2 Bus Error Detection ................................................................................................... 6-14
6.3.2.1 Address Time Out.................................................................................................. 6-14
6.3.2.2 Data Time Out ....................................................................................................... 6-14
6.3.2.3 Transfer Error ........................................................................................................ 6-14
6.3.2.4 Address Only Transaction Type............................................................................. 6-15
6.3.2.5 Reserved Transaction Type.................................................................................... 6-15
6.3.2.6 Illegal (eciwx/ecowx) Transaction Type................................................................ 6-16
6.4 Initialization/Applications Information ......................................................................... 6-16
6.4.1 Initialization Sequence...............................................................................................6-16
6.4.2 Error Handling Sequence........................................................................................... 6-17
Chapter 7
e300 Processor Core Overview
7.1 Overview.......................................................................................................................... 7-1
7.1.1 Features........................................................................................................................ 7-3
7.1.2 Instruction Unit............................................................................................................ 7-6
7.1.2.1 Instruction Queue and Dispatch Unit ...................................................................... 7-6
7.1.2.2 Branch Processing Unit (BPU)................................................................................ 7-7
7.1.3 Independent Execution Units....................................................................................... 7-7
7.1.3.1 Integer Unit (IU)...................................................................................................... 7-7
7.1.3.2 Floating-Point Unit (FPU)....................................................................................... 7-7
7.1.3.3 Load/Store Unit (LSU) ............................................................................................ 7-8
7.1.3.4 System Register Unit (SRU).................................................................................... 7-8
7.1.4 Completion Unit .......................................................................................................... 7-8
7.1.5 Memory Subsystem Support........................................................................................ 7-8
7.1.5.1 Memory Management Units (MMUs)..................................................................... 7-9
7.1.5.2 Cache Units............................................................................................................ 7-10
7.1.6 Bus Interface Unit (BIU) ........................................................................................... 7-10
7.1.7 System Support Functions......................................................................................... 7-11
7.1.7.1 Power Management ............................................................................................... 7-11
7.1.7.2 Time Base/Decrementer ........................................................................................ 7-11
7.1.7.3 JTAG Test and Debug Interface............................................................................. 7-12
7.1.7.4 Clock Multiplier.....................................................................................................7-12
7.2 PowerPC Architecture Implementation........................................................................ 7-12
7.3 Implementation-Specific Information............................................................................ 7-12
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7.3.1 Register Model........................................................................................................... 7-13
7.3.1.1 UISA Registers...................................................................................................... 7-15
7.3.1.1.1 General-Purpose Registers (GPRs) ................................................................... 7-15
7.3.1.1.2 Floating-Point Registers (FPRs)........................................................................ 7-15
7.3.1.1.3 Condition Register (CR).................................................................................... 7-15
7.3.1.1.4 Floating-Point Status and Control Register (FPSCR) .......................................7-15
7.3.1.1.5 User-Level SPRs................................................................................................ 7-15
7.3.1.2 VEA Registers ....................................................................................................... 7-16
7.3.1.3 OEA Registers ....................................................................................................... 7-16
7.3.1.3.1 Machine State Register (MSR).......................................................................... 7-16
7.3.1.3.2 Segment Registers (SRs) ................................................................................... 7-18
7.3.1.3.3 Supervisor-Level SPRs...................................................................................... 7-18
7.3.2 Instruction Set and Addressing Modes...................................................................... 7-25
7.3.2.1 PowerPC Instruction Set and Addressing Modes..................................................7-25
7.3.2.2 Implementation-Specific Instruction Set ............................................................... 7-26
7.3.3 Cache Implementation............................................................................................... 7-27
7.3.3.1 PowerPC Cache Characteristics ............................................................................ 7-27
7.3.3.2 Implementation-Specific Cache Implementation..................................................7-27
7.3.3.3 Instruction and Data Cache Way-Locking............................................................. 7-29
7.3.4 Interrupt Model.......................................................................................................... 7-29
7.3.4.1 PowerPC Interrupt Model...................................................................................... 7-29
7.3.4.2 Implementation-Specific Interrupt Model ............................................................. 7-30
7.3.5 Memory Management................................................................................................ 7-33
7.3.5.1 PowerPC Memory Management............................................................................ 7-33
7.3.5.2 Implementation-Specific Memory Management...................................................7-33
7.3.6 Instruction Timing ..................................................................................................... 7-34
7.3.7 Core Interface ............................................................................................................ 7-35
7.3.7.1 Memory Accesses.................................................................................................. 7-36
7.3.7.2 Signals....................................................................................................................7-36
7.3.8 Debug Features ......................................................................................................... 7-37
7.3.8.1 Breakpoint Signaling ............................................................................................. 7-37
7.4 Differences Between Cores............................................................................................ 7-38
Chapter 8
Integrated Programmable Interrupt Controller (IPIC)
8.1 Introduction...................................................................................................................... 8-1
8.2 Features............................................................................................................................8-4
8.3 Modes of Operation ......................................................................................................... 8-4
8.3.1 Core Enable Mode ....................................................................................................... 8-4
8.3.2 Core Disable Mode...................................................................................................... 8-5
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8.4 External Signal Description............................................................................................. 8-5
8.4.1 Overview...................................................................................................................... 8-5
8.4.2 Detailed Signal Descriptions ....................................................................................... 8-6
8.5 Memory Map/Register Definition ................................................................................... 8-6
8.5.1 System Global Interrupt Configuration Register (SICFR)..........................................8-8
8.5.2 System Global Interrupt Vector Register (SIVCR)......................................................8-9
8.5.3 System Internal Interrupt Pending Registers (SIPNR_H and SIPNR_L).................. 8-11
8.5.4 System Internal Interrupt Group A Priority Register (SIPRR_A).............................8-14
8.5.5 System Internal Interrupt Group D Priority Register (SIPRR_D).............................8-14
8.5.6 System Internal Interrupt Mask Register (SIMSR_H and SIMSR_L) ...................... 8-15
8.5.7 System Internal Interrupt Control Register (SICNR)................................................ 8-16
8.5.8 System External Interrupt Pending Register (SEPNR).............................................. 8-18
8.5.9 System Mixed Interrupt Group A Priority Register (SMPRR_A)............................. 8-18
8.5.10 System Mixed Interrupt Group B Priority Register (SMPRR_B)............................. 8-19
8.5.11 System External Interrupt Mask Register (SEMSR)................................................. 8-20
8.5.12 System External Interrupt Control Register (SECNR).............................................. 8-21
8.5.13 System Error Status Register (SERSR) ..................................................................... 8-22
8.5.14 System Error Mask Register (SERMR)..................................................................... 8-23
8.5.15 System Error Control Register (SERCR) .................................................................. 8-24
8.5.16 System Internal Interrupt Force Registers (SIFCR_H and SIFCR_L) ...................... 8-25
8.5.17 System External Interrupt Force Register (SEFCR).................................................. 8-26
8.5.18 System Error Force Register (SERFR)...................................................................... 8-26
8.5.19 System Critical Interrupt Vector Register (SCVCR).................................................8-27
8.5.20 System Management Interrupt Vector Register (SMVCR) ....................................... 8-27
8.6 Functional Description................................................................................................... 8-28
8.6.1 Interrupt Types........................................................................................................... 8-28
8.6.2 Interrupt Configuration.............................................................................................. 8-29
8.6.3 Internal Interrupts Group Relative Priority................................................................ 8-30
8.6.4 Mixed Interrupts Group Relative Priority..................................................................8-30
8.6.5 Highest Priority Interrupt........................................................................................... 8-31
8.6.6 Interrupt Source Priorities..........................................................................................8-31
8.6.7 Masking Interrupt Sources......................................................................................... 8-34
8.6.8 Interrupt Vector Generation and Calculation............................................................. 8-35
8.6.9 Machine Check Interrupts.......................................................................................... 8-35
Chapter 9
DDR Memory Controller
9.1 Introduction...................................................................................................................... 9-1
9.2 Features............................................................................................................................9-2
9.2.1 Modes of Operation ..................................................................................................... 9-3
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9.3 External Signal Descriptions ........................................................................................... 9-3
9.3.1 Signals Overview......................................................................................................... 9-3
9.3.2 Detailed Signal Descriptions ....................................................................................... 9-5
9.3.2.1 Memory Interface Signals........................................................................................ 9-5
9.3.2.2 Clock Interface Signals............................................................................................ 9-8
9.3.2.3 Debug Signals.......................................................................................................... 9-9
9.4 Memory Map/Register Definition ................................................................................... 9-9
9.4.1 Register Descriptions................................................................................................. 9-10
9.4.1.1 Chip Select Memory Bounds (CSn_BNDS)..........................................................9-10
9.4.1.2 Chip Select Configuration (CSn_CONFIG).......................................................... 9-11
9.4.1.3 DDR SDRAM Timing Configuration 3 (TIMING_CFG_3).................................9-13
9.4.1.4 DDR SDRAM Timing Configuration 0 (TIMING_CFG_0).................................9-14
9.4.1.5 DDR SDRAM Timing Configuration 1 (TIMING_CFG_1).................................9-16
9.4.1.6 DDR SDRAM Timing Configuration 2 (TIMING_CFG_2).................................9-18
9.4.1.7 DDR SDRAM Control Configuration (DDR_SDRAM_CFG)............................. 9-20
9.4.1.8 DDR SDRAM Control Configuration 2 (DDR_SDRAM_CFG_2)...................... 9-22
9.4.1.9 DDR SDRAM Mode Configuration (DDR_SDRAM_MODE)............................9-24
9.4.1.10 DDR SDRAM Mode 2 Configuration (DDR_SDRAM_MODE_2)..................... 9-24
9.4.1.11 DDR SDRAM Mode Control Register (DDR_SDRAM_MD_CNTL)................. 9-25
9.4.1.12 DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) ................. 9-27
9.4.1.13 DDR SDRAM Data Initialization (DDR_DATA_INIT) .......................................9-28
9.4.1.14 DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL).............................9-28
9.4.1.15 DDR Initialization Address (DDR_INIT_ADDR)................................................ 9-29
9.4.1.16 DDR IP Block Revision 1 (DDR_IP_REV1)........................................................9-30
9.4.1.17 DDR IP Block Revision 2 (DDR_IP_REV2)........................................................9-30
9.4.1.18 Memory Data Path Error Injection Mask High (DATA_ERR_INJECT_HI)........ 9-31
9.4.1.19 Memory Data Path Error Injection Mask Low (DATA_ERR_INJECT_LO)........ 9-31
9.4.1.20 Memory Data Path Error Injection Mask ECC (ERR_INJECT)........................... 9-32
9.4.1.21 Memory Data Path Read Capture High (CAPTURE_DATA_HI)......................... 9-32
9.4.1.22 Memory Data Path Read Capture Low (CAPTURE_DATA_LO)........................ 9-33
9.4.1.23 Memory Data Path Read Capture ECC (CAPTURE_ECC)..................................9-33
9.4.1.24 Memory Error Detect (ERR_DETECT)................................................................ 9-33
9.4.1.25 Memory Error Disable (ERR_DISABLE)............................................................. 9-34
9.4.1.26 Memory Error Interrupt Enable (ERR_INT_EN).................................................. 9-35
9.4.1.27 Memory Error Attributes Capture (CAPTURE_ATTRIBUTES).......................... 9-36
9.4.1.28 Memory Error Address Capture (CAPTURE_ADDRESS) .................................. 9-37
9.4.1.29 Single-Bit ECC Memory Error Management (ERR_SBE) ...................................9-37
9.5 Functional Description................................................................................................... 9-38
9.5.1 DDR SDRAM Interface Operation............................................................................ 9-43
9.5.1.1 Supported DDR SDRAM Organizations............................................................... 9-43
9.5.2 DDR SDRAM Address Multiplexing........................................................................ 9-45
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9.5.3 JEDEC Standard DDR SDRAM Interface Commands .............................................9-49
9.5.4 DDR SDRAM Interface Timing................................................................................ 9-51
9.5.4.1 Clock Distribution ................................................................................................. 9-54
9.5.5 DDR SDRAM Mode-Set Command Timing.............................................................9-55
9.5.6 DDR SDRAM Registered DIMM Mode................................................................... 9-56
9.5.7 DDR SDRAM Write Timing Adjustments................................................................ 9-56
9.5.8 DDR SDRAM Refresh .............................................................................................. 9-57
9.5.8.1 DDR SDRAM Refresh Timing.............................................................................. 9-58
9.5.8.2 DDR SDRAM Refresh and Power-Saving Modes................................................9-58
9.5.8.2.1 Self-Refresh in Sleep Mode............................................................................... 9-60
9.5.9 DDR Data Beat Ordering........................................................................................... 9-61
9.5.10 Page Mode and Logical Bank Retention ................................................................... 9-61
9.5.11 Error Checking and Correcting (ECC) ...................................................................... 9-62
9.5.12 Error Management..................................................................................................... 9-64
9.6 Initialization/Application Information...........................................................................9-65
9.6.1 Programming Differences Between Memory Types..................................................9-66
9.6.2 DDR SDRAM Initialization Sequence...................................................................... 9-69
9.6.3 Using Forced Self-Refresh Mode to Implement a Battery-Backed
RAM System ......................................................................................................... 9-69
9.6.3.1 Hardware Based Self-Refresh Scheme.................................................................. 9-69
9.6.3.2 Software Based Self-Refresh Scheme ................................................................... 9-70
9.6.3.3 Bypassing Re-initialization During Battery-Backed Operation............................ 9-70
Chapter 10
Local Bus Controller
10.1 Introduction....................................................................................................................10-1
10.1.1 Features......................................................................................................................10-2
10.1.2 Modes of Operation ................................................................................................... 10-3
10.1.2.1 LBC Bus Clock and Clock Ratios ......................................................................... 10-3
10.1.2.2 Source ID Debug Mode......................................................................................... 10-3
10.2 External Signal Descriptions ......................................................................................... 10-4
10.3 Memory Map/Register Definition ................................................................................. 10-9
10.3.1 Register Descriptions............................................................................................... 10-10
10.3.1.1 Base Registers (BR0–BR7) ................................................................................. 10-11
10.3.1.2 Option Registers (OR0–OR7).............................................................................. 10-12
10.3.1.2.1 Address Mask .................................................................................................. 10-12
10.3.1.2.2 Option Registers (ORn)—GPCM Mode .........................................................10-13
10.3.1.2.3 Option Registers (ORn)—UPM Mode............................................................ 10-16
10.3.1.2.4 Option Registers (ORn)—SDRAM Mode ...................................................... 10-17
10.3.1.3 UPM Memory Address Register (MAR)............................................................. 10-18
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10.3.1.4 UPM Mode Registers (MnMR)........................................................................... 10-19
10.3.1.5 Memory Refresh Timer Prescaler Register (MRTPR) ........................................ 10-21
10.3.1.6 UPM Data Register (MDR)................................................................................. 10-22
10.3.1.7 Local Bus SDRAM Machine Mode Register (LSDMR).....................................10-22
10.3.1.8 UPM Refresh Timer (LURT)............................................................................... 10-24
10.3.1.9 SDRAM Refresh Timer (LSRT).......................................................................... 10-25
10.3.1.10 Transfer Error Status Register (LTESR).............................................................. 10-26
10.3.1.11 Transfer Error Check Disable Register (LTEDR)................................................10-27
10.3.1.12 Transfer Error Interrupt Enable Register (LTEIR) .............................................. 10-27
10.3.1.13 Transfer Error Attributes Register (LTEATR).....................................................10-28
10.3.1.14 Transfer Error Address Register (LTEAR)..........................................................10-29
10.3.1.15 Local Bus Configuration Register (LBCR).........................................................10-29
10.3.1.16 Clock Ratio Register (LCRR).............................................................................. 10-30
10.4 Functional Description................................................................................................. 10-31
10.4.1 Basic Architecture.................................................................................................... 10-32
10.4.1.1 Address and Address Space Checking ................................................................ 10-32
10.4.1.2 External Address Latch Enable Signal (LALE) .................................................. 10-33
10.4.1.3 Data Transfer Acknowledge (TA) ....................................................................... 10-34
10.4.1.4 Data Buffer Control (LBCTL)............................................................................. 10-35
10.4.1.5 Parity Generation and Checking (LDP)............................................................... 10-35
10.4.1.6 Bus Monitor......................................................................................................... 10-35
10.4.2 General-Purpose Chip-Select Machine (GPCM).....................................................10-35
10.4.2.1 Timing Configuration .......................................................................................... 10-37
10.4.2.2 Chip-Select Assertion Timing .............................................................................10-40
10.4.2.2.1 Programmable Wait State Configuration......................................................... 10-41
10.4.2.2.2 Chip-Select and Write Enable Negation Timing.............................................10-41
10.4.2.2.3 Relaxed Timing ............................................................................................... 10-42
10.4.2.2.4 Output Enable (LOE) Timing.......................................................................... 10-45
10.4.2.2.5 Extended Hold Time on Read Accesses.......................................................... 10-45
10.4.2.3 External Access Termination (LGTA) ................................................................. 10-46
10.4.2.4 Boot Chip-Select Operation................................................................................. 10-47
10.4.3 SDRAM Machine.................................................................................................... 10-48
10.4.3.1 Supported SDRAM Configurations..................................................................... 10-48
10.4.3.2 SDRAM Power-On Initialization ........................................................................ 10-49
10.4.3.3 Intel PC133 and JEDEC-Standard SDRAM Interface Commands..................... 10-50
10.4.3.4 Page Hit Checking............................................................................................... 10-51
10.4.3.5 Page Management................................................................................................ 10-51
10.4.3.6 SDRAM Address Multiplexing........................................................................... 10-51
10.4.3.7 SDRAM Device-Specific Parameters.................................................................. 10-52
10.4.3.7.1 Precharge-to-Activate Interval......................................................................... 10-52
10.4.3.7.2 Activate-to-Read/Write Interval ...................................................................... 10-53
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10.4.3.7.3 Column Address to First Data Out—CAS Latency......................................... 10-53
10.4.3.7.4 Last Data In to Precharge—Write Recovery...................................................10-54
10.4.3.7.5 Refresh Recovery Interval (RFRC) ................................................................. 10-54
10.4.3.7.6 External Address and Command Buffers (BUFCMD).................................... 10-55
10.4.3.8 SDRAM Interface Timing ................................................................................... 10-55
10.4.3.9 SDRAM Read/Write Transactions....................................................................... 10-57
10.4.3.10 SDRAM MODE-SET Command Timing............................................................ 10-58
10.4.3.11 SDRAM Refresh.................................................................................................. 10-58
10.4.3.11.1 SDRAM Refresh Timing................................................................................. 10-58
10.4.4 User-Programmable Machines (UPMs)................................................................... 10-59
10.4.4.1 UPM Requests ..................................................................................................... 10-60
10.4.4.1.1 Memory Access Requests................................................................................ 10-61
10.4.4.1.2 UPM Refresh Timer Requests......................................................................... 10-61
10.4.4.1.3 Software Requests—RUN Command ............................................................. 10-62
10.4.4.1.4 Exception Requests.......................................................................................... 10-62
10.4.4.2 Programming the UPMs ...................................................................................... 10-62
10.4.4.2.1 UPM Programming Example (Two Sequential Writes to the
RAM Array) ................................................................................................ 10-63
10.4.4.2.2 UPM Programming Example (Two Sequential Reads from the
RAM Array) ................................................................................................ 10-64
10.4.4.3 UPM Signal Timing............................................................................................. 10-64
10.4.4.4 UPM RAM Array ................................................................................................ 10-65
10.4.4.4.1 UPM RAM Words........................................................................................... 10-66
10.4.4.4.2 Chip-Select Signal Timing (CSTn) ................................................................. 10-69
10.4.4.4.3 Byte Select Signal Timing (BSTn).................................................................. 10-69
10.4.4.4.4 General-Purpose Signals (GnTn, GOn)........................................................... 10-70
10.4.4.4.5 Loop Control (LOOP) .....................................................................................10-70
10.4.4.4.6 Repeat Execution of Current RAM Word (REDO).........................................10-71
10.4.4.4.7 Address Multiplexing (AMX) .........................................................................10-71
10.4.4.4.8 Data Valid and Data Sample Control (UTA) ................................................... 10-72
10.4.4.4.9 LGPL[0:5] Signal Negation (LAST)............................................................... 10-73
10.4.4.4.10 Wait Mechanism (WAEN)............................................................................... 10-73
10.4.4.5 Synchronous Sampling of LUPWAIT for Early Transfer Acknowledge ............ 10-74
10.4.4.6 Extended Hold Time on Read Accesses.............................................................. 10-74
10.4.4.7 Memory System Interface Example Using UPM................................................10-74
10.5 Initialization/Application Information.........................................................................10-80
10.5.1 Interfacing to Peripherals in Multiplexed Address/Data Mode...............................10-80
10.5.1.1 Multiplexed Address/Data Bus and Unmultiplexed Address Signals.................10-80
10.5.1.2 Peripheral Hierarchy on the Local Bus................................................................ 10-81
10.5.1.3 Peripheral Hierarchy on the Local Bus for Very High Bus Speeds..................... 10-81
10.5.1.4 GPCM Timings.................................................................................................... 10-82
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10.5.2 Bus Turnaround ....................................................................................................... 10-83
10.5.2.1 Address Phase after Previous Read ..................................................................... 10-83
10.5.2.2 Read Data Phase after Address Phase ................................................................. 10-83
10.5.2.3 Read-Modify-Write Cycle for Parity Protected Memory Banks.........................10-84
10.5.2.4 UPM Cycles with Additional Address Phases.....................................................10-84
10.5.3 Interface to Different Port-Size Devices.................................................................. 10-84
10.5.4 Interfacing to SDRAM............................................................................................. 10-86
10.5.4.1 Basic SDRAM Capabilities of the Local Bus...................................................... 10-86
10.5.4.2 Maximum Amount of SDRAM Supported..........................................................10-87
10.5.4.3 SDRAM Machine Limitations.............................................................................10-88
10.5.4.3.1 Analysis of Maximum Row Number Due to Bank Select
Multiplexing................................................................................................10-88
10.5.4.3.2 Bank Select Signals ......................................................................................... 10-88
10.5.4.3.3 128-Mbyte SDRAM........................................................................................ 10-89
10.5.4.3.4 256-Mbyte SDRAM........................................................................................ 10-91
10.5.4.3.5 512-Mbyte SDRAM........................................................................................ 10-91
10.5.4.4 Parity Support for SDRAM ................................................................................. 10-93
10.5.5 Interfacing to ZBT SRAM....................................................................................... 10-94
10.5.6 Interfacing to DSP Host Ports.................................................................................. 10-95
10.5.6.1 Interfacing to MSC8122 DSI............................................................................... 10-95
10.5.6.2 DSI in Asynchronous SRAM-Like Mode ...........................................................10-96
10.5.6.3 DSI in Synchronous Mode...................................................................................10-98
10.5.6.3.1 Synchronous Single Write.............................................................................10-101
10.5.6.3.2 Synchronous Single Read.............................................................................. 10-102
10.5.6.3.3 Synchronous Burst Write............................................................................... 10-103
10.5.6.3.4 Synchronous Burst Read ............................................................................... 10-104
10.5.6.4 Broadcast Accesses............................................................................................ 10-104
Chapter 11
Sequencer
11.1 Overview........................................................................................................................ 11-1
11.1.1 Features...................................................................................................................... 11-2
11.2 External Signal Description........................................................................................... 11-2
11.3 Memory Map/Register Definition ................................................................................. 11-2
11.4 Register Descriptions..................................................................................................... 11-3
11.4.1 PCI Outbound Translation Address Registers (POTARn)......................................... 11-3
11.4.2 PCI Outbound Base Address Registers (POBARn) .................................................. 11-3
11.4.3 PCI Outbound Comparison Mask Registers (POCMRn).......................................... 11-4
11.4.4 Power Management Control Register (PMCR).........................................................11-5
11.4.5 Discard Timer Control Register (DTCR) .................................................................. 11-6
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11.5 Functional Description................................................................................................... 11-6
11.5.1 Transaction Forwarding............................................................................................. 11-6
11.5.1.1 Transactions from the Coherency System Bus (CSB) Port................................... 11-7
11.5.1.2 Transactions from the PCI Ports............................................................................ 11-7
11.5.1.3 Transactions from the DMA Port .......................................................................... 11-7
11.5.2 PCI Outbound Address Translation........................................................................... 11-7
11.5.3 Transaction Ordering ................................................................................................. 11-8
Chapter 12
DMA/Messaging Unit
12.1 Features..........................................................................................................................12-2
12.2 External Signal Description........................................................................................... 12-2
12.2.1 Detailed Signal Descriptions ..................................................................................... 12-2
12.3 Memory Map/Register Definition ................................................................................. 12-3
12.4 Register Descriptions..................................................................................................... 12-4
12.4.1 Outbound Message Interrupt Status Register (OMISR)............................................ 12-4
12.4.2 Outbound Message Interrupt Mask Register (OMIMR)............................................ 12-6
12.4.3 Inbound Message Registers....................................................................................... 12-7
12.4.4 Outbound Message Registers (OMR0–OMR1).........................................................12-7
12.4.5 Doorbell Registers ..................................................................................................... 12-8
12.4.5.1 Outbound Doorbell Register (ODR)...................................................................... 12-8
12.4.5.2 Inbound Doorbell Register (IDR).......................................................................... 12-9
12.4.6 Inbound Message Interrupt Status Register (IMISR) ................................................ 12-9
12.4.7 Inbound Message Interrupt Mask Register (IMIMR).............................................. 12-11
12.4.8 DMA Registers ........................................................................................................ 12-11
12.4.8.1 DMA Mode Register (DMAMRn)...................................................................... 12-12
12.4.8.2 DMA Status Register (DMASRn)....................................................................... 12-14
12.4.8.3 DMA Current Descriptor Address Register (DMACDARn) .............................. 12-15
12.4.8.4 DMA Source Address Register (DMASARn).....................................................12-16
12.4.8.5 DMA Destination Address Register (DMADARn)............................................. 12-16
12.4.8.6 DMA Byte Count Register (DMABCRn) ........................................................... 12-17
12.4.8.7 DMA Next Descriptor Address Register (DMANDARn)...................................12-17
12.4.8.8 DMA General Status Register (DMAGSR).........................................................12-18
12.5 Functional Description................................................................................................. 12-18
12.5.1 Message Unit ........................................................................................................... 12-18
12.5.1.1 Messaging Registers (IMR0–IMR1) ................................................................... 12-19
12.5.1.2 Doorbell Registers (IDR and ODR) .................................................................... 12-19
12.5.2 DMA Controller....................................................................................................... 12-19
12.5.3 DMA Operation....................................................................................................... 12-20
12.5.3.1 External Control................................................................................................... 12-21
/