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MPC8306

NXP MPC8306 Reference guide

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MPC8306 PowerQUICC II Pro
Integrated Communications
Processor Family Reference Manual
Supports
MPC8306
MPC8306S
MPC8306RM
Rev. 2
10/2014
Freescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire,
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© 2011 and 2014 Freescale Semiconductor, Inc.
Information in this document is provided solely to enable system and software
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Document Number: MPC8306RM
Rev. 2
10/2014
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Reference Manual, Rev. 2
Freescale Semiconductor iii
Contents
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Contents
About This Book
Audience.......................................................................................................................... xlv
Organization..................................................................................................................... xlv
Suggested Reading......................................................................................................... xlvii
Conventions ..................................................................................................................xlviii
Signal Conventions.......................................................................................................xlviii
Acronyms and Abbreviations ......................................................................................... xlix
Chapter 1
Overview
1.1 Introduction..................................................................................................................... 1-1
1.1.1 MPC8306 PowerQUICC II Pro Processor Overview.................................................. 1-1
1.1.2 MPC8306S PowerQUICC II Pro Processor Overview................................................ 1-2
1.2 Features............................................................................................................................ 1-3
1.3 MPC8306/MPC8306S Architecture Overview ............................................................... 1-8
1.3.1 Power Architecture Core ............................................................................................. 1-8
1.3.2 QUICC Engine Block................................................................................................ 1-11
1.3.3 DDR2 Memory Controller......................................................................................... 1-15
1.3.4 Enhanced Local Bus Controller (eLBC).................................................................. 1-15
1.3.5 Integrated Programmable Interrupt Controller (IPIC)............................................... 1-17
1.3.6 Enhanced Secure Digital Host Controller (eSDHC).................................................. 1-17
1.3.7 Universal Serial Bus (USB) 2.0................................................................................. 1-18
1.3.8 FlexCAN Module ...................................................................................................... 1-19
1.3.9 Dual I
2
C Interfaces ....................................................................................................1-20
1.3.10 DMA Engine 1........................................................................................................... 1-21
1.3.11 Dual Universal Asynchronous Receiver/Transmitter (DUART)............................... 1-21
1.3.12 Serial Peripheral Interface (SPI)................................................................................ 1-22
1.3.13 System Timers ...........................................................................................................1-22
1.3.14 Real Time Clock........................................................................................................ 1-22
Chapter 2
Memory Map
2.1 Internal Memory-Mapped Registers................................................................................ 2-1
2.2 Accessing IMMR Memory from the Local Processor..................................................... 2-1
2.3 IMMR Address Map........................................................................................................ 2-1
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Chapter 3
Signal Descriptions
3.1 Signals Overview.............................................................................................................3-1
3.1.1 MPC8306 Signals........................................................................................................ 3-2
3.1.2 MPC8306S Signals.................................................................................................... 3-19
3.2 Output Signal States During Reset ................................................................................ 3-34
Chapter 4
Reset, Clocking, and Initialization
4.1 External Signals............................................................................................................... 4-1
4.1.1 Reset Signals................................................................................................................ 4-1
4.1.2 Clock Signals............................................................................................................... 4-2
4.2 Functional Description..................................................................................................... 4-3
4.2.1 Reset Operations.......................................................................................................... 4-3
4.2.2 Power-On Reset Flow.................................................................................................. 4-5
4.2.3 Hard Reset Flow .......................................................................................................... 4-7
4.3 Reset Configuration......................................................................................................... 4-8
4.3.1 Reset Configuration Signals ........................................................................................ 4-8
4.3.2 Reset Configuration Words........................................................................................ 4-10
4.3.3 Loading the Reset Configuration Words ................................................................... 4-17
4.4 Clocking ........................................................................................................................ 4-23
4.4.1 System Clock Domains.............................................................................................. 4-24
4.5 Memory Map/Register Definitions................................................................................ 4-26
4.5.1 Reset Configuration Register Descriptions................................................................ 4-26
4.5.2 Clock Configuration Registers................................................................................... 4-30
Chapter 5
System boot
5.1 Booting from On Chip ROM........................................................................................... 5-1
5.2 eSDHC Boot .................................................................................................................... 5-1
5.2.1 Overview...................................................................................................................... 5-2
5.2.2 Features........................................................................................................................ 5-2
5.2.3 SD/MMC Card Data Structure .................................................................................... 5-3
5.2.4 eSDHC Controller Initial Configuration...................................................................... 5-7
5.2.5 eSDHC Controller Boot Sequence .............................................................................. 5-8
5.2.6 eSDHC Boot Error Handling....................................................................................... 5-8
5.3 SPI Boot ROM............................................................................................................... 5-10
5.3.1 Overview.................................................................................................................... 5-10
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5.3.2 Features...................................................................................................................... 5-11
5.3.3 EEPROM Data Structure........................................................................................... 5-11
5.3.4 SPI Controller Configuration..................................................................................... 5-14
Chapter 6
System Configuration
6.1 Introduction..................................................................................................................... 6-1
6.2 Local Memory Map Overview and Example .................................................................. 6-1
6.2.1 Address Translation and Mapping............................................................................... 6-3
6.2.2 Window into Configuration Space............................................................................... 6-3
6.2.3 Local Access Windows................................................................................................ 6-4
6.2.4 Local Access Register Descriptions ............................................................................ 6-5
6.2.5 Precedence of Local Access Windows ...................................................................... 6-11
6.2.6 Configuring Local Access Windows ......................................................................... 6-11
6.2.7 Distinguishing Local Access Windows from Other Mapping Functions.................. 6-11
6.2.8 Internal Memory Map................................................................................................ 6-12
6.3 System Configuration .................................................................................................... 6-12
6.3.1 System Configuration Register Memory Map........................................................... 6-12
6.3.2 System Configuration Registers ................................................................................ 6-13
6.3.3 Multisite Muxing ....................................................................................................... 6-39
6.4 Software Watchdog Timer (WDT).................................................................................6-39
6.4.1 WDT Overview.......................................................................................................... 6-40
6.4.2 WDT Features............................................................................................................ 6-40
6.4.3 WDT Modes of Operation......................................................................................... 6-40
6.4.4 WDT Memory Map/Register Definition ................................................................... 6-41
6.4.5 Functional Description............................................................................................... 6-44
6.4.6 Initialization/Application Information (WDT Programming Guidelines)................. 6-46
6.5 Real Time Clock Module (RTC).................................................................................... 6-47
6.5.1 Overview.................................................................................................................... 6-47
6.5.2 Features...................................................................................................................... 6-47
6.5.3 Modes of Operation................................................................................................... 6-48
6.5.4 External Signal Description....................................................................................... 6-48
6.5.5 RTC Memory Map/Register Definition..................................................................... 6-48
6.5.6 Functional Description............................................................................................... 6-52
6.5.7 RTC Initialization Sequence...................................................................................... 6-53
6.6 Periodic Interval Timer (PIT) ........................................................................................ 6-54
6.6.1 PIT Overview............................................................................................................. 6-54
6.6.2 PIT Features...............................................................................................................6-54
6.6.3 PIT Modes of Operation............................................................................................ 6-54
6.6.4 PIT External Signal Description................................................................................ 6-55
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6.6.5 PIT Memory Map/Register Definition ...................................................................... 6-55
6.6.6 Functional Description............................................................................................... 6-58
6.6.7 PIT Programming Guidelines.................................................................................... 6-59
6.7 General-Purpose Timers (GTMs) .................................................................................. 6-60
6.7.1 GTM Overview.......................................................................................................... 6-60
6.7.2 GTM Features............................................................................................................ 6-60
6.7.3 GTM Modes of Operation ......................................................................................... 6-61
6.7.4 GTM External Signal Description............................................................................. 6-62
6.7.5 GTM Memory Map/Register Definition....................................................................6-64
6.7.6 Functional Description............................................................................................... 6-73
6.7.7 Initialization/Application Information (Programming Guidelines for GTM Registers) ...
6-76
6.8 Power Management Control (PMC).............................................................................. 6-76
6.8.1 External Signal Description....................................................................................... 6-77
6.8.2 PMC Memory Map/Register Definition.................................................................... 6-77
6.8.3 Functional Description............................................................................................... 6-78
Chapter 7
Arbiter and Bus Monitor
7.1 Overview.......................................................................................................................... 7-1
7.1.1 Coherent System Bus Overview.................................................................................. 7-1
7.2 Arbiter Memory Map/Register Definition....................................................................... 7-2
7.2.1 Arbiter Configuration Register (ACR)........................................................................ 7-3
7.2.2 Arbiter Timers Register (ATR).................................................................................... 7-4
7.2.3 Arbiter Event Register (AER)...................................................................................... 7-5
7.2.4 Arbiter Interrupt Definition Register (AIDR).............................................................. 7-6
7.2.5 Arbiter Mask Register (AMR)..................................................................................... 7-7
7.2.6 Arbiter Event Attributes Register (AEATR)................................................................ 7-8
7.2.7 Arbiter Event Address Register (AEADR).................................................................. 7-9
7.2.8 Arbiter Event Response Register (AERR)................................................................. 7-10
7.3 Functional Description................................................................................................... 7-11
7.3.1 Arbitration Policy ...................................................................................................... 7-11
7.3.2 Bus Error Detection................................................................................................... 7-14
7.4 Initialization/Applications Information ......................................................................... 7-17
7.4.1 Initialization Sequence............................................................................................... 7-17
7.4.2 Error Handling Sequence........................................................................................... 7-17
Chapter 8
e300 Processor Core Overview
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8.1 Overview.......................................................................................................................... 8-1
8.1.1 Features........................................................................................................................ 8-3
8.1.2 Instruction Unit............................................................................................................ 8-6
8.1.3 Independent Execution Units....................................................................................... 8-7
8.1.4 Completion Unit .......................................................................................................... 8-8
8.1.5 Memory Subsystem Support........................................................................................ 8-9
8.1.6 Bus Interface Unit (BIU) ........................................................................................... 8-10
8.1.7 System Support Functions......................................................................................... 8-11
8.2 e300 Processor and System Version Numbers............................................................... 8-13
8.3 Power Architecture Implementation.............................................................................. 8-13
8.4 Implementation-Specific Information............................................................................ 8-14
8.4.1 Register Model........................................................................................................... 8-14
8.4.2 Instruction Set and Addressing Modes...................................................................... 8-26
8.4.3 Cache Implementation............................................................................................... 8-29
8.4.4 Interrupt Model.......................................................................................................... 8-31
8.4.5 Memory Management................................................................................................ 8-35
8.4.6 Instruction Timing .....................................................................................................8-36
8.4.7 Core Interface ............................................................................................................ 8-37
8.4.8 Debug Features ......................................................................................................... 8-39
8.5 Differences Between Cores........................................................................................... 8-40
Chapter 9
Integrated Programmable Interrupt Controller (IPIC)
9.1 Introduction...................................................................................................................... 9-1
9.2 Features............................................................................................................................ 9-5
9.3 Modes of Operation ......................................................................................................... 9-5
9.3.1 Core Enable Mode....................................................................................................... 9-5
9.3.2 Core Disable Mode...................................................................................................... 9-5
9.4 External Signal Description............................................................................................. 9-6
9.4.1 Overview...................................................................................................................... 9-6
9.4.2 Detailed Signal Descriptions ....................................................................................... 9-6
9.5 Memory Map/Register Definition ................................................................................... 9-6
9.5.1 System Global Interrupt Configuration Register (SICFR).......................................... 9-8
9.5.2 System Global Interrupt Vector Register (SIVCR)...................................................... 9-9
9.5.3 System Internal Interrupt Pending Registers (SIPNR_H and SIPNR_L).................. 9-12
9.5.4 System Internal Interrupt Group A Priority Register (SIPRR_A)............................. 9-15
9.5.5 System Internal Interrupt Group B Priority Register (SIPRR_B) ............................. 9-15
9.5.6 System Internal Interrupt Group C Priority Register (SIPRR_C) ............................. 9-16
9.5.7 System Internal Interrupt Group D Priority Register (SIPRR_D)............................. 9-17
9.5.8 System Internal Interrupt Mask Register (SIMSR_H and SIMSR_L)...................... 9-18
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9.5.9 System Internal Interrupt Control Register (SICNR)................................................ 9-19
9.5.10 System External Interrupt Pending Register (SEPNR).............................................. 9-21
9.5.11 System Mixed Interrupt Group A Priority Register (SMPRR_A)............................. 9-22
9.5.12 System Mixed Interrupt Group B Priority Register (SMPRR_B)............................. 9-23
9.5.13 System External Interrupt Mask Register (SEMSR)................................................. 9-23
9.5.14 System External Interrupt Control Register (SECNR).............................................. 9-24
9.5.15 System Error Status Register (SERSR) ..................................................................... 9-26
9.5.16 System Error Mask Register (SERMR)..................................................................... 9-27
9.5.17 System Error Control Register (SERCR) .................................................................. 9-28
9.5.18 System External interrupt Polarity Control Register (SEPCR)................................. 9-28
9.5.19 System Internal Interrupt Force Registers (SIFCR_H and SIFCR_L)...................... 9-29
9.5.20 System External Interrupt Force Register (SEFCR).................................................. 9-31
9.5.21 System Error Force Register (SERFR)...................................................................... 9-31
9.5.22 System Critical Interrupt Vector Register (SCVCR)................................................. 9-32
9.5.23 System Management Interrupt Vector Register (SMVCR)....................................... 9-32
9.5.24 QUICC Engine Ports Interrupt Event Register (CEPIER) ........................................ 9-33
9.5.25 QUICC Engine Ports Interrupt Mask Register (CEPIMR)........................................ 9-34
9.5.26 QUICC Engine Ports Interrupt Control Register (CEPICR)..................................... 9-36
9.6 Functional Description................................................................................................... 9-36
9.6.1 Interrupt Types........................................................................................................... 9-36
9.6.2 Interrupt Configuration.............................................................................................. 9-37
9.6.3 Internal Interrupts Group Relative Priority................................................................ 9-39
9.6.4 Mixed Interrupts Group Relative Priority.................................................................. 9-39
9.6.5 Highest Priority Interrupt........................................................................................... 9-40
9.6.6 Interrupt Source Priorities.......................................................................................... 9-40
9.6.7 Masking Interrupt Sources......................................................................................... 9-44
9.6.8 Interrupt Vector Generation and Calculation............................................................. 9-44
9.6.9 Machine Check Interrupts.......................................................................................... 9-45
Chapter 10
DDR Memory Controller
10.1 Introduction.................................................................................................................... 10-1
10.2 Features.......................................................................................................................... 10-2
10.2.1 Modes of Operation................................................................................................... 10-3
10.3 External Signal Descriptions ......................................................................................... 10-3
10.3.1 Signals Overview....................................................................................................... 10-3
10.3.2 Detailed Signal Descriptions ..................................................................................... 10-5
10.4 Memory Map/Register Definition ................................................................................. 10-8
10.4.1 Register Descriptions................................................................................................. 10-9
10.5 Functional Description................................................................................................. 10-28
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10.5.1 DDR SDRAM Interface Operation.......................................................................... 10-31
10.5.2 DDR SDRAM Address Multiplexing...................................................................... 10-33
10.5.3 JEDEC Standard DDR SDRAM Interface Commands........................................... 10-34
10.5.4 DDR SDRAM Interface Timing.............................................................................. 10-36
10.5.5 DDR SDRAM Mode-Set Command Timing........................................................... 10-39
10.5.6 DDR SDRAM Write Timing Adjustments.............................................................. 10-40
10.5.7 DDR SDRAM Refresh ............................................................................................ 10-41
10.5.8 DDR Data Beat Ordering......................................................................................... 10-44
10.5.9 Page Mode and Logical Bank Retention ................................................................. 10-45
10.6 Initialization/Application Information......................................................................... 10-46
10.6.1 DDR SDRAM Initialization Sequence.................................................................... 10-47
Chapter 11
Enhanced Local Bus Controller
11.1 Introduction.................................................................................................................... 11-1
11.1.1 Overview.................................................................................................................... 11-2
11.1.2 Features...................................................................................................................... 11-2
11.1.3 Modes of Operation................................................................................................... 11-3
11.2 External Signal Descriptions ......................................................................................... 11-4
11.3 Memory Map/Register Definition ................................................................................. 11-8
11.3.1 Register Descriptions................................................................................................. 11-9
11.4 Functional Description................................................................................................. 11-38
11.4.1 Basic Architecture.................................................................................................... 11-40
11.4.2 General-Purpose Chip-Select Machine (GPCM)..................................................... 11-43
11.4.3 Flash Control Machine (FCM) ................................................................................ 11-55
11.4.4 User-Programmable Machines (UPMs)................................................................... 11-71
11.5 Initialization/Application Information......................................................................... 11-87
11.5.1 Interfacing to Peripherals in Different Address Modes........................................... 11-87
11.5.2 Bus Turnaround ....................................................................................................... 11-89
11.5.3 Interface to Different Port-Size Devices.................................................................. 11-90
11.5.4 Command Sequence Examples for NAND Flash EEPROM................................... 11-91
11.5.5 Interfacing to Fast-Page Mode DRAM Using UPM ............................................... 11-95
11.5.6 Interfacing to ZBT SRAM Using UPM................................................................. 11-100
Chapter 12
Enhanced Secure Digital Host Controller
12.1 Overview........................................................................................................................ 12-1
12.2 Features.......................................................................................................................... 12-3
12.2.1 Data Transfer Modes.................................................................................................. 12-4
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12.3 External Signal Description........................................................................................... 12-4
12.4 Memory Map/Register Definition ................................................................................. 12-5
12.4.1 DMA System Address Register (DSADDR)............................................................. 12-7
12.4.2 Block Attributes Register (BLKATTR)..................................................................... 12-7
12.4.3 Command Argument Register (CMDARG).............................................................. 12-8
12.4.4 Transfer Type Register (XFERTYP).......................................................................... 12-9
12.4.5 Command Response 0–3 (CMDRSP0–3)................................................................ 12-12
12.4.6 Buffer Data Port Register (DATPORT)................................................................... 12-14
12.4.7 Present State Register (PRSSTAT) ..........................................................................12-15
12.4.8 Protocol Control Register (PROCTL) ..................................................................... 12-19
12.4.9 System Control Register (SYSCTL)........................................................................ 12-22
12.4.10 Interrupt Status Register (IRQSTAT)....................................................................... 12-24
12.4.11 Interrupt Status Enable Register (IRQSTATEN)..................................................... 12-29
12.4.12 Interrupt Signal Enable Register (IRQSIGEN) ....................................................... 12-31
12.4.13 Auto CMD12 Error Status Register (AUTOC12ERR)............................................ 12-33
12.4.14 Host Controller Capabilities (HOSTCAPBLT)....................................................... 12-35
12.4.15 Watermark Level Register (WML).......................................................................... 12-36
12.4.16 Force Event Register (FEVT).................................................................................. 12-37
12.4.17 Host Controller Version Register (HOSTVER)....................................................... 12-39
12.4.18 DMA Control Register (DCR)................................................................................. 12-39
12.5 Functional Description................................................................................................. 12-39
12.5.1 Data Buffer .............................................................................................................. 12-39
12.5.2 DMA CSB Interface ................................................................................................ 12-42
12.5.3 SD Protocol Unit...................................................................................................... 12-43
12.5.4 Clock & Reset Manager........................................................................................... 12-45
12.5.5 Clock Generator....................................................................................................... 12-45
12.5.6 SDIO Card Interrupt ................................................................................................ 12-45
12.5.7 Card Insertion and Removal Detection.................................................................... 12-47
12.5.8 Power Management ................................................................................................. 12-47
12.6 Initialization/Application Information......................................................................... 12-48
12.6.1 Command Send and Response Receive Basic Operation........................................ 12-48
12.6.2 Card Identification Mode......................................................................................... 12-49
12.6.3 Card Access ............................................................................................................. 12-53
12.6.4 Switch Function....................................................................................................... 12-58
12.6.5 Commands for MMC/SD/SDIO.............................................................................. 12-61
12.7 Software Restrictions................................................................................................... 12-66
12.7.1 Initialization Active ................................................................................................. 12-66
12.7.2 Software Polling Procedure..................................................................................... 12-66
12.7.3 Suspend Operation................................................................................................... 12-66
12.7.4 Data Port Access...................................................................................................... 12-66
12.7.5 Multi-block Read..................................................................................................... 12-67
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Chapter 13
DMA Engine 1
13.1 Overview........................................................................................................................ 13-1
13.1.1 Features...................................................................................................................... 13-2
13.2 DMAC Memory Map/Register Definition .................................................................... 13-2
13.2.1 DMA Control Register (DMACR)............................................................................ 13-4
13.3 DMA Error Status (DMAES) ........................................................................................13-5
13.3.1 DMA Enable Request Register (DMAERQ)............................................................. 13-8
13.3.2 DMA Enable Error Interrupt Register (DMAEEI).................................................... 13-9
13.3.3 DMA Set Enable Request (DMASERQ)................................................................. 13-10
13.3.4 DMA Clear Enable Request (DMACERQ)............................................................. 13-11
13.3.5 DMA Set Enable Error Interrupt (DMASEEI)........................................................ 13-11
13.3.6 DMA Clear Enable Error Interrupt (DMACEEI).................................................... 13-12
13.3.7 DMA Clear Interrupt Request (DMACINT)........................................................... 13-13
13.3.8 DMA Clear Error (DMACERR).............................................................................. 13-13
13.3.9 DMA Set START Bit (DMASSRT)......................................................................... 13-14
13.3.10 DMA Clear DONE Status (DMACDNE)................................................................ 13-15
13.3.11 DMA Interrupt Request Register (DMAINT)......................................................... 13-15
13.3.12 DMA Error Register (DMAERR)............................................................................ 13-16
13.3.13 DMA General Purpose Output Register (DMAGPOR) .......................................... 13-17
13.3.14 DMA Channel n Priority (DCHPRIn), n = 0–15..................................................... 13-18
13.3.15 Transfer Control Descriptor (TCD)......................................................................... 13-19
13.4 Functional Description................................................................................................. 13-27
13.4.1 DMA Microarchitecture ..........................................................................................13-27
13.4.2 DMA Basic Data Flow ............................................................................................13-28
13.5 Initialization/Application Information......................................................................... 13-31
13.5.1 DMA Initialization................................................................................................... 13-31
13.5.2 DMA Programming Errors...................................................................................... 13-32
13.6 DMA Transfer.............................................................................................................. 13-32
13.6.1 Single Request ......................................................................................................... 13-32
13.6.2 Multiple Requests.................................................................................................... 13-33
13.7 TCD Status................................................................................................................... 13-35
13.7.1 Minor Loop Complete ............................................................................................. 13-35
13.7.2 Active Channel TCD Reads..................................................................................... 13-35
13.7.3 Preemption status..................................................................................................... 13-35
13.8 Channel Linking .......................................................................................................... 13-36
13.9 Programming during channel execution...................................................................... 13-36
13.9.1 Dynamic priority changing...................................................................................... 13-36
13.9.2 Dynamic channel linking and dynamic scatter/gather............................................. 13-37
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Chapter 14
DMA Engine 2
14.1 DMA Features................................................................................................................14-1
14.2 DMA Memory Map/Register Definition....................................................................... 14-2
14.3 DMA Register Descriptions........................................................................................... 14-3
14.3.1 DMA Registers.......................................................................................................... 14-3
14.4 Functional Description................................................................................................... 14-9
14.4.1 DMA Operation......................................................................................................... 14-9
14.4.2 DMA Segment Descriptors...................................................................................... 14-10
14.5 Initialization/Application Information......................................................................... 14-12
14.5.1 Initialization Steps in Direct Mode.......................................................................... 14-12
14.5.2 Initialization Steps in Chaining Mode..................................................................... 14-13
Chapter 15
FlexCAN
15.1 Introduction.................................................................................................................... 15-1
15.1.1 Overview.................................................................................................................... 15-2
15.1.2 FlexCAN Module Features........................................................................................ 15-3
15.1.3 Modes of Operation................................................................................................... 15-4
15.2 External Signal Description........................................................................................... 15-5
15.2.1 Signals Overview....................................................................................................... 15-5
15.3 Memory Map/Register Definition ................................................................................. 15-5
15.3.1 Message Buffer Structure .......................................................................................... 15-7
15.3.2 Rx FIFO Structure ................................................................................................... 15-10
15.3.3 Register Descriptions............................................................................................... 15-12
15.4 Functional Description................................................................................................. 15-28
15.4.1 Overview.................................................................................................................. 15-28
15.4.2 Transmit Process...................................................................................................... 15-29
15.4.3 Arbitration process................................................................................................... 15-30
15.4.4 Receive Process ....................................................................................................... 15-30
15.4.5 Matching Process..................................................................................................... 15-32
15.4.6 Data Coherence....................................................................................................... 15-33
15.4.7 Rx FIFO................................................................................................................... 15-36
15.4.8 CAN Protocol Related Features............................................................................... 15-36
15.4.9 Modes of Operation Details..................................................................................... 15-40
15.4.10 WInterrupts.............................................................................................................. 15-41
15.4.11 Bus Interface............................................................................................................ 15-42
15.5 Initialization/Application Information......................................................................... 15-42
15.5.1 FlexCAN Initialization Sequence............................................................................ 15-42
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Chapter 16
Universal Serial Bus Interface
16.1 Introduction.................................................................................................................... 16-1
16.1.1 Overview.................................................................................................................... 16-2
16.1.2 Features...................................................................................................................... 16-2
16.1.3 Modes of Operation................................................................................................... 16-2
16.2 External Signals............................................................................................................. 16-3
16.2.1 ULPI Interface ........................................................................................................... 16-3
16.3 Memory Map/Register Definitions................................................................................ 16-4
16.3.1 Capability Registers................................................................................................... 16-6
16.3.2 Operational Registers............................................................................................... 16-10
16.4 Functional Description................................................................................................. 16-44
16.4.1 System Interface ...................................................................................................... 16-44
16.4.2 DMA Engine............................................................................................................ 16-44
16.4.3 FIFO RAM Controller............................................................................................. 16-45
16.4.4 PHY Interface.......................................................................................................... 16-45
16.5 Host Data Structures.................................................................................................... 16-45
16.5.1 Periodic Frame List.................................................................................................. 16-46
16.5.2 Asynchronous List Queue Head Pointer.................................................................. 16-47
16.5.3 Isochronous (High-Speed) Transfer Descriptor (iTD)............................................. 16-47
16.5.4 Split Transaction Isochronous Transfer Descriptor (siTD)...................................... 16-51
16.5.5 Queue Element Transfer Descriptor (qTD) ............................................................. 16-55
16.5.6 Queue Head.............................................................................................................. 16-60
16.5.7 Periodic Frame Span Traversal Node (FSTN)......................................................... 16-64
16.6 Host Operations ........................................................................................................... 16-65
16.6.1 Host Controller Initialization................................................................................... 16-66
16.6.2 Power Port................................................................................................................ 16-67
16.6.3 Reporting Over-Current........................................................................................... 16-67
16.6.4 Suspend/Resume...................................................................................................... 16-67
16.6.5 Schedule Traversal Rules......................................................................................... 16-69
16.6.6 Periodic Schedule Frame Boundaries vs. Bus Frame Boundaries........................... 16-71
16.6.7 Periodic Schedule .................................................................................................... 16-73
16.6.8 Managing Isochronous Transfers Using iTDs......................................................... 16-74
16.6.9 Asynchronous Schedule........................................................................................... 16-79
16.6.10 Managing Control/Bulk/Interrupt Transfers via Queue Heads................................ 16-83
16.6.11 Ping Control............................................................................................................. 16-87
16.6.12 Split Transactions..................................................................................................... 16-88
16.6.13 Port Test Modes..................................................................................................... 16-116
16.6.14 Interrupts................................................................................................................ 16-117
16.7 Device Data Structures .............................................................................................. 16-121
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16.7.1 Endpoint Queue Head............................................................................................ 16-122
16.7.2 Endpoint Transfer Descriptor (dTD) ..................................................................... 16-124
16.8 Device Operational Model......................................................................................... 16-127
16.8.1 Device Controller Initialization............................................................................. 16-127
16.8.2 Port State and Control............................................................................................ 16-128
16.8.3 Managing Endpoints.............................................................................................. 16-131
16.8.4 Managing Queue Heads......................................................................................... 16-141
16.8.5 Managing Transfers with Transfer Descriptors ..................................................... 16-143
16.8.6 Servicing Interrupts................................................................................................ 16-146
16.9 Deviations from the EHCI Specifications ................................................................. 16-147
16.9.1 Embedded Transaction Translator Function.......................................................... 16-148
16.9.2 Device Operation................................................................................................... 16-151
16.9.3 Non-Zero Fields the Register File ......................................................................... 16-152
16.9.4 SOF Interrupt......................................................................................................... 16-152
16.9.5 Embedded Design.................................................................................................. 16-152
16.9.6 Miscellaneous Variations from EHCI.................................................................... 16-152
Chapter 17
I
2
C Interfaces
17.1 Introduction.................................................................................................................... 17-1
17.1.1 Features...................................................................................................................... 17-2
17.1.2 Modes of Operation................................................................................................... 17-2
17.2 External Signal Descriptions ......................................................................................... 17-3
17.2.1 Signal Overview ........................................................................................................ 17-3
17.2.2 Detailed Signal Descriptions ..................................................................................... 17-3
17.3 Memory Map/Register Definition ................................................................................. 17-4
17.3.1 Register Descriptions................................................................................................. 17-5
17.4 Functional Description................................................................................................. 17-10
17.4.1 Transaction Protocol................................................................................................ 17-10
17.4.2 Arbitration Procedure .............................................................................................. 17-14
17.4.3 Handshaking ............................................................................................................ 17-15
17.4.4 Clock Control........................................................................................................... 17-15
17.4.5 Boot Sequencer Mode.............................................................................................. 17-16
17.5 Initialization/Application Information......................................................................... 17-20
17.5.1 Interrupt Service Routine Flowchart........................................................................ 17-20
17.5.2 Initialization Sequence............................................................................................. 17-22
17.5.3 Generation of START .............................................................................................. 17-22
17.5.4 Post-Transfer Software Response............................................................................ 17-22
17.5.5 Generation of STOP................................................................................................. 17-23
17.5.6 Generation of Repeated START .............................................................................. 17-23
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17.5.7 Generation of SCLn When SDAn is Negated ......................................................... 17-23
17.5.8 Slave Mode Interrupt Service Routine..................................................................... 17-23
Chapter 18
DUART
18.1 Overview........................................................................................................................ 18-1
18.1.1 Features...................................................................................................................... 18-2
18.1.2 Modes of Operation................................................................................................... 18-3
18.2 External Signal Descriptions ......................................................................................... 18-3
18.2.1 Signal Overview ........................................................................................................ 18-3
18.2.2 Detailed Signal Descriptions ..................................................................................... 18-3
18.3 Memory Map/Register Definition ................................................................................. 18-4
18.3.1 Register Descriptions................................................................................................. 18-6
18.4 Functional Description................................................................................................. 18-18
18.4.1 Serial Interface......................................................................................................... 18-19
18.4.2 Baud-Rate Generator Logic..................................................................................... 18-20
18.4.3 Local Loopback Mode............................................................................................. 18-21
18.4.4 Errors ....................................................................................................................... 18-21
18.4.5 FIFO Mode .............................................................................................................. 18-21
18.5 DUART Initialization/Application Information .......................................................... 18-23
Chapter 19
Serial Peripheral Interface
19.1 Overview........................................................................................................................ 19-1
19.2 Introduction.................................................................................................................... 19-2
19.2.1 Features...................................................................................................................... 19-2
19.2.2 SPI Transmission and Reception Process.................................................................. 19-3
19.2.3 Modes of Operation................................................................................................... 19-3
19.3 External Signal Descriptions ......................................................................................... 19-6
19.3.1 Overview.................................................................................................................... 19-7
19.3.2 Detailed Signal Descriptions ..................................................................................... 19-7
19.4 Memory Map/Register Definition ................................................................................. 19-8
19.4.1 Register Descriptions................................................................................................. 19-9
19.5 Initialization/Application Information......................................................................... 19-16
19.5.1 SPI Master Programming Example ......................................................................... 19-16
19.5.2 SPI Slave Programming Example............................................................................ 19-16
Chapter 20
JTAG/Testing Support
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20.1 Overview........................................................................................................................ 20-1
20.2 JTAG Signals ................................................................................................................. 20-1
20.2.1 External Signal Descriptions ..................................................................................... 20-2
20.3 JTAG Registers and Scan Chains ..................................................................................20-3
Chapter 21
General Purpose I/O (GPIO)
21.1 Introduction.................................................................................................................... 21-1
21.1.1 Overview.................................................................................................................... 21-1
21.1.2 Features...................................................................................................................... 21-2
21.2 External Signal Description........................................................................................... 21-2
21.2.1 Signals Overview....................................................................................................... 21-2
21.3 Memory Map/Register Definition ................................................................................. 21-2
21.3.1 GPIOn Direction Register (GP1DIR–GP2DIR)........................................................ 21-3
21.3.2 GPIOn Open Drain Register (GP1ODR–GP2ODR)................................................. 21-4
21.3.3 GPIOn Data Register (GP1DAT–GP2DAT).............................................................. 21-4
21.3.4 GPIOn Interrupt Event Register (GP1IER–GP2IER)................................................ 21-5
21.3.5 GPIOn Interrupt Mask Register (GP1IMR–GP2IMR).............................................. 21-5
21.3.6 GPIOn Interrupt Control Register (GP1ICR–GP2ICR) ............................................ 21-6
Chapter 22
QUICC Engine Block on the MPC8306 and MPC8306S
22.1 QUICC Engine Block.................................................................................................... 22-1
22.2 QUICC Engine Implementation Details for the MPC8306 and MPC8306S................. 22-3
22.2.1 System Interface ........................................................................................................ 22-5
22.2.2 Configuration – Parameter RAM............................................................................. 22-37
22.2.3 QUICC Engine Multiplexing and Timers................................................................ 22-42
22.2.4 UCC Ethernet (UEC)............................................................................................... 22-45
22.2.5 IEEE Standard 1588 Assist...................................................................................... 22-45
Appendix A
Complete List of Configuration, Control, and Status Registers
A.1 Local Access Windows................................................................................................... A-1
A.2 System Configuration Registers ..................................................................................... A-2
A.3 Watchdog Timer (WDT)................................................................................................. A-3
A.4 Real Time Clock (RTC).................................................................................................. A-3
A.5 Periodic Interval Timer (PIT) ......................................................................................... A-3
A.6 General Purpose (Global) Timers (GTMs)..................................................................... A-4
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A.7 Integrated Programmable Interrupt Controller (IPIC).................................................... A-5
A.8 QUICC Engine Ports Interrupts...................................................................................... A-6
A.9 System Arbiter................................................................................................................ A-6
A.10 Reset Configuration........................................................................................................ A-7
A.11 Clock Configuration ....................................................................................................... A-7
A.12 Power Management Controller (PMC)........................................................................... A-7
A.13 General Purpose I/O (GPIO)........................................................................................... A-8
A.14 DDR Memory Controller................................................................................................ A-8
A.15 I
2
C Controller ................................................................................................................. A-9
A.16 DUART......................................................................................................................... A-10
A.17 Enhanced Local Bus Controller (eLBC)........................................................................A-11
A.18 Serial Peripheral Interface (SPI)................................................................................... A-13
A.19 DMA Engine 1.............................................................................................................. A-13
A.20 DMA Engine 2.............................................................................................................. A-14
A.21 Enhanced Secure Digital Host Controller (eSDHC)..................................................... A-15
A.22 FlexCAN....................................................................................................................... A-16
A.23 Universal Serial Bus (USB) Interface........................................................................... A-17
Appendix B
Revision History
B.1 Changes From Revision 1 to Revision 2 .........................................................................B-1
B.2 Changes From Revision 0 to Revision 1 .........................................................................B-8
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Figures
1-1 MPC8306 Block Diagram....................................................................................................... 1-2
1-2 MPC8306S Block Diagram .................................................................................................... 1-3
1-3 MPC8306 Integrated e300 Core Block Diagram.................................................................. 1-10
1-4 QUICC Engine Block Architectural Block Diagram............................................................ 1-12
1-5 USB Controllers Port Configuration..................................................................................... 1-19
3-1 MPC8306 Signal Groupings (1 of 2)...................................................................................... 3-3
3-2 MPC8306 Signal Groupings (2 of 2)...................................................................................... 3-4
3-3 MPC8306S Signal Groupings (1 of 2).................................................................................. 3-20
3-4 MPC8306S Signal Groupings (2 of 2).................................................................................. 3-21
4-1 Power-On Reset Flow............................................................................................................. 4-7
4-2 Hard Reset Flow...................................................................................................................... 4-8
4-3 Reset Configuration Word Low Register (RCWLR)............................................................ 4-11
4-4 Reset Configuration Word High Register (RCWHR)........................................................... 4-14
4-5 EEPROM Data Format for Reset Configuration Words Preload Command........................ 4-20
4-6 EEPROM Contents............................................................................................................... 4-21
4-7 MPC8306/8306S Clock Subsystem...................................................................................... 4-24
4-8 Reset Status Register (RSR)..................................................................................................4-27
4-9 Reset Mode Register (RMR)................................................................................................. 4-28
4-10 Reset Protection Register (RPR)........................................................................................... 4-29
4-11 Reset Control Register (RCR)............................................................................................... 4-29
4-12 Reset Control Enable Register (RCER)................................................................................ 4-30
4-13 System PLL Mode Register.................................................................................................. 4-31
4-14 Output Clock Control Register (OCCR)............................................................................... 4-32
4-15 System Clock Control Register (SCCR)............................................................................... 4-33
5-1 SD/MMC Card Data Structure................................................................................................ 5-4
5-2 Config Address Fields............................................................................................................. 5-6
5-3 SD/MMC Card Data Structure for Maximum Redundancy ................................................. 5-10
5-4 SPI EEPROM Data Structure................................................................................................ 5-12
5-5 Config Address Fields........................................................................................................... 5-13
5-6 External Signal Connection ..................................................................................................5-15
6-1 Local Memory Map Example ................................................................................................. 6-2
6-2 Internal Memory Map Registers’ Base Address Register (IMMRBAR)................................ 6-6
6-3 Alternate Configuration Base Address Register (ALTCBAR)............................................... 6-7
6-4 LBC Local Access Window n Base Address Registers (LBLAWBAR0–LBLAWBAR3).... 6-7
6-5 LBC Local Access Window n Attributes Registers (LBLAWAR0–LBLAWAR3) ................ 6-8
6-6 DDR Local Access Window n Base Address Registers (DDRLAWBAR0–DDRLAWBAR1)...
6-9
6-7 DDR Local Access Window n Attributes Registers (DDRLAWAR0–DDRLAWAR1)....... 6-10
6-8 System General Purpose Register Low (SGPRL)................................................................. 6-13
6-9 System General Purpose Register High (SGPRH) ............................................................... 6-14
6-10 System Part and Revision ID Register (SPRIDR) ................................................................ 6-14
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6-11 System Priority Configuration Register (SPCR) .................................................................. 6-16
6-12 System I/O Configuration Register 1 (SICR_1) ................................................................... 6-17
6-13 System I/O Configuration Register 2 (SICR_2) ................................................................... 6-22
6-14 System I/O Configuration Register 3 (SICR_3) ................................................................... 6-26
6-15 DDR Control Driver Register (DDRCDR)........................................................................... 6-27
6-16 DDR Debug Status Register (DDRDSR).............................................................................. 6-28
6-17 eSDHC Control Register (SDHCCR)................................................................................... 6-29
6-18 CAN Access Control Register (CAN_DBG_CTRL)............................................................ 6-31
6-19 SPI Chip Select Register (SPI_CS)....................................................................................... 6-32
6-20 General Purpose Register 1 (GPR_1) ................................................................................... 6-33
6-21 CAN Interrupt Status Register (CAN_INT_STAT) .............................................................. 6-35
6-22 DUART Interrupt Status Register (DUART_INT_STAT).................................................... 6-37
6-23 GPIO Interrupt Status Register (GPIO_INT_STAT) ............................................................ 6-38
6-24 Software Watchdog Timer High-Level Block Diagram ....................................................... 6-40
6-25 System Watchdog Control Register (SWCRR)..................................................................... 6-42
6-26 System Watchdog Count Register (SWCNR)....................................................................... 6-43
6-27 System Watchdog Service Register (SWSRR)..................................................................... 6-43
6-28 Software Watchdog Timer Service State Diagram................................................................ 6-45
6-29 Software Watchdog Timer Functional Block Diagram......................................................... 6-45
6-30 Real Time Clock Module High Level Block Diagram ......................................................... 6-47
6-31 Real Time Counter Control Register (RTCNR).................................................................... 6-49
6-32 Real Time Counter Load Register (RTLDR)........................................................................ 6-49
6-33 Real Time Counter Prescale Register (RTPSR).................................................................... 6-50
6-34 Real Time Counter Register (RTCTR).................................................................................. 6-50
6-35 Real Time Counter Event Register (RTEVR)....................................................................... 6-51
6-36 Real Time Counter Alarm Register (RTALR) ...................................................................... 6-51
6-37 Real Time Clock Module Functional Block Diagram .......................................................... 6-52
6-38 Periodic Interval Timer High Level Block Diagram............................................................. 6-54
6-39 Periodic Interval Timer Control Register (PTCNR)............................................................. 6-56
6-40 Periodic Interval Timer Load Register (PTLDR) ................................................................. 6-56
6-41 Periodic Interval Timer Prescale Register (PTPSR)............................................................. 6-57
6-42 Periodic Interval Timer Counter Register (PTCTR)............................................................. 6-57
6-43 Periodic Interval Timer Event Register (PTEVR) ................................................................ 6-58
6-44 Periodic Interval Timer Functional Block Diagram.............................................................. 6-59
6-45 Global Timers Block Diagram.............................................................................................. 6-60
6-46 Global Timers Configuration Register 1 (GTCFR1) ............................................................ 6-66
6-47 Global Timers Configuration Register 2 (GTCFR2) ............................................................ 6-67
6-48 Global Timers Mode Registers (GTMDR1–GTMDR4)....................................................... 6-69
6-49 Global Timers Reference Registers (GTRFR1–GTRFR4)................................................... 6-70
6-50 Global Timers Capture Registers (GTCPR1–GTCPR4)....................................................... 6-70
6-51 Global Timers Counter Registers (GTCNR1—GTCNR4)................................................... 6-71
/