onsemi RSL10-002GEVB Operating instructions

Brand
onsemi
Model
RSL10-002GEVB
Type
Operating instructions
Semiconductor Components Industries, LLC, 2017
December, 2017 − Rev. 0 1Publication Order Number:
EVBUM2529/D
EVBUM2529/D
RSL10 Evaluation and
Development Board
User's Manual
INTRODUCTION
Purpose
This manual provides detailed information about the
configuration and use of the RSL10 Evaluation and
Development Board, both the wafer level chip scale package
(WLCSP) and the quad flat no-leads (QFN) package. The
Evaluation and Development Board is designed to be used
with the software development tools to evaluate the
performance and capabilities of the RSL10 radio
System-on-Chip (SoC).
Intended Audience
This manual is for engineers, developers, and anyone else
who requires technical information about the Evaluation
and Development Board.
Conventions
The following conventions are used in this manual to
signify particular types of information:
monospace fontConnector and pin names.
Manual Organization
The Evaluation and Development Board Manual contains
the following chapters and appendices:
•Chapter 1: Introduction describes the purpose of this
manual, describes the target reader, explains how the
book is organized, and provides a list of suggested
reading for more information.
•Chapter 2: Overview provides an overview of the
Evaluation and Development Board described in this
manual.
•Chapter 3: Evaluation and Development Board
provides the details of the Evaluation and Development
Board. The chapter is divided into the following topics:
♦Development Board Setup
♦Development Board Design
♦Power Supply
♦Level Translators
♦LED Circuitry
♦RSL10 SoC
♦Measuring the Current Consumption
♦SWJ−DP Debug Port
♦Digital Input/Output (DIO)
♦Power Supply and Test Points
•Appendix A: WLCSP Connectors provides
a complete list of the connectors and jumpers on
the WLCSP Evaluation and Development Board.
The appendix is divided into the following sections:
♦Configuration Header Jumpers
♦Headers
♦Switches
♦Connectors
•Appendix B: QFN Connectors provides a complete
list of the connectors and jumpers on the QFN
Evaluation and Development Board.
•Appendix C: WLCSP Schematics contains the
schematics for the WLCSP Evaluation and
Development Board.
•Appendix D: QFN Schematics contains the
schematics for the QFN Evaluation and Development
Board.
•Appendix E: WLCSP Bill of Materials contains a list
of the parts that are used to manufacture the WLCSP
Evaluation and Development Board.
•Appendix F: QFN Bill of Materials contains a list of
the parts that are used to manufacture the QFN
Evaluation and Development Board.
Further Reading
For more information, refer to the following documents:
•RSL10 Software Development Tools User’s Guide
•Firmware Reference Manual for RSL10
•Hardware Reference Manual for RSL10
•RSL10 Datasheet
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OVERVIEW
Introduction
The RSL10 Evaluation and Development Board is used
for evaluating the RSL10 SoC and for application
development. The board provides access to all input and
output connections via 0.1″ standard headers. The on-board
communication interface circuit provides communication to
the board from a host PC. The communication interface
translates RSL10 SWJ−DP debug port signals to the USB of
the host PC. There is also an on-board 4-bit level shifter for
debugging; it translates the I/O signal level of RSL10 to the
3.3 V digital logic level. It is not enabled by default; you
enable it when it is needed.
Evaluation and Development Board Features
The Evaluation and Development Board enables
developers to evaluate the performance and capabilities of
the RSL10 radio SoC in addition to developing,
demonstrating and debugging applications.
Key features of the board include:
•J−Link onboard solution provides a SWJ−DP
(serial-wire and/or JTAG) interface that enables you to
debug the board via a USB connection with the PC
•Alternate onboard SWJ−DP (serial-wire and/or JTAG)
interface for Arm Cortex−M3 processor debugging
•Access to all RSL10 peripherals via standard 0.1″
headers
•Onboard 4-bit level translator to translate the LPDSP32
debug interface at low voltage to a 3.3 V JTAG
debugger
•Antenna matching and filtering network
•Integrated PCB antenna
In addition, the QFN board provides:
•Compliance with the Arduino form factor
•Support for PMOD (i.e., J4 is a standard connector)
EVALUATION AND DEVELOPMENT BOARD
Evaluation and Development Board Setup
This section is an overview of how to configure the
Evaluation and Development Board. Details of the
development board configuration are discussed later in this
manual.
Figure 1 represents an overview of the board setup.
Figure 1. Evaluation and Development Board Setup
RSL10
Evaluation and
Development
Board
Micro USB Cable
If you want to use an external J−Link debugger instead of
the onboard one, connect the debugger to the JTAG port of
the WLCSP board, or to connector P2 on the QFN board, as
shown in Figure 2. Notice that for this setup, you also need
a power supply.
Figure 2. Evaluation and Development Board Setup with External J−Link Debugger
Micro USB Cable
J−Link
Debugger
10/9 Pin Connector
RSL10 Evaluation and
Development Board
P2 or JTAG
Port
Power Supply
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Evaluation and Development Board Design
The following sections detail the various sub-circuits of
the RSL10 Evaluation and Development Board. The block
diagram in Figure 3 shows the locations of the various
circuit sections for the WLCSP board. The block diagrams
in Figure 4 and Figure 5 show the locations of the circuit
sections for the QFN board. Figure 6 and Figure 7 provide
3-dimensional illustrations of the QFN board.
Figure 3. Circuit Location Block Diagram for WLCSP Board
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Figure 4. Circuit Location Block Diagram for QFN Board (Top View)
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Figure 5. Circuit Location Block Diagram for QFN Board (Bottom View)
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Figure 6. Three-Dimensional Line Drawing of the QFN Board (Top View)
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Figure 7. Three-Dimensional Line Drawing of the QFN Board (Bottom View)
Power Supply
The Evaluation and Development Board can be powered
by one of the following:
•Micro USB port with regulator
•External power supply connector (P5 for QFN, P9 for
WLCSP) with regulator
•External power supply connector (P5 for QFN, P9 for
WLCSP) without regulator
For the WLCSP board, use the jumpers on pin headers P6
and P8 to select a power supply option as shown in Table 1.
Table 1. POWER SUPPLY SELECTION FOR WLCSP
Power Source Jumper Position on P6 Jumper Position on P8
Micro USB Port with Regulator 1&2 1&2
External Power Supply with Regulator 1&2 3&4
External Power Supply without Regulator 2&3 5&6
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For the QFN board, use the jumpers on pin headers P4,
P7 and P10 to select a power supply option as show in
Table 2.
Table 2. POWER SUPPLY SELECTION FOR QFN
Power Source Jumper Position on P4 Jumper Position on P7 Jumper Position on P10
Micro USB Port with Regulator 1&2 2&3 1&2
External Power Supply with Regulator 3&4 2&3 1&2
External Power Supply without Regulator 1&2, 5&6 2&3 2&3
Table 3. MINIMUM/MAXIMUM EXTERNAL REGULATED VOLTAGES
Power Supply Header
Input Voltage
Minimum Typical Maximum
RSL10 and J−Link OB MCU EXT−PSU Regulated 3.3 V 3.6 V 12.0 V
RSL10 and J−Link OB MCU USB − 5.0 V −
RSL10 EXT−PSU Unregulated 1.1 V 1.25 V 3.6 V
Level Translators
The board has level translators for the DIO signals of
RSL10, including the clock signal. The level translators
facilitate interfacing to external devices that operate at a
higher voltage than RSL10.
VDDO and 3.3 V are two different power rails. The
translator allows a logic signal on the VDDO side to be
translated to either a higher or a lower logic signal voltage
on the 3.3 V side, and vice-versa.
The level translation circuitry consists of components U4
and the 2x4 header. Signals are translated from the VDDO
voltage reference to 3.3 V (default) voltage provided by the
regulator output or by an external supply. The VDDO
voltage is configured by the pin on header P11 (located on
the board edge) to either VBAT_DUT, 3.3 V or other level
within the VDDO voltage range, which is 1.1 to 3.3 V.
The NLSX5014 level translators are bi-directional. They
have the following features:
•Wide voltage operating range: 0.9 V to 4.5 V
•VDDO and 3.3 V are independent
•VDDO can be equal to, or less than, 3.3 V when
connected to the power rail
To enable the level translators, populate positions R34 and
R35 with 0 ohms. By default, the level translators are
disabled. NOTE: Enabling the level translator affects power
consumption.
LED Circuitry
There are two LEDs on the board. One is a dual color LED,
called LD1, connected to the J−Link emulator
microcontroller unit (MCU). The other is the green LED,
connected to DIO 6 of RSL10. You can use this LED within
your applications as an indication LED by programming
DIO 6. If DIO 6 is high, this LED is on.
Measuring the Current Consumption
This section deals with measuring current consumption
for both WLCSP and QFN versions of the Evaluation and
Development Board.
Measuring Current Consumption for WLCSP
The RSL10 VBAT main system supply can be the USB’s
5 V ±5% through the 3.3 V regulator, or the external
regulated 3.3 V supply, or the supply can be an external
power source without regulator. For more information, refer
to Section “Power Supply” on page 7.
The current measurement header (P7) located on
the board is provided to measure the current consumption of
RSL10. For normal operation, short the current
measurement header. When using an external supply,
ensure that the recommended voltage level for RSL10 is not
exceeded. Refer to Table 3 on page 8 for minimum and
maximum voltages.
Headers are provided for each of the regulated voltages
for additional capacitance and/or for measurements. RSL10
has 16 digital I/Os. The VDDO pin in header P11 configures
the I/O voltages for power domains to either VBAT or to
some other voltage.
To measure the current consumption of RSL10 only, you
must use an unregulated external power supply, and remove
the jumpers that connect nRESET, SWDIO and SWCLK
between the MCU and RSL10, preventing leakage from the
JTAG interface. For WLCSP boards, remove the jumpers on
header P12.
Measuring Current Consumption for QFN
The current measurement header (P3) located on
the board is provided to measure the current consumption of
RSL10. For normal operation, short the current
measurement header. When using an external supply,
ensure that the recommended voltage level for RSL10 is not
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exceeded. Refer to Table 3 on page 8 for minimum and
maximum voltages.
Headers are provided for each of the regulated voltages
for additional capacitance and/or for measurements. RSL10
has 16 digital I/Os. The VDDO pin in header P9 configures
the I/O voltages for power domains to VBAT.
To measure the current consumption of RSL10 only, you
must use an unregulated external power supply, and remove
the jumpers on header SWD. Removing the jumpers
between the MCU and RSL10 that connect nRESET,
SWDIO and SWCLK prevents current leakage from the
JTAG interface, avoiding inaccurate current measurements.
SWJ−DP DEBUG Port
The J−Link adapters are typically used to communicate
with RSL10 using the standard Coresight SWJ−DP debug
port in a JTAG/SW communication protocol. The 9-pin 0.05
in Samtec FTSH header (P3 for WLCSP, P1 for QFN),
defined by the Arm Cortex−M3 core on the board, connects
RSL10 to external adapters compatible with the Arm
Cortex−M3 processor’s SWJ−DP interface. Alternatively,
you can connect the micro USB port on the board to a PC.
DIGITAL Input/Output (DIO)
RSL10 contains 16 digital I/O (DIO) signals. The DIO
voltage domain is VDDO, while the input voltage can be
VBAT or external voltage as outlined in Section “Measuring
the Current Consumption” on page 8.
The DIO signals on RSL10 are multiplexed with several
interfaces, including:
•One I2C interface (on DIO [7:8] for QFN)
•Four external inputs to the low-speed analog to digital
converters (on DIO [0:3] for QFN)
•One PCM interface
•Two PWM drivers
•Two SPI interfaces (on DIO [9:12] and DIO
[13:15] for QFN)
•One UART interface (on DIO [4:5] for QFN)
•Support interfaces that can be used to monitor control
of the RF front-end and Bluetooth baseband controller
For more information about the DIO multiplexed signals,
refer to the Hardware Reference Manual for RSL10.
The WLCSP board provides access to any of the DIOs or
their multiplexed signals via the DIO0-15 headers. One
16-pin protected header, organized in a 2x8 configuration,
is provided on the board.
The QFN board provides access to any of the DIOs or their
multiplexed signals via the Arduino Headers (Power1,
AD1, IOL1, and IOH1).
The LED circuit provides visual monitoring of the DIOs;
refer to Section “LED Circuitry” on page 8 for further
information.
Power Supplies and Test Points
There are several external power supplies available on
your Evaluation and Development Board. Depending on
what type of board you are working with, test points might
also be present.
The user can also access signals on various headers on
boards, as described throughout this document.
WLCSP Power Supply and Test Points
External power supplies available for WLCSP boards are:
•VBUS, 5 V from USB connection − available only
when USB is plugged in
•V3.3, 3.3 V from LDO − available when regulated
supply is selected
•VEXT, unregulated external supply − available when
unregulated supply is selected
The user can also access signals on various headers on
boards, as described throughout this document.
The WLCSP board includes several test points which the
user can access to measure the following internal power
supplies:
•VDDA
•VDDC
•VDDM
•VDDPA
•VCC
•VDDRF
•VPP
QFN Power Supplies
The external power supplies available for QFN boards
are:
•VBUS, 5 V from USB connection − available only
when USB is plugged in
•V3.3, 3.3 V from LDO − available when regulated
supply is selected
•VEXT, (P5 header) unregulated external supply −
available when unregulated supply is selected
•Battery (J5 Battery Holder, 12 mm coin cell battery)
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APPENDIX A − WLCSP CONNECTORS
Overview
This appendix lists all connectors on the Evaluation and Development Board. The sections that follow provide descriptions
for:
•Jumpers and their possible configurations
•Headers
•Switches and their possible configurations
•Connectors
Configuration Header Jumpers
Table 4. JUMPER DESCRIPTIONS
Designator Description
P6 Regulated or Unregulated power supply selection (see Table 1 on page 7)
P8 Power Source Selection (see Table 1 on page 7)
P11 VDDO selection between VBAT_DUT and V3.3
VDD_AT selection between 3.3 V and VEXT, removing R39
Headers
Table 5. HEADER DESCRIPTIONS
Designator Description
P1 DIO signals
P2 External slow clock input header
P3 JTAG debug connection header
P4 Virtual UART port from PC
P5 Analog test header
P7 Current measurement header
P9 External power supply header
P10 Input and output of level shifter
P11 Power supply on board and supply voltage configuration header
Switches
Table 6. SWITCH DESCRIPTIONS
Designator Description
RESET Pushbutton switch to reset RSL10
DIO5 Pushbutton switch for DIO5
Connectors
Table 7. CONNECTOR DESCRIPTIONS
Designator Description
J1 Micro USB port for power supply, JTAG and UART emulation
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APPENDIX B − QFN CONNECTORS
Overview
This appendix lists all connectors on the QFN Evaluation and Development Board. The sections that follow provide
descriptions for:
•Jumpers and their possible configurations
•Headers
•Switches and their possible configurations
•Connectors
Configuration Header Jumpers
Table 8. JUMPER DESCRIPTIONS
Designator Description
P4 Regulated or Unregulated power supply selection
P10 VBAT Power Source selection (3.3 V, Vext or Battery)
P9 VDDO selection (VBAT_DUT, 3.3 V)
P8 VDD_AT selection (3.3 V, VDDO)
P1 Onboard JTAG debugger connection
Headers
Table 9. HEADER DESCRIPTIONS
Designator Description
POWER1 Arduino Power header 3.3 V, VDDO, nRESET, GND
AD1 Arduino Analog Inputs header A [0:3]
IOL1 Arduino IOL header UART, INT [0:1], SPI2
IOH1 Arduino IOH header I2C, SPI1
P2 External JTAG debug connection header
P3 Current measurement header
P5 External power supply header
P6 Input and output of level shifter
Switches
Table 10. SWITCH DESCRIPTIONS
Designator Description
SW1 Pushbutton switch to reset RSL10
SW2 Pushbutton switch for DIO5
Connectors
Table 11. CONNECTOR DESCRIPTIONS
Designator Description
J1 RF switch connector
J2 Micro USB port for power supply, JTAG and UART emulation
J3 MCU programming connector
J4 Digilent PMOD peripheral connector I2C, SPI1, INT0
J5 Battery Holder (12 mm coin cell)
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APPENDIX C − WLCSP SCHEMATICS
This appendix contains schematics for the WLCSP Evaluation and Development Board:
•The Interface MCU schematic
•The RSL10 schematic
•The Power Supply schematic
These schematics are for Version 1.1 and Version 1.2 of the WLCSP board.
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Figure 8. Interface MCU Schematic
NRSTB
47
PA0/TIOB0/NPCS1
26
PA1/TIOA0/NPCS2
27
PA10/TWCK0/PWML3
39
PA11/URXD/PWMFI0
40
PA12/UTXD/PWMFI1
41
PA13/MISO
10
PA14/MOSI
11
PA15/SPCK/PWMH2
12
PA16/NPCS0/NCS1
13
PA17/SCK0/ADTRG
14
PA18/TXD0/PWMFI2
17
PA19/RXD0/NPCS3
18
PA2/TCLK0/AD12BTRG
28
PA20/TXD1/PWMH3
19
PA21/RXD1/PCK0
20
PA22/TXD2/RTS1/AD12B0
5
PA23/RXD2/CTS1
21
PA24/TWD1/SCK1
23
PA25/TWCK1/SCK2
24
PA26/TD/TCLK2
25
RD/PCK0/PA27 96
TK/PWMH0/PA28 84
RK/PWMH1/PA29 85
PA3/MCCK/PCK1
29
PA30/TF/TIOA2/AD12B1
6
PA4/MCCDA/PWMH0
30
PA5/MCDA0/PWMH1
31
PA6/MCDA1/PWMH2
32
PA7/MCDA2/PWML0
33
PA8/MCDA3/PWML1
37
PA9/TWD0/PWML2
38
PWMH0/A2/PB0 90
PWMH1/A3/PB1 91
D1/DSR0/PB10 70
D2/DCD0/PB11 93
D3/RI0/PB12 94
D4/PWMH0/PB13 95
D5/PWMH1/PB14 69
PB15/D6/PWMH2
16 PB16/D7/PWMH3
15
NANDOE/PWML0/PB17 68
NANDWE/PWML1/PB18 67
NRD/PWML2/PB19 66
PWMH2/A4/PB2 92
NCS0/PWML3/PB20 65
A21(NANDALE/RTS2/PB21 64
A22/NANDCLE/CTS2/PB22 63
NWR0/NWE/PCK2/PB23 62
NANDRDY/PCK1/PB24 58
AD12BVREF
4
DHSDP 76
DHSDM 77
VBG 78
DFSDM 80
PB3/PWMH3/A5/AD12BAB2
7
DFSDP 81
PB4/TCLK1/A6/AD12BAB3
8
TIOA1/A7/AD0/PB5 97
TIOB1/D15/AD1/PB6 98
RTS0/A0/NBS0/AD2/PB7 99
CTS0/A1/AD3/PB8 100
D0/DTR0/PB9 71
RF/TIOB2/PA31 86
ADVREF
2
XIN32
50 XOUT32
49
ERASE
43
NRST 57
FWUP
42
XIN 75
XOUT 74
TEST
44
JTAGSEL
48
TCK 56
TDI 51
TDO 54
TMS 55
GNDANA
3
GND
35
GNDBU
46
GND 61
GNDPLL 72
GNDUTMI 82
GND 89
VDDCORE
9
VDDCORE
34
VDDCORE 59
VDDCORE 87
VDDBU
45
VDDIN 53
VDDANA
1
VDDIO
22
VDDIO
36
VDDIO 60
VDDIO 88
VDDOUT 52
VDDPLL 73
VDDCORE 83
VDDUTMI 79
U2
ATSAM3U2CA−AU
VDD_AT
GND
VDD_AT
TCKin
R20
0
C34
100nF
VCORE
TDIin
TMSin
TCKout
TMSout
TDIout
TDOin
ENSPIVDD_AT
TCKout
0R29
DNP 0R30
DNP
TRSTin
TRESin
TRSTout
TRESout
C42
100nF C43
100nF
VDD_AT
CTS
RTS
RxD
TxD
C41
100nF
VDD_AT
R34
6k8 C40
100nF
IMCU_TDIS
IMCU_TDOS
IMCU_TMSS
IMCU_TCKS
IMCU_RESET
C39
10µF
VCORE
C38
10µF
C37
100nF
VDD_AT
C35
100nF C36
100nF
VCORE
VDD_AT
C33
100nF
VCORE
X3
12MHz
C30
18pF
C32
18pF
DFSD_P
DFSD_N
DHSD_N
DHSD_P
C26
10pF
R18
6k8 C27
100nF
VDD_AT
C22
100nF
VCORE
C23
100nF
VCORE
C24
100nF
R16
6k8
ENSPI
VBUS 1
D− 2
D+ 3
GND 5
ID 4
Shield
J2
MicroUSB−B
C25
100nF
R17
6k8 GND 1
IO1 2
VCC
4
IO2
3D1
PRTR5V0U2X
C28
10µF
R11
39
R12
39
DFSD_P
DFSD_N
DHSD_N
DHSD_P 1 10
2 9
374 65
8
J3
TC2050−IDC
R13
4k7 R14
4k7 R15
4k7
R19
4k7
VDD_AT VDD_AT
VBUS
VBUS
IMCU_TMSS
IMCU_TCKS
IMCU_TDOS
IMCU_TDIS
IMCU_RESET
R22
150
R24
150
R26
150
R28
150
R32
150
TRSTout
TRSTin
TDIout
TDIin
TMSout
TMSin
TCKout
TCKin
TRESout
TRESin
TDOin
TRST
TDI
TMS/SWDIO
TCK/SWCLK
NRESET
TDO
12
3
4
P4
LIST−2x2 Header
CTS
RTS TxD
RxD
RG LD1
LTST−C195KGJRKT
R25
220 R27
220
VDD_AT
C29
100nF
C31
100nF
1 2
3 4
5 6
P12
2x3 Pin Header
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Figure 9. RSL10 Schematic
X2
32.768kHz
J1
MM8130−2600
C7
2pF L1
5.7nH
L4
2.2µH
C19
DNP
VCC
C21
1uF
12 34 5
8 7
10 9
12 11
14 13
6
1516
P1
Pin Header 2x8
R5 68
R7 68
R8 68
R9 68
R2
68
R1
68
TCK/SWCLK
TMS/SWDIO
VDDPA
VDDC
VPP
VDDM
VDDSYN_SW
VDDRF
VDDA
VDDO
C3
4.7µFC4
100nF C5
100pF
VBAT_DUT
VDDO
C12
DNP
VDDPA
C13
DNP
VDDM VDDC
C14
DNP C15
DNP
VDDRF
C16
DNP
VDDA
C2
DNP
C1
DNP
WAKEUP
1
2
P2
LIST−1X2
NRESET
SW1
PB SW
NRESET
R6
10k
VBAT_DUT
EN_TEST
NRESET
TRST
TDI
TDO
1 2
3 4
587 109
6
P3
FTSH−105
VDDO
TCK/SWCLK
TMS/SWDIO
TMS/SWDIO
TCK/SWCLK
TDO
TDI
NRESET
TDO
TDI
DIO4 K2
DIO5 K1
DIO6 J1
DIO7 H1
DIO8 G2
DIO9 E2
DIO10 D1
DIO11 B2
DIO12 A1
DIO13 A2
DIO14 A3
DIO15 A4
AOUT L6
VDDO B4
VDDA F11
VDDRF A11
VDDRF_SW A9
VDDSYN_SW B8
VDDM F4
VPP J6
VDDC H6
VDDPA C11
VBAT K5
VBAT1 K7
RF
B11
VDC
J11
VCC
K11
CAP0
H11
CAP1
G10
XTAL48M_OUT
A6
XTAL48M_IN
A8
XTAL32K_OUT
L11
XTAL32K_IN
L10
EXT_CLK
F1
WAKEUP
L8
NRESET
L9
EN_TEST
F8
VSSC
D6
VSSA
E10
VSSPA
D11
VSSRF
B9
VSS
B6
XBO5
F3
VSSL
F9
XBO2
K10
DIO0
L4
DIO1
L3
DIO2
L2
DIO3
L1
RSL 10
JTCK C1
JTMS B1
U1
RSL 10 WLCSP
1
2
P5
LIST−1X2
C11
1uF C18
1uF
C17
2.2uF
TP8
R4
DNP R10
DNP R21
DNP
SW2
PB SW
DIO5(Pairing)
DIO5(Pairing)
LED 1
L0603G
R23
68
GND
V3.3
DIO6(LED)
DIO6(LED) G
1
D3
S
2
Q1
NMOS
A1
2.4G PCB antenna
C20
4.7µF
TRST
I/O 1
G
2O/I 3
G
4X1
48MHz XTAL
C8
1.5pF
C6
1.5pF
L2
1.8nH
L3
3nH
EVBUM2529/D
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15
Figure 10. Power Supply Schematic
VBUS
C48
DNP
C45
4.7µF
C47
1uF
C46
1uF
1
2
3
P6 LIST−1x3 VBAT_DUT
R35
DNP
V3.3
VDDO V3.3 VBUSVBAT_DUT VDD_AT
V3.3 VDD_AT
R39
0
1
2
P9
Pin List 1x2, Angled
1 2
3 4
5 6
P8
2x3 Pin Header
TP1 TP2 TP3 TP4 TP5 TP6
VDDA VDDC VDDM VDDPA VCC VDDRF
VEXT
VL
1
I/O VL1
2
I/O VL2
3
I/O VL3
4
I/O VL4
5
NC
6
GND
7I/O Vcc4 8
NC 9
I/O Vcc3 10
I/O Vcc2 11
I/O Vcc1 12
Vcc 13
EN 14
U4
NLSX5014
VDDO
C51
1uF C52
10nF
R38
10k C49
10nF C50
1uF
V3.3
1
3
5
2
4
678
P10
2x4 Header
1
2
3
4
5
6
7
8
9
10
P11
Pin List 1x10
VEXT
VPP
TP7
R33
DNP
R31
DNP
1
2
P7
Pin List 1x2, Angled
Vin
1
GND
2
EN
3N/C 4
Vout 5
U3
NCP114ASN330T1G
VDDO
WAKEUP
V3.3
Range 1.1V − 3.3V
VDDO is the digital IO ring supply (provided externally).
EVBUM2529/D
www.onsemi.com
16
APPENDIX D − QFN SCHEMATICS
This appendix contains schematics for the QFN Evaluation and Development Board, version 1.3:
•The Top-level (Arduino interface) schematic
•The RSL10 schematic
•The Interface MCU schematic
•The Power Supply schematic
EVBUM2529/D
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Figure 11. Top-Level (Arduino Interface) Schematic
GND
AD0 1
AD1 2
AD2 3
AD3 4
AD4 5
AD5 6
AD1
VIN 8
GND 7
GND 6
5V 5
3V3 4
RESET 3
IOREF 2
1
POWER1
IO8
1IO9
2IO10
3IO11
4IO12
5IO13
6GND
7AREF
8SDA
9SCL
10 IOH1
IOH
IO0
1
IO2
3IO3
4IO4
5IO5
6IO6
7IO7
8
IO1
2
IOL1
IOL
DIO[7..0] DIO[15..8]
JTAG_TMS
JTAG_TCK
RESET
TRSTin
TDIin
TDOin
U_RSL10
RSL10.SchDoc
GND
TRSTin
TDIin
TMSin
TCKin
TRESin
TDOin
DIO4
DIO5
U_Interface MCU
Interface MCU.SchDoc
DIO[7..0]
DIO0
DIO1
DIO2
DIO3
INT0
DIO[15..8]
DIO13
DIO14
DIO15
DIO10
DIO11
DIO12
SCL
SDA
DIO[7..0] DIO[15..8]
INT0
SPI_CS
U_Power
Power.SchDoc
VDDO
5V
VIN3.3V
1 2
3 4
5 6
P1
2x3 Pin Header
DIO4
DIO5
SDA
SCL
1
2
3
4
5
6
7
8
9
10
11
12
J4
GND
SPI_CLK1
SPI_DATAI1
SPI_DATAO1
SPI1_CS1
SWO/DIO11
AREF
I2C_SDA1
I2C_SCK1
SWDIO/DIO13
SWDCLK/DIO12
SPI_DATAI2/DIO16
INT2
SPI_CLK2/DIO14
PWM1
INT0
UART1_TX
UART1_RX
J7−BB
J8−BB
J20−BB
VCOM
3V3_KNX
RESET
IOREF
IOREF
5V
GND
GND
J21−BB
A0
A1
A2
A3
I2C_EXP_GPIO12
I2C_EXP_GPIO13
SCL
SDA
INT0
SPI_CS
SPI_CS
SPI_CS
DIO10 INT0
DIO13
SCL
DIO11
DIO12
GND
SDA
VDDO
RESET
JTAG_TCK
JTAG_TMS
TDOin
TDIin
TRSTin
TMSin
TCKin
TRESin
GND
PMOD
EVBUM2529/D
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18
Figure 12. RSL10 SoC Schematic
VDDRF 48
RFIO 1
VDDPA 2
VSSPA
3
AOUT 4
VDDA 5
CAP1
6
CAP0
7
VSSA
8
VBAT 9
VDC
10
EN_TEST 11
VCC
12
XTAL32K_OUT 13
XTAL32K_IN 14
WAKEUP 15
RESET 16
VPP 17
DIO0
18
VDDC 19
DIO1
20
VDDM 21
DIO9 22
DIO2
23
DIO4
24 DIO3
25
DIO8 26
DIO5
27
VSSD
28
DIO6
29
DIO7
30
EXT_CLK
31
DIO10 32
JTCK 33
JTMS 34
VSSD
35
VDDO 36
DIO12 37
DIO11 38
DIO13 39
DIO15 40
DIO14 41
VSS
42
XTAL48M_N
43
XTAL48M_P
44
VDDSYN_SW 45
VSSRF
46 VDDRF_SW 47
RSL10
EP
49
U1
RSL10
GND
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
DIO6
DIO7
DIO[7..0]
DIO[7..0] DIO8
DIO9
DIO10
DIO11
DIO12
DIO13
DIO14
DIO15
DIO[15..8]
DIO[15..8]
JTAG_TMS
JTAG_TCK
X2
32.768kHz
I/O 1
G
2O/I 3
G
4X1
ECS 48MHz XTAL C17
1uF
VCC
0603
C16
4.7µF
GND
J1
MM8130−2600 C14
12pF
L3
15nH
A1
2.4G PCB antenna
R1
68
R2
68
RESET
R9
68
R6
DNP
R5
DNP
R3
DNP TRSTin
TDIin
TDOin
DIO13
DIO14
DIO15
VDDO
C2
DNP
VDDPA
C3
DNP
VDDM VDDC
C4
DNP C5
DNP
VDDRF
C6
DNP
VDDA
C1
1uF C8
1uF
C7
2.2uF
VDDPA VDDC VDDOVDDM VDDRF VDDAVPP VDDSYN_SW
0603
C9
4.7µFC10
100nF C11
100pF
VBAT_DUT
VBAT_DUT
SW2
PB SW
R7
10k
VBAT_DUT
SW1
PB SW
DIO5
LED 1
L0603G
R4
68
GND
V3.3
DIO6 G1
D3
S
2
Q1
NMOS
1 2
3 4
587 109
6
P2
FTSH−105
VDDO
JTAG_TMS
JTAG_TCK
TDOin
TDIin
RESET
RESET
JTAG_TMS
JTAG_TCK
TDOin
TDIin
C12
1.5pF C13
1.5pF
L1
3nH
L2
1.8nH
TP1
TP2
TP3
TRSTin
0805
L4
2.2uH
2.2uF
0402
C15
DNP
R54
100k
VDDO
EVBUM2529/D
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19
Figure 13. Interface MCU Schematic
NRSTB
47
PA0/TIOB0/NPCS1
26
PA1/TIOA0/NPCS2
27
PA10/TWCK0/PWML3
39
PA11/URXD/PWMFI0
40
PA12/UTXD/PWMFI1
41
PA13/MISO
10
PA14/MOSI
11
PA15/SPCK/PWMH2
12
PA16/NPCS0/NCS1
13
PA17/SCK0/ADTRG
14
PA18/TXD0/PWMFI2
17
PA19/RXD0/NPCS3
18
PA2/TCLK0/AD12BTRG
28
PA20/TXD1/PWMH3
19
PA21/RXD1/PCK0
20
PA22/TXD2/RTS1/AD12B0
5
PA23/RXD2/CTS1
21
PA24/TWD1/SCK1
23
PA25/TWCK1/SCK2
24
PA26/TD/TCLK2
25
RD/PCK0/PA27 96
TK/PWMH0/PA28 84
RK/PWMH1/PA29 85
PA3/MCCK/PCK1
29
PA30/TF/TIOA2/AD12B1
6
PA4/MCCDA/PWMH0
30
PA5/MCDA0/PWMH1
31
PA6/MCDA1/PWMH2
32
PA7/MCDA2/PWML0
33
PA8/MCDA3/PWML1
37
PA9/TWD0/PWML2
38
PWMH0/A2/PB0 90
PWMH1/A3/PB1 91
D1/DSR0/PB10 70
D2/DCD0/PB11 93
D3/RI0/PB12 94
D4/PWMH0/PB13 95
D5/PWMH1/PB14 69
PB15/D6/PWMH2
16 PB16/D7/PWMH3
15
NANDOE/PWML0/PB17 68
NANDWE/PWML1/PB18 67
NRD/PWML2/PB19 66
PWMH2/A4/PB2 92
NCS0/PWML3/PB20 65
A21(NANDALE/RTS2/PB21 64
A22/NANDCLE/CTS2/PB22 63
NWR0/NWE/PCK2/PB23 62
NANDRDY/PCK1/PB24 58
AD12BVREF
4
DHSDP 76
DHSDM 77
VBG 78
DFSDM 80
PB3/PWMH3/A5/AD12BAB2
7
DFSDP 81
PB4/TCLK1/A6/AD12BAB3
8
TIOA1/A7/AD0/PB5 97
TIOB1/D15/AD1/PB6 98
RTS0/A0/NBS0/AD2/PB7 99
CTS0/A1/AD3/PB8 100
D0/DTR0/PB9 71
RF/TIOB2/PA31 86
ADVREF
2
XIN32
50 XOUT32
49
ERASE
43
NRST 57
FWUP
42
XIN 75
XOUT 74
TEST
44
JTAGSEL
48
TCK 56
TDI 51
TDO 54
TMS 55
GNDANA
3
GND
35
GNDBU
46
GND 61
GNDPLL 72
GNDUTMI 82
GND 89
VDDCORE
9
VDDCORE
34
VDDCORE 59
VDDCORE 87
VDDBU
45
VDDIN 53
VDDANA
1
VDDIO
22
VDDIO
36
VDDIO 60
VDDIO 88
VDDOUT 52
VDDPLL 73
VDDCORE 83
VDDUTMI 79
U2
ATSAM3U2CA−AU
VDD_AT
GND
VDD_AT
TCKin
R21
0
C30
100nF
VCORE
TDIin
TMSin
TCKout
TMSout
TDIout
TDOin
ENSPI
VDD_AT
TCKout
0R26
DNP 0R27
DNP
TRSTin
TRESin
TRSTout
TRESout
C38
100nF C39
100nF
VDD_AT
CTS
RTS
RxD
TxD
C37
100nF
VDD_AT
R29
6k8
C36
100nF
IMCU_TDIS
IMCU_TDOS
IMCU_TMSS
IMCU_TCKS
IMCU_RESET
C35
10µF
VCORE
C34
10µF
C33
100nF
VDD_AT
C31
100nF C32
100nF
VCORE
VDD_AT
C29
100nF
VCORE
X3
12MHz
C26
18pF
C28
18pF
DFSD_P
DFSD_N
DHSD_N
DHSD_P
C22
10pF
R18
6k8 C23
100nF
VDD_AT
C18
100nF
VCORE
C19
100nF
VCORE
C21
100nF
R19
6k8
ENSPI
VBUS 1
D− 2
D+ 3
GND 5
ID 4
Shield
J2
MicroUSB−B
C20
100nF
R17
6k8 GND 1
IO1 2
VCC
4
IO2
3D1
PRTR5V0U2X
C24
10µF
R10
39
R11
39
DFSD_P
DFSD_N
DHSD_N
DHSD_P 1 10
2 9
374 65
8
J3
TC2050−IDC
R12
4k7 R13
4k7 R14
4k7
R20
4k7
VDD_AT VDD_AT
VBUS
VBUS
IMCU_TMSS
IMCU_TCKS
IMCU_TDOS
IMCU_TDIS
IMCU_RESET
R22
150
R23
150
R24
150
R25
150
R28
150
TRSTout
TRSTin
TDIout
TDIin
TMSout
TMSin
TCKout
TCKin
TRESout
TRESin
TDOin
TRSTin
TDIin
TMSin
TCKin
TRESin
TDOin
RG LD1
LTST−C195KGJRKT
R15
220 R16
220
VDD_AT
C25
100nF
C27
100nF
DIO4
DIO5
R30
68
R31
68
DIO4
DIO5
EVBUM2529/D
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20
Figure 14. Power Supply Schematic
VBUS
4.7 F
C43
DNP
C40
4.7 FC42
1uF
C41
1uF
Vin
1
GND
2
EN
3N/C 4
Vout 5
U3
NCP551SN32T1G VBAT_DUT
R32
DNP
V3.3
VDD_AT
1 2
3 4
56
P4
VL
1
I/O VL1
2
I/O VL2
3
I/O VL3
4
I/O VL4
5
NC
6
GND
7I/O Vcc4 8
NC 9
I/O Vcc3 10
I/O Vcc2 11
I/O Vcc1 12
Vcc 13
EN 14
U4
NLSX5014
VDDO
C46
1uF C47
10nF
R36
10k C44
10nF C4
5
1uF
V3.3
1
3
5
2
4
678
P6
2x4 Header
R35
DNI
R34
DNI
GND
VEXT
V3.3
VDDO
VDDO
R40
10k
20 14
IO1_3 13
IO1_2 12
IO1_0 10
IO1_5 15
IO0_7 8
IO0_6 7
IO0_5 6
IO0_4 5
IO0_3 4
IO0_2 3
IO0_1 2
IO0_0 1
INT
22
SCL
19
SDA
20
AD0
18
AD1
23
AD2
24
VSS
9
EP
25
PCA9655
IO1_6 16
IO1_7 17
VDD
21
U5
PCA9655
R51
10k
R41
10k
R42
10k
R43
10k R44
DNP
V3.3
R45
0
R46
DNP R47
0
R48
DNP
R49
DNP
R50
DNP
R52
0
R53
0
SCL
SDA
DIO[7..0] DIO7
DIO6
DIO7
DIO8
DIO6
DIO9
INT0
SPI_CS
DIO9
DIO8
DIO[15..8]
VIN3.3V
5V
V3.3
C48
100nF
1
2
3
J5
BAT-HLD-012
2
1
3
P8
2
1
3
P9
VDD_AT Select VDDO Select
Optional Level Shifter
2
1
P5
2
1
P3
2
1
3
P7
2
1
3
P10
VBAT VBAT Select
3.3V Select
Power Select
SDA
SCL
INT0
SPI_CS
POWER SUPPLY CONFIGURATION HEADERS P4, P7, P10
ARDUINO ORION POWERED VIN3.3V: P4 (no jumper), P7(1-2), P10(1-2)
STAND ALONE USB POWERED: P4(1-2), P7(2-3), P10(1-2)
STAND ALONE Vext POWERED: P4(3-4), P7(2-3), P10(1-2)
STAND ALONE USB and Vext POWERED: P4(1-2), (5-6), P7(2-3), P10(2-3)
(provided externally). Range : 1.1V - 3.3V
VDDO is the digital IO ring supply
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onsemi RSL10-002GEVB Operating instructions

Brand
onsemi
Model
RSL10-002GEVB
Type
Operating instructions
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