NXP KL2x Reference guide

KL24 Sub-Family Reference Manual

Supports: MKL24Z32VFM4, MKL24Z64VFM4, MKL24Z32VFT4,

MKL24Z64VFT4, MKL24Z32VLH4, MKL24Z64VLH4, MKL24Z32VLK4,

and MKL24Z64VLK4

Document Number: KL24P80M48SF0RM

Rev. 3, September 2012

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Contents

Section number Title Page

Chapter 1

About This Document

1.1 Overview.......................................................................................................................................................................31

1.1.1 Purpose.........................................................................................................................................................31

1.1.2 Audience......................................................................................................................................................31

1.2 Conventions..................................................................................................................................................................31

1.2.1 Numbering systems......................................................................................................................................31

1.2.2 Typographic notation...................................................................................................................................32

1.2.3 Special terms................................................................................................................................................32

Chapter 2

Introduction

2.1 Overview.......................................................................................................................................................................33

2.2 Kinetis L Series.............................................................................................................................................................33

2.3 KL24 Sub-Family Introduction.....................................................................................................................................36

2.4 Module functional categories........................................................................................................................................37

2.4.1 ARM® Cortex™-M0+ Core Modules.........................................................................................................37

2.4.2 System Modules...........................................................................................................................................38

2.4.3 Memories and Memory Interfaces...............................................................................................................39

2.4.4 Clocks...........................................................................................................................................................39

2.4.5 Security and Integrity modules....................................................................................................................39

2.4.6 Analog modules...........................................................................................................................................40

2.4.7 Timer modules.............................................................................................................................................40

2.4.8 Communication interfaces...........................................................................................................................41

2.4.9 Human-machine interfaces..........................................................................................................................41

2.5 Orderable part numbers.................................................................................................................................................42

Chapter 3

Chip Configuration

3.1 Introduction...................................................................................................................................................................43

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3.2 Module to Module Interconnects..................................................................................................................................43

3.2.1 Module to Module Interconnects.................................................................................................................43

3.2.2 Analog reference options.............................................................................................................................46

3.3 Core Modules................................................................................................................................................................46

3.3.1 ARM Cortex-M0+ Core Configuration.......................................................................................................46

3.3.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................49

3.3.3 Asynchronous wake-up interrupt controller (AWIC) configuration............................................................52

3.4 System Modules............................................................................................................................................................54

3.4.1 SIM Configuration.......................................................................................................................................54

3.4.2 System Mode Controller (SMC) Configuration...........................................................................................54

3.4.3 PMC Configuration......................................................................................................................................55

3.4.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................56

3.4.5 MCM Configuration....................................................................................................................................58

3.4.6 Crossbar-Light Switch Configuration..........................................................................................................59

3.4.7 Peripheral Bridge Configuration..................................................................................................................60

3.4.8 DMA request multiplexer configuration......................................................................................................61

3.4.9 DMA Controller Configuration...................................................................................................................64

3.4.10 Computer Operating Properly (COP) Watchdog Configuration..................................................................65

3.5 Clock Modules..............................................................................................................................................................68

3.5.1 MCG Configuration.....................................................................................................................................68

3.5.2 OSC Configuration......................................................................................................................................69

3.6 Memories and Memory Interfaces................................................................................................................................70

3.6.1 Flash Memory Configuration.......................................................................................................................70

3.6.2 Flash Memory Controller Configuration.....................................................................................................72

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3.6.3 SRAM Configuration...................................................................................................................................73

3.7 Analog...........................................................................................................................................................................75

3.7.1 12-bit SAR ADC Configuration..................................................................................................................75

3.7.2 CMP Configuration......................................................................................................................................78

3.8 Timers...........................................................................................................................................................................81

3.8.1 Timer/PWM Module Configuration............................................................................................................81

3.8.2 PIT Configuration........................................................................................................................................84

3.8.3 Low-power timer configuration...................................................................................................................85

3.8.4 RTC configuration.......................................................................................................................................87

3.9 Communication interfaces............................................................................................................................................88

3.9.1 Universal Serial Bus (USB) FS Subsystem.................................................................................................88

3.9.2 SPI configuration.........................................................................................................................................92

3.9.3 I2C Configuration........................................................................................................................................93

3.9.4 UART Configuration...................................................................................................................................94

3.10 Human-machine interfaces (HMI)................................................................................................................................95

3.10.1 GPIO Configuration.....................................................................................................................................95

Chapter 4

Memory Map

4.1 Introduction...................................................................................................................................................................99

4.2 System memory map.....................................................................................................................................................99

4.3 Flash Memory Map.......................................................................................................................................................100

4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................100

4.4 SRAM memory map.....................................................................................................................................................101

4.5 Bit Manipulation Engine...............................................................................................................................................101

4.6 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................102

4.6.1 Read-after-write sequence and required serialization of memory operations..............................................102

4.6.2 Peripheral Bridge (AIPS-Lite) Memory Map..............................................................................................103

4.6.3 Modules Restricted Access in User Mode...................................................................................................106

4.7 Private Peripheral Bus (PPB) memory map..................................................................................................................106

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Chapter 5

Clock Distribution

5.1 Introduction...................................................................................................................................................................109

5.2 Programming model......................................................................................................................................................109

5.3 High-Level device clocking diagram............................................................................................................................109

5.4 Clock definitions...........................................................................................................................................................110

5.4.1 Device clock summary.................................................................................................................................111

5.5 Internal clocking requirements.....................................................................................................................................113

5.5.1 Clock divider values after reset....................................................................................................................113

5.5.2 VLPR mode clocking...................................................................................................................................114

5.6 Clock Gating.................................................................................................................................................................115

5.7 Module clocks...............................................................................................................................................................115

5.7.1 PMC 1-kHz LPO clock................................................................................................................................116

5.7.2 COP clocking...............................................................................................................................................116

5.7.3 RTC clocking...............................................................................................................................................117

5.7.4 LPTMR clocking..........................................................................................................................................117

5.7.5 TPM clocking...............................................................................................................................................118

5.7.6 USB FS OTG Controller clocking...............................................................................................................118

5.7.7 UART clocking............................................................................................................................................119

Chapter 6

Reset and Boot

6.1 Introduction...................................................................................................................................................................121

6.2 Reset..............................................................................................................................................................................121

6.2.1 Power-on reset (POR)..................................................................................................................................122

6.2.2 System reset sources....................................................................................................................................122

6.2.3 MCU Resets.................................................................................................................................................125

6.2.4 Reset Pin .....................................................................................................................................................127

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6.2.5 Debug resets.................................................................................................................................................127

6.3 Boot...............................................................................................................................................................................128

6.3.1 Boot sources.................................................................................................................................................128

6.3.2 FOPT boot options.......................................................................................................................................128

6.3.3 Boot sequence..............................................................................................................................................129

Chapter 7

Power Management

7.1 Introduction...................................................................................................................................................................131

7.2 Clocking Modes............................................................................................................................................................131

7.2.1 Partial Stop...................................................................................................................................................131

7.2.2 DMA Wakeup..............................................................................................................................................132

7.2.3 Compute Operation......................................................................................................................................133

7.2.4 Peripheral Doze............................................................................................................................................134

7.2.5 Clock Gating................................................................................................................................................135

7.3 Power modes.................................................................................................................................................................135

7.4 Entering and exiting power modes...............................................................................................................................137

7.5 Module Operation in Low Power Modes......................................................................................................................137

Chapter 8

Security

8.1 Introduction...................................................................................................................................................................143

8.2 Flash Security...............................................................................................................................................................143

8.3 Security Interactions with other Modules.....................................................................................................................143

8.3.1 Security Interactions with Debug.................................................................................................................144

Chapter 9

Debug

9.1 Introduction...................................................................................................................................................................145

9.2 Debug Port Pin Descriptions.........................................................................................................................................145

9.3 SWD status and control registers..................................................................................................................................146

9.3.1 MDM-AP Control Register..........................................................................................................................147

9.3.2 MDM-AP Status Register............................................................................................................................148

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9.4 Debug Resets................................................................................................................................................................150

9.5 Micro Trace Buffer (MTB)...........................................................................................................................................151

9.6 Debug in Low Power Modes........................................................................................................................................151

9.7 Debug & Security.........................................................................................................................................................151

Chapter 10

Signal Multiplexing and Signal Descriptions

10.1 Introduction...................................................................................................................................................................153

10.2 Signal Multiplexing Integration....................................................................................................................................153

10.2.1 Port control and interrupt module features..................................................................................................154

10.2.2 Clock gating.................................................................................................................................................155

10.2.3 Signal multiplexing constraints....................................................................................................................155

10.3 Pinout............................................................................................................................................................................155

10.3.1 KL24 Signal Multiplexing and Pin Assignments........................................................................................155

10.3.2 KL24 Pinouts...............................................................................................................................................158

10.4 Module Signal Description Tables................................................................................................................................162

10.4.1 Core Modules...............................................................................................................................................162

10.4.2 System Modules...........................................................................................................................................163

10.4.3 Clock Modules.............................................................................................................................................163

10.4.4 Memories and Memory Interfaces...............................................................................................................163

10.4.5 Analog..........................................................................................................................................................163

10.4.6 Timer Modules.............................................................................................................................................164

10.4.7 Communication Interfaces...........................................................................................................................165

10.4.8 Human-Machine Interfaces (HMI)..............................................................................................................167

Chapter 11

Port control and interrupts (PORT)

11.1 Introduction...................................................................................................................................................................169

11.2 Overview.......................................................................................................................................................................169

11.2.1 Features........................................................................................................................................................169

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11.2.2 Modes of operation......................................................................................................................................170

11.3 External signal description............................................................................................................................................170

11.4 Detailed signal description............................................................................................................................................171

11.5 Memory map and register definition.............................................................................................................................171

11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................177

11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................179

11.5.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................180

11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................180

11.6 Functional description...................................................................................................................................................181

11.6.1 Pin control....................................................................................................................................................181

11.6.2 Global pin control........................................................................................................................................182

11.6.3 External interrupts........................................................................................................................................182

Chapter 12

System integration module (SIM)

12.1 Introduction...................................................................................................................................................................185

12.1.1 Features........................................................................................................................................................185

12.2 Memory map and register definition.............................................................................................................................185

12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................187

12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)....................................................................................188

12.2.3 System Options Register 2 (SIM_SOPT2)..................................................................................................189

12.2.4 System Options Register 4 (SIM_SOPT4)..................................................................................................191

12.2.5 System Options Register 5 (SIM_SOPT5)..................................................................................................193

12.2.6 System Options Register 7 (SIM_SOPT7)..................................................................................................194

12.2.7 System Device Identification Register (SIM_SDID)...................................................................................196

12.2.8 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................198

12.2.9 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................200

12.2.10 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................201

12.2.11 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................203

12.2.12 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................203

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12.2.13 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................205

12.2.14 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................206

12.2.15 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................207

12.2.16 Unique Identification Register Mid Low (SIM_UIDML)...........................................................................208

12.2.17 Unique Identification Register Low (SIM_UIDL)......................................................................................208

12.2.18 COP Control Register (SIM_COPC)...........................................................................................................209

12.2.19 Service COP Register (SIM_SRVCOP)......................................................................................................210

12.3 Functional description...................................................................................................................................................210

Chapter 13

System Mode Controller (SMC)

13.1 Introduction...................................................................................................................................................................211

13.2 Modes of operation.......................................................................................................................................................211

13.3 Memory map and register descriptions.........................................................................................................................213

13.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................213

13.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................215

13.3.3 Stop Control Register (SMC_STOPCTRL).................................................................................................216

13.3.4 Power Mode Status register (SMC_PMSTAT)...........................................................................................217

13.4 Functional description...................................................................................................................................................218

13.4.1 Power mode transitions................................................................................................................................218

13.4.2 Power mode entry/exit sequencing..............................................................................................................221

13.4.3 Run modes....................................................................................................................................................223

13.4.4 Wait modes..................................................................................................................................................225

13.4.5 Stop modes...................................................................................................................................................226

13.4.6 Debug in low power modes.........................................................................................................................229

Chapter 14

Power Management Controller (PMC)

14.1 Introduction...................................................................................................................................................................231

14.2 Features.........................................................................................................................................................................231

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14.3 Low-voltage detect (LVD) system................................................................................................................................231

14.3.1 LVD reset operation.....................................................................................................................................232

14.3.2 LVD interrupt operation...............................................................................................................................232

14.3.3 Low-voltage warning (LVW) interrupt operation.......................................................................................232

14.4 I/O retention..................................................................................................................................................................233

14.5 Memory map and register descriptions.........................................................................................................................233

14.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................234

14.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................235

14.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................236

Chapter 15

Low-Leakage Wakeup Unit (LLWU)

15.1 Introduction...................................................................................................................................................................239

15.1.1 Features........................................................................................................................................................239

15.1.2 Modes of operation......................................................................................................................................240

15.1.3 Block diagram..............................................................................................................................................241

15.2 LLWU signal descriptions............................................................................................................................................242

15.3 Memory map/register definition...................................................................................................................................242

15.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................243

15.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................244

15.3.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................245

15.3.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................246

15.3.5 LLWU Module Enable register (LLWU_ME)............................................................................................247

15.3.6 LLWU Flag 1 register (LLWU_F1).............................................................................................................249

15.3.7 LLWU Flag 2 register (LLWU_F2).............................................................................................................251

15.3.8 LLWU Flag 3 register (LLWU_F3).............................................................................................................252

15.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)..............................................................................................254

15.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)..............................................................................................255

15.4 Functional description...................................................................................................................................................256

15.4.1 LLS mode.....................................................................................................................................................257

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15.4.2 VLLS modes................................................................................................................................................257

15.4.3 Initialization.................................................................................................................................................257

Chapter 16

Reset Control Module (RCM)

16.1 Introduction...................................................................................................................................................................259

16.2 Reset memory map and register descriptions...............................................................................................................259

16.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................259

16.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................261

16.2.3 Reset Pin Filter Control register (RCM_RPFC)..........................................................................................262

16.2.4 Reset Pin Filter Width register (RCM_RPFW)...........................................................................................263

Chapter 17

Bit Manipulation Engine (BME)

17.1 Introduction...................................................................................................................................................................265

17.1.1 Overview......................................................................................................................................................266

17.1.2 Features........................................................................................................................................................266

17.1.3 Modes of Operation.....................................................................................................................................267

17.2 External Signal Description..........................................................................................................................................267

17.3 Memory Map and Register Definition..........................................................................................................................268

17.4 Functional Description..................................................................................................................................................268

17.4.1 BME Decorated Stores.................................................................................................................................268

17.4.2 BME Decorated Loads.................................................................................................................................274

17.4.3 Additional Details on Decorated Addresses and GPIO Accesses................................................................281

17.5 Application Information................................................................................................................................................282

Chapter 18

Miscellaneous Control Module (MCM)

18.1 Introduction...................................................................................................................................................................285

18.1.1 Features........................................................................................................................................................285

18.2 Memory map/register descriptions...............................................................................................................................285

18.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................286

18.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................287

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18.2.3 Platform Control Register (MCM_PLACR)................................................................................................287

18.2.4 Compute Operation Control Register (MCM_CPO)...................................................................................290

Chapter 19

Micro Trace Buffer (MTB)

19.1 Introduction...................................................................................................................................................................293

19.1.1 Overview......................................................................................................................................................293

19.1.2 Features........................................................................................................................................................296

19.1.3 Modes of Operation.....................................................................................................................................297

19.2 External Signal Description..........................................................................................................................................297

19.3 Memory Map and Register Definition..........................................................................................................................298

19.3.1 MTB_RAM Memory Map...........................................................................................................................298

19.3.2 MTB_DWT Memory Map...........................................................................................................................310

19.3.3 System ROM Memory Map.........................................................................................................................320

Chapter 20

Crossbar Switch Lite (AXBS-Lite)

20.1 Introduction...................................................................................................................................................................325

20.1.1 Features........................................................................................................................................................325

20.2 Memory Map / Register Definition...............................................................................................................................325

20.3 Functional Description..................................................................................................................................................326

20.3.1 General operation.........................................................................................................................................326

20.3.2 Arbitration....................................................................................................................................................327

20.4 Initialization/application information...........................................................................................................................328

Chapter 21

Peripheral Bridge (AIPS-Lite)

21.1 Introduction...................................................................................................................................................................329

21.1.1 Features........................................................................................................................................................329

21.1.2 General operation.........................................................................................................................................329

21.2 Functional description...................................................................................................................................................330

21.2.1 Access support.............................................................................................................................................330

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Chapter 22

Direct Memory Access Multiplexer (DMAMUX)

22.1 Introduction...................................................................................................................................................................331

22.1.1 Overview......................................................................................................................................................331

22.1.2 Features........................................................................................................................................................332

22.1.3 Modes of operation......................................................................................................................................332

22.2 External signal description............................................................................................................................................333

22.3 Memory map/register definition...................................................................................................................................333

22.3.1 Channel Configuration register (DMAMUXx_CHCFGn)..........................................................................333

22.4 Functional description...................................................................................................................................................334

22.4.1 DMA channels with periodic triggering capability......................................................................................335

22.4.2 DMA channels with no triggering capability...............................................................................................337

22.4.3 Always-enabled DMA sources....................................................................................................................337

22.5 Initialization/application information...........................................................................................................................338

22.5.1 Reset.............................................................................................................................................................338

22.5.2 Enabling and configuring sources................................................................................................................338

Chapter 23

DMA Controller Module

23.1 Introduction...................................................................................................................................................................343

23.1.1 Overview......................................................................................................................................................343

23.1.2 Features........................................................................................................................................................344

23.2 DMA Transfer Overview..............................................................................................................................................345

23.3 Memory Map and Registers..........................................................................................................................................346

23.3.1 Source Address Register (DMA_SARn).....................................................................................................347

23.3.2 Destination Address Register (DMA_DARn).............................................................................................348

23.3.3 DMA Status Register / Byte Count Register (DMA_DSR_BCRn).............................................................349

23.3.4 DMA Control Register (DMA_DCRn)........................................................................................................351

23.4 Functional Description..................................................................................................................................................355

23.4.1 Transfer Requests (Cycle-Steal and Continuous Modes)............................................................................355

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23.4.2 Channel Initialization and Startup................................................................................................................355

23.4.3 Dual-Address Data Transfer Mode..............................................................................................................357

23.4.4 Advanced Data Transfer Controls: Auto-Alignment...................................................................................358

23.4.5 Termination..................................................................................................................................................359

Chapter 24

Multipurpose Clock Generator (MCG)

24.1 Introduction...................................................................................................................................................................361

24.1.1 Features........................................................................................................................................................361

24.1.2 Modes of Operation.....................................................................................................................................364

24.2 External Signal Description..........................................................................................................................................365

24.3 Memory Map/Register Definition.................................................................................................................................365

24.3.1 MCG Control 1 Register (MCG_C1)...........................................................................................................366

24.3.2 MCG Control 2 Register (MCG_C2)...........................................................................................................367

24.3.3 MCG Control 3 Register (MCG_C3)...........................................................................................................368

24.3.4 MCG Control 4 Register (MCG_C4)...........................................................................................................368

24.3.5 MCG Control 5 Register (MCG_C5)...........................................................................................................370

24.3.6 MCG Control 6 Register (MCG_C6)...........................................................................................................371

24.3.7 MCG Status Register (MCG_S)..................................................................................................................372

24.3.8 MCG Status and Control Register (MCG_SC)............................................................................................374

24.3.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............................................................375

24.3.10 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............................................................375

24.3.11 MCG Control 7 Register (MCG_C7)...........................................................................................................376

24.3.12 MCG Control 8 Register (MCG_C8)...........................................................................................................376

24.3.13 MCG Control 9 Register (MCG_C9)...........................................................................................................377

24.3.14 MCG Control 10 Register (MCG_C10).......................................................................................................377

24.4 Functional Description..................................................................................................................................................378

24.4.1 MCG mode state diagram............................................................................................................................378

24.4.2 Low Power Bit Usage..................................................................................................................................382

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24.4.3 MCG Internal Reference Clocks..................................................................................................................382

24.4.4 External Reference Clock............................................................................................................................383

24.4.5 MCG Fixed frequency clock .......................................................................................................................383

24.4.6 MCG PLL clock ..........................................................................................................................................384

24.4.7 MCG Auto TRIM (ATM)............................................................................................................................384

24.5 Initialization / Application information........................................................................................................................385

24.5.1 MCG module initialization sequence...........................................................................................................385

24.5.2 Using a 32.768 kHz reference......................................................................................................................387

24.5.3 MCG mode switching..................................................................................................................................388

Chapter 25

Oscillator (OSC)

25.1 Introduction...................................................................................................................................................................399

25.2 Features and Modes......................................................................................................................................................399

25.3 Block Diagram..............................................................................................................................................................400

25.4 OSC Signal Descriptions..............................................................................................................................................400

25.5 External Crystal / Resonator Connections....................................................................................................................401

25.6 External Clock Connections.........................................................................................................................................402

25.7 Memory Map/Register Definitions...............................................................................................................................403

25.7.1 OSC Memory Map/Register Definition.......................................................................................................403

25.8 Functional Description..................................................................................................................................................404

25.8.1 OSC Module States......................................................................................................................................404

25.8.2 OSC Module Modes.....................................................................................................................................406

25.8.3 Counter.........................................................................................................................................................407

25.8.4 Reference Clock Pin Requirements.............................................................................................................407

25.9 Reset..............................................................................................................................................................................408

25.10 Low Power Modes Operation.......................................................................................................................................408

25.11 Interrupts.......................................................................................................................................................................408

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Chapter 26

Flash Memory Controller (FMC)

26.1 Introduction...................................................................................................................................................................409

26.1.1 Overview......................................................................................................................................................409

26.1.2 Features........................................................................................................................................................409

26.2 Modes of operation.......................................................................................................................................................410

26.3 External signal description............................................................................................................................................410

26.4 Memory map and register descriptions.........................................................................................................................410

26.5 Functional description...................................................................................................................................................410

Chapter 27

Flash Memory Module (FTFA)

27.1 Introduction...................................................................................................................................................................413

27.1.1 Features........................................................................................................................................................414

27.1.2 Block Diagram.............................................................................................................................................414

27.1.3 Glossary.......................................................................................................................................................415

27.2 External Signal Description..........................................................................................................................................416

27.3 Memory Map and Registers..........................................................................................................................................416

27.3.1 Flash Configuration Field Description.........................................................................................................416

27.3.2 Program Flash IFR Map...............................................................................................................................417

27.3.3 Register Descriptions...................................................................................................................................418

27.4 Functional Description..................................................................................................................................................426

27.4.1 Flash Protection............................................................................................................................................427

27.4.2 Interrupts......................................................................................................................................................427

27.4.3 Flash Operation in Low-Power Modes........................................................................................................428

27.4.4 Functional Modes of Operation...................................................................................................................428

27.4.5 Flash Reads and Ignored Writes..................................................................................................................428

27.4.6 Read While Write (RWW)...........................................................................................................................429

27.4.7 Flash Program and Erase..............................................................................................................................429

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27.4.8 Flash Command Operations.........................................................................................................................429

27.4.9 Margin Read Commands.............................................................................................................................434

27.4.10 Flash Command Description........................................................................................................................435

27.4.11 Security........................................................................................................................................................448

27.4.12 Reset Sequence............................................................................................................................................450

Chapter 28

Analog-to-Digital Converter (ADC)

28.1 Introduction...................................................................................................................................................................451

28.1.1 Features........................................................................................................................................................451

28.1.2 Block diagram..............................................................................................................................................452

28.2 ADC Signal Descriptions..............................................................................................................................................453

28.2.1 Analog Power (VDDA)...............................................................................................................................454

28.2.2 Analog Ground (VSSA)...............................................................................................................................454

28.2.3 Voltage Reference Select.............................................................................................................................454

28.2.4 Analog Channel Inputs (ADx).....................................................................................................................455

28.3 Register definition.........................................................................................................................................................455

28.3.1 ADC Status and Control Registers 1 (ADCx_SC1n)...................................................................................456

28.3.2 ADC Configuration Register 1 (ADCx_CFG1)...........................................................................................459

28.3.3 ADC Configuration Register 2 (ADCx_CFG2)...........................................................................................461

28.3.4 ADC Data Result Register (ADCx_Rn).......................................................................................................462

28.3.5 Compare Value Registers (ADCx_CVn).....................................................................................................463

28.3.6 Status and Control Register 2 (ADCx_SC2)................................................................................................464

28.3.7 Status and Control Register 3 (ADCx_SC3)................................................................................................466

28.3.8 ADC Offset Correction Register (ADCx_OFS)...........................................................................................467

28.3.9 ADC Plus-Side Gain Register (ADCx_PG).................................................................................................468

28.3.10 ADC Plus-Side General Calibration Value Register (ADCx_CLPD).........................................................468

28.3.11 ADC Plus-Side General Calibration Value Register (ADCx_CLPS)..........................................................469

28.3.12 ADC Plus-Side General Calibration Value Register (ADCx_CLP4)..........................................................469

28.3.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP3)..........................................................470

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Section number Title Page

28.3.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP2)..........................................................470

28.3.15 ADC Plus-Side General Calibration Value Register (ADCx_CLP1)..........................................................471

28.3.16 ADC Plus-Side General Calibration Value Register (ADCx_CLP0)..........................................................471

28.4 Functional description...................................................................................................................................................472

28.4.1 Clock select and divide control....................................................................................................................472

28.4.2 Voltage reference selection..........................................................................................................................473

28.4.3 Hardware trigger and channel selects..........................................................................................................473

28.4.4 Conversion control.......................................................................................................................................474

28.4.5 Automatic compare function........................................................................................................................481

28.4.6 Calibration function.....................................................................................................................................483

28.4.7 User-defined offset function........................................................................................................................484

28.4.8 Temperature sensor......................................................................................................................................485

28.4.9 MCU wait mode operation...........................................................................................................................486

28.4.10 MCU Normal Stop mode operation.............................................................................................................486

28.4.11 MCU Low-Power Stop mode operation......................................................................................................487

28.5 Initialization information..............................................................................................................................................488

28.5.1 ADC module initialization example............................................................................................................488

28.6 Application information................................................................................................................................................490

28.6.1 External pins and routing.............................................................................................................................490

28.6.2 Sources of error............................................................................................................................................492

Chapter 29

Comparator (CMP)

29.1 Introduction...................................................................................................................................................................497

29.2 CMP features................................................................................................................................................................497

29.3 6-bit DAC key features.................................................................................................................................................498

29.4 ANMUX key features...................................................................................................................................................499

29.5 CMP, DAC and ANMUX diagram...............................................................................................................................499

29.6 CMP block diagram......................................................................................................................................................500

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Section number Title Page

29.7 Memory map/register definitions..................................................................................................................................502

29.7.1 CMP Control Register 0 (CMPx_CR0).......................................................................................................502

29.7.2 CMP Control Register 1 (CMPx_CR1).......................................................................................................503

29.7.3 CMP Filter Period Register (CMPx_FPR)...................................................................................................505

29.7.4 CMP Status and Control Register (CMPx_SCR).........................................................................................505

29.7.5 DAC Control Register (CMPx_DACCR)....................................................................................................506

29.7.6 MUX Control Register (CMPx_MUXCR)..................................................................................................507

29.8 Functional description...................................................................................................................................................508

29.8.1 CMP functional modes.................................................................................................................................508

29.8.2 Power modes................................................................................................................................................517

29.8.3 Startup and operation...................................................................................................................................518

29.8.4 Low-pass filter.............................................................................................................................................519

29.9 CMP interrupts..............................................................................................................................................................521

29.10 DMA support................................................................................................................................................................521

29.11 CMP Asyncrhonous DMA support...............................................................................................................................522

29.12 Digital-to-analog converter...........................................................................................................................................522

29.13 DAC functional description..........................................................................................................................................523

29.13.1 Voltage reference source select....................................................................................................................523

29.14 DAC resets....................................................................................................................................................................523

29.15 DAC clocks...................................................................................................................................................................523

29.16 DAC interrupts..............................................................................................................................................................524

29.17 CMP Trigger Mode.......................................................................................................................................................524

Chapter 30

Timer/PWM Module (TPM)

30.1 Introduction...................................................................................................................................................................525

30.1.1 TPM Philosophy..........................................................................................................................................525

30.1.2 Features........................................................................................................................................................525

30.1.3 Modes of Operation.....................................................................................................................................526

30.1.4 Block Diagram.............................................................................................................................................526

KL24 Sub-Family Reference Manual, Rev. 3, September 2012

20 Freescale Semiconductor, Inc.

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NXP KL2x Reference guide

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