NXP MPC8271 Reference guide

MPC8272 PowerQUICC II™

Family Reference Manual

Supports

MPC8272

MPC8271

MPC8248

MPC8247

MPC8272RM

Rev. 2, 10/2005

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Document Number: MPC8272RM

Rev. 2, 10/2005

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Part I—Overview I

Overview 1

G2_LE Core 2

Memory Map 3

Part II—Configuration and Reset II

System Interface Unit (SIU) 4

Reset 5

Part III—The Hardware Interface III

External Signals 6

60x Signals 7

The 60x Bus 8

PCI Bridge 9

PLL and Clock Generator 10

Memory Controller 11

IEEE 1149.1 Test Access Port 12

Part IV—Communications Processor Module IV

Communications Processor Module Overview 13

Serial Interface with Time-Slot Assigner 14

CPM Multiplexing 15

Baud-Rate Generators (BRG) 16

Timers 17

SDMA Channels and IDMA Emulation 18

Serial Communications Controllers (SCCs) 19

SCC UART Mode 20

SCC HDLC Mode 21

SCC BISYNC Mode 22

SCC Transparent Mode 23

SCC Ethernet Mode 24

SCC AppleTalk Mode 25

QMC (QUICC Multi-Channel Controller) 26

Universal Serial Bus Controller 27

Serial Management Controllers (SMCs) 28

Fast Communications Controllers (FCCs) 29

ATM Controller and AAL0, AAL1, and AAL5 Protocols 30

AAL2 Protocol 31

Fast Ethernet Controller 32

FCC HDLC Controller 33

FCC Transparent Controller 34

I Part I—Overview

1 Overview

2 G2_LE Core

3 Memory Map

II Part II—Configuration and Reset

4 System Interface Unit (SIU)

5 Reset

III Part III—The Hardware Interface

6 External Signals

7 60x Signals

8 The 60x Bus

9 PCI Bridge

10 PLL and Clock Generator

11 Memory Controller

12 IEEE 1149.1 Test Access Port

IV Part IV—Communications Processor Module

13 Communications Processor Module Overview

14 Serial Interface with Time-Slot Assigner

15 CPM Multiplexing

16 Baud-Rate Generators (BRG)

17 Timers

18 SDMA Channels and IDMA Emulation

19 Serial Communications Controllers (SCCs)

20 SCC UART Mode

21 SCC HDLC Mode

22 SCC BISYNC Mode

23 SCC Transparent Mode

24 SCC Ethernet Mode

25 SCC AppleTalk Mode

26 QMC (QUICC Multi-Channel Controller)

27 Universal Serial Bus Controller

28 Serial Management Controllers (SMCs)

29 Fast Communications Controllers (FCCs)

30 ATM Controller and AAL0, AAL1 and AAL5 Protocols

31 AAL2 Protocol

32 Fast Ethernet Controller

33 FCC HDLC Controller

.

34 FCC Transparent Controller

Serial Peripheral Interface (SPI) 35

I

2

C Controller 36

Parallel I/O Ports 37

Part V—Integrated Security Engine V

Security Engine 38

Register Quick Reference Guide A

Revision History B

Glossary of Terms and Abbreviations GLO

Index IND

35 Serial Peripheral Interface (SPI)

36 I

2

C Controller

37 Parallel I/O Ports

V Part V—Integrated Security Engine

38 Security Engine (SEC)

A Register Quick Reference Guide

B Revision History

GLO Glossary of Terms and Abbreviations

IND Index

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Contents

About This Book

Before Using This Manual—Important Note.............................................................. lxxvii

Audience......................................................................................................................lxxvii

Organization................................................................................................................lxxviii

Suggested Reading......................................................................................................... lxxx

Conventions .................................................................................................................. lxxxi

Acronyms and Abbreviations ......................................................................................lxxxii

PowerPC Architecture Terminology Conventions....................................................... lxxxv

Chapter 1

Overview

1.1 Features............................................................................................................................1-1

1.2 Architecture Overview..................................................................................................... 1-5

1.2.1 G2_LE Core.................................................................................................................1-6

1.2.2 System Interface Unit (SIU)........................................................................................ 1-7

1.2.3 Communications Processor Module (CPM)................................................................ 1-7

1.2.4 Security Engine (SEC)................................................................................................. 1-8

1.3 Software Compatibility.................................................................................................... 1-8

1.3.1 Signals..........................................................................................................................1-8

1.4 Differences Between the MPC860 and the MPC8272 ....................................................1-9

1.5 Serial Protocol Table...................................................................................................... 1-10

1.6 MPC8272 Configurations.............................................................................................. 1-11

1.6.1 Pin Configurations..................................................................................................... 1-11

1.6.2 Serial Performance..................................................................................................... 1-11

1.7 Application Examples.................................................................................................... 1-11

1.7.1 Examples of Communication Systems ...................................................................... 1-11

1.7.1.1 Small Office Router............................................................................................... 1-12

1.7.1.2 ADSL Small Office Router.................................................................................... 1-13

1.7.1.3 General-Purpose Controller................................................................................... 1-13

1.7.2 Bus Configurations .................................................................................................... 1-13

1.7.2.1 Basic System.......................................................................................................... 1-13

1.7.2.2 High-Performance Communication....................................................................... 1-14

1.7.2.3 High-Performance System Microprocessor........................................................... 1-15

1.7.2.4 MPC8272 as PCI Agent......................................................................................... 1-16

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Chapter 2

G2_LE Core

2.1 Overview.......................................................................................................................... 2-1

2.2 G2_LE Core Features ..................................................................................................... 2-3

2.2.1 Instruction Unit............................................................................................................2-5

2.2.2 Instruction Queue and Dispatch Unit........................................................................... 2-5

2.2.3 Branch Processing Unit (BPU).................................................................................... 2-6

2.2.4 Independent Execution Units....................................................................................... 2-6

2.2.4.1 Integer Unit (IU)...................................................................................................... 2-6

2.2.4.2 Floating-Point Unit (FPU)....................................................................................... 2-6

2.2.4.3 Load/Store Unit (LSU) ............................................................................................ 2-7

2.2.4.4 System Register Unit (SRU).................................................................................... 2-7

2.2.5 Completion Unit .......................................................................................................... 2-7

2.2.6 Memory Subsystem Support........................................................................................2-7

2.2.6.1 Memory Management Units (MMUs)..................................................................... 2-8

2.2.6.2 Cache Units..............................................................................................................2-8

2.3 Programming Model........................................................................................................ 2-8

2.3.1 Register Set.................................................................................................................. 2-8

2.3.1.1 PowerPC Register Set.............................................................................................. 2-9

2.3.1.2 MPC8272-Specific Registers................................................................................. 2-11

2.3.1.2.1 Hardware Implementation-Dependent Register 0 (HID0) ................................ 2-11

2.3.1.2.2 Hardware Implementation-Dependent Register 1 (HID1) ................................ 2-14

2.3.1.2.3 Hardware Implementation-Dependent Register 2 (HID2) ................................ 2-14

2.3.1.2.4 Processor Version Register (PVR)..................................................................... 2-15

2.3.2 PowerPC Instruction Set and Addressing Modes...................................................... 2-15

2.3.2.1 Calculating Effective Addresses............................................................................ 2-15

2.3.2.2 PowerPC Instruction Set........................................................................................ 2-16

2.3.2.3 MPC8272 Implementation-Specific Instruction Set..............................................2-17

2.4 Cache Implementation................................................................................................... 2-17

2.4.1 PowerPC Cache Model.............................................................................................. 2-18

2.4.2 MPC8272 Implementation-Specific Cache Implementation.....................................2-18

2.4.2.1 Data Cache............................................................................................................. 2-18

2.4.2.2 Instruction Cache................................................................................................... 2-20

2.4.2.3 Cache Locking....................................................................................................... 2-20

2.4.2.3.1 Entire Cache Locking........................................................................................ 2-20

2.4.2.3.2 Way Locking...................................................................................................... 2-20

2.5 Exception Model............................................................................................................ 2-21

2.5.1 PowerPC Exception Model........................................................................................ 2-21

2.5.2 Implementation-Specific Exception Model............................................................... 2-22

2.6 Memory Management.................................................................................................... 2-25

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2.6.1 PowerPC Memory Management................................................................................ 2-25

2.6.2 Implementation-Specific MMU Features.................................................................. 2-25

2.7 Instruction Timing.......................................................................................................... 2-26

2.8 Differences Between the MPC8272 G2_LE Embedded Core and the MPC603e......... 2-27

Chapter 3

Memory Map

3.1 Internal Memory Map...................................................................................................... 3-3

Chapter 4

System Interface Unit (SIU)

4.1 System Configuration and Protection.............................................................................. 4-2

4.1.1 Bus Monitor.................................................................................................................4-3

4.1.2 Timers Clock................................................................................................................4-4

4.1.3 Time Counter (TMCNT).............................................................................................. 4-4

4.1.4 Periodic Interrupt Timer (PIT)..................................................................................... 4-5

4.1.5 Software Watchdog Timer ........................................................................................... 4-6

4.2 Interrupt Controller.......................................................................................................... 4-7

4.2.1 Interrupt Configuration................................................................................................ 4-8

4.2.1.1 Machine Check Interrupt (MCP)............................................................................. 4-9

4.2.1.2 External Interrupt (INT) .......................................................................................... 4-9

4.2.1.3 Critical Interrupt (CINT) ......................................................................................... 4-9

4.2.1.4 External Interrupt Sources in Single MPC8272 Bus Mode...................................4-10

4.2.2 Interrupt Source Priorities..........................................................................................4-10

4.2.2.1 SCC and FCC Relative Priority............................................................................. 4-12

4.2.2.2 PIT, TMCNT, PCI, and IRQ Relative Priority ...................................................... 4-13

4.2.2.3 Highest Priority Interrupt....................................................................................... 4-13

4.2.3 Masking Interrupt Sources......................................................................................... 4-13

4.2.4 Interrupt Vector Generation and Calculation............................................................. 4-14

4.2.4.1 Port C External Interrupts...................................................................................... 4-16

4.3 Programming Model...................................................................................................... 4-17

4.3.1 Interrupt Controller Registers.................................................................................... 4-17

4.3.1.1 SIU Interrupt Configuration Register (SICR)........................................................ 4-17

4.3.1.2 SIU Interrupt Priority Register (SIPRR)................................................................ 4-18

4.3.1.3 CPM Interrupt Priority Registers (SCPRR_H and SCPRR_L).............................4-19

4.3.1.4 SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L) ................................ 4-21

4.3.1.5 SIU Interrupt Mask Registers (SIMR_H and SIMR_L)........................................4-22

4.3.1.6 SIU Interrupt Vector Register (SIVEC)................................................................. 4-24

4.3.1.7 SIU External Interrupt Control Register (SIEXR)................................................. 4-25

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4.3.2 System Configuration and Protection Registers........................................................4-26

4.3.2.1 Bus Configuration Register (BCR)........................................................................ 4-26

4.3.2.2 60x Bus Arbiter Configuration Register (PPC_ACR)...........................................4-29

4.3.2.3 60x Bus Arbitration-Level Registers (PPC_ALRH/PPC_ALRL).........................4-30

4.3.2.4 SIU Module Configuration Register (SIUMCR)...................................................4-31

4.3.2.5 Internal Memory Map Register (IMMR)............................................................... 4-33

4.3.2.6 System Protection Control Register (SYPCR)......................................................4-34

4.3.2.7 Software Service Register (SWSR)....................................................................... 4-35

4.3.2.8 60x Bus Transfer Error Status and Control Register 1 (TESCR1)........................4-36

4.3.2.9 60x Bus Transfer Error Status and Control Register 2 (TESCR2)........................4-37

4.3.2.10 Time Counter Status and Control Register (TMCNTSC)...................................... 4-38

4.3.2.11 Time Counter Register (TMCNT)......................................................................... 4-39

4.3.2.12 Time Counter Alarm Register (TMCNTAL).........................................................4-39

4.3.3 Periodic Interrupt Registers ....................................................................................... 4-40

4.3.3.1 Periodic Interrupt Status and Control Register (PISCR).......................................4-40

4.3.3.2 Periodic Interrupt Timer Count Register (PITC)...................................................4-40

4.3.3.3 Periodic Interrupt Timer Register (PITR).............................................................. 4-41

4.3.4 PCI Control Registers................................................................................................ 4-42

4.3.4.1 PCI Base Register (PCIBRx)................................................................................. 4-42

4.3.4.2 PCI Mask Register (PCIMSKx) ............................................................................ 4-43

4.4 SIU Pin Multiplexing..................................................................................................... 4-43

Chapter 5

Reset

5.1 Reset Causes .................................................................................................................... 5-1

5.1.1 Reset Actions...............................................................................................................5-2

5.1.2 Power-On Reset Flow.................................................................................................. 5-2

5.1.3 HRESET Flow............................................................................................................. 5-3

5.1.4 SRESET Flow..............................................................................................................5-3

5.2 Reset Status Register (RSR) ............................................................................................ 5-4

5.3 Reset Mode Register (RMR) ........................................................................................... 5-5

5.4 Reset Configuration.........................................................................................................5-6

5.4.1 Hard Reset Configuration Word .................................................................................. 5-7

5.4.2 Hard Reset Configuration Examples ........................................................................... 5-9

5.4.2.1 Single MPC8272 with Default Configuration.........................................................5-9

5.4.2.2 Single MPC8272 Configured from Boot EEPROM..............................................5-10

5.4.2.3 Multiple MPC8272s Configured from Boot EEPROM.........................................5-10

5.4.2.4 Multiple MPC8272s in a System with No EEPROM............................................5-12

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Chapter 6

External Signals

6.1 Functional Pinout.............................................................................................................6-1

6.2 Signal Descriptions..........................................................................................................6-2

Chapter 7

60x Signals

7.1 Signal Configuration........................................................................................................ 7-2

7.2 Signal Descriptions..........................................................................................................7-2

7.2.1 Address Bus Arbitration Signals.................................................................................. 7-3

7.2.1.1 Bus Request (BR)—Output..................................................................................... 7-3

7.2.1.1.1 Address Bus Request (BR

)—Output................................................................... 7-3

7.2.1.1.2 Address Bus Request (BR

)—Input...................................................................... 7-3

7.2.1.2 Bus Grant (BG)........................................................................................................ 7-4

7.2.1.2.1 Bus Grant (BG)—Input....................................................................................... 7-4

7.2.1.2.2 Bus Grant (BG)—Output..................................................................................... 7-4

7.2.1.3 Address Bus Busy (ABB)........................................................................................ 7-5

7.2.1.3.1 Address Bus Busy (ABB)—Output..................................................................... 7-5

7.2.1.3.2 Address Bus Busy (ABB)—Input ....................................................................... 7-5

7.2.2 Address Transfer Start Signal...................................................................................... 7-5

7.2.2.1 Transfer Start (TS)................................................................................................... 7-5

7.2.2.1.1 Transfer Start (TS)—Output................................................................................ 7-5

7.2.2.2 Transfer Start (TS)—Input....................................................................................... 7-6

7.2.3 Address Transfer Signals............................................................................................. 7-6

7.2.3.1 Address Bus (A[0:31])............................................................................................. 7-6

7.2.3.1.1 Address Bus (A[0:31])—Output ......................................................................... 7-6

7.2.3.1.2 Address Bus (A[0:31])—Input............................................................................7-6

7.2.4 Address Transfer Attribute Signals.............................................................................. 7-7

7.2.4.1 Transfer Type (TT[0:4])........................................................................................... 7-7

7.2.4.1.1 Transfer Type (TT[0:4])—Output ....................................................................... 7-7

7.2.4.1.2 Transfer Type (TT[0:4])—Input.......................................................................... 7-7

7.2.4.2 Transfer Size (TSIZ[0:3])........................................................................................ 7-7

7.2.4.3 Transfer Burst (TBST)............................................................................................. 7-8

7.2.4.4 Global (GBL)........................................................................................................... 7-8

7.2.4.4.1 Global (GBL)—Output........................................................................................ 7-8

7.2.4.4.2 Global (GBL)—Input..........................................................................................7-8

7.2.4.5 Caching-Inhibited (CI)—Output ............................................................................. 7-8

7.2.4.6 Write-Through (WT)—Output ................................................................................ 7-9

7.2.5 Address Transfer Termination Signals......................................................................... 7-9

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7.2.5.1 Address Acknowledge (AACK)..............................................................................7-9

7.2.5.1.1 Address Acknowledge (AACK)—Output...........................................................7-9

7.2.5.1.2 Address Acknowledge (AACK)—Input .............................................................7-9

7.2.5.2 Address Retry (ARTRY)........................................................................................ 7-10

7.2.5.2.1 Address Retry (ARTRY)—Output .................................................................... 7-10

7.2.5.2.2 Address Retry (ARTRY)—Input.......................................................................7-10

7.2.6 Data Bus Arbitration Signals..................................................................................... 7-11

7.2.6.1 Data Bus Grant (DBG) .......................................................................................... 7-11

7.2.6.1.1 Data Bus Grant (DBG)—Input.......................................................................... 7-11

7.2.6.1.2 Data Bus Grant (DBG)—Output....................................................................... 7-11

7.2.6.2 Data Bus Busy (DBB) ........................................................................................... 7-12

7.2.6.2.1 Data Bus Busy (DBB)—Output ........................................................................ 7-12

7.2.6.2.2 Data Bus Busy (DBB)—Input........................................................................... 7-12

7.2.7 Data Transfer Signals................................................................................................. 7-12

7.2.7.1 Data Bus (D[0:63])................................................................................................ 7-12

7.2.7.1.1 Data Bus (D[0:63])—Output............................................................................. 7-13

7.2.7.1.2 Data Bus (D[0:63])—Input................................................................................ 7-13

7.2.8 Data Transfer Termination Signals ............................................................................ 7-13

7.2.8.1 Transfer Acknowledge (TA)..................................................................................7-13

7.2.8.1.1 Transfer Acknowledge (TA)—Input ................................................................. 7-14

7.2.8.1.2 Transfer Acknowledge (TA)—Output............................................................... 7-14

7.2.8.2 Transfer Error Acknowledge (TEA)......................................................................7-14

7.2.8.2.1 Transfer Error Acknowledge (TEA)—Input .....................................................7-15

7.2.8.2.2 Transfer Error Acknowledge (TEA)—Output...................................................7-15

7.2.8.3 Partial Data Valid Indication (PSDVAL)............................................................... 7-15

7.2.8.3.1 Partial Data Valid (PSDVAL)—Input................................................................ 7-15

7.2.8.3.2 Partial Data Valid (PSDVAL)—Output............................................................. 7-16

Chapter 8

The 60x Bus

8.1 Terminology..................................................................................................................... 8-1

8.2 Bus Configuration............................................................................................................8-2

8.2.1 Single-MPC8272 Bus Mode........................................................................................8-2

8.2.2 60x-Compatible Bus Mode..........................................................................................8-3

8.3 60x Bus Protocol Overview............................................................................................. 8-4

8.3.1 Arbitration Phase ......................................................................................................... 8-5

8.3.2 Address Pipelining and Split-Bus Transactions...........................................................8-6

8.4 Address Tenure Operations.............................................................................................. 8-7

8.4.1 Address Arbitration...................................................................................................... 8-7

8.4.2 Address Pipelining....................................................................................................... 8-8

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8.4.3 Address Transfer Attribute Signals.............................................................................. 8-9

8.4.3.1 Transfer Type Signal (TT[0:4]) Encoding............................................................... 8-9

8.4.3.2 Transfer Code Signals TC[0:2].............................................................................. 8-12

8.4.3.3 TBST and TSIZ[0:3] Signals and Size of Transfer ...............................................8-12

8.4.3.4 Burst Ordering During Data Transfers .................................................................. 8-13

8.4.3.5 Effect of Alignment on Data Transfers.................................................................. 8-14

8.4.3.6 Effect of Port Size on Data Transfers .................................................................... 8-15

8.4.3.7 60x-Compatible Bus Mode—Size Calculation .....................................................8-17

8.4.3.8 Extended Transfer Mode ....................................................................................... 8-18

8.4.4 Address Transfer Termination ................................................................................... 8-21

8.4.4.1 Address Retried with ARTRY ............................................................................... 8-21

8.4.4.2 Address Tenure Timing Configuration.................................................................. 8-23

8.4.5 Pipeline Control......................................................................................................... 8-23

8.5 Data Tenure Operations ................................................................................................. 8-24

8.5.1 Data Bus Arbitration.................................................................................................. 8-24

8.5.2 Data Streaming Mode................................................................................................ 8-25

8.5.3 Data Bus Transfers and Normal Termination............................................................8-25

8.5.4 Effect of ARTRY Assertion on Data Transfer and Arbitration ................................. 8-26

8.5.5 Port Size Data Bus Transfers and PSDVAL Termination..........................................8-26

8.5.6 Data Bus Termination by Assertion of TEA.............................................................. 8-28

8.6 Memory Coherency—MEI Protocol ............................................................................. 8-29

8.7 Processor State Signals .................................................................................................. 8-30

8.7.1 Support for the lwarx/stwcx. Instruction Pair............................................................ 8-31

8.7.2 TLBISYNC Input ...................................................................................................... 8-31

8.8 Little-Endian Mode........................................................................................................8-31

Chapter 9

PCI Bridge

9.1 Signals..............................................................................................................................9-3

9.2 Clocking...........................................................................................................................9-3

9.3 PCI Bridge Initialization..................................................................................................9-3

9.4 SDMA Interface...............................................................................................................9-4

9.5 Interrupts from PCI Bridge.............................................................................................. 9-4

9.6 60x Bus Arbitration Priority ............................................................................................ 9-4

9.7 60x Bus Masters............................................................................................................... 9-5

9.8 CompactPCI Hot Swap Specification Support................................................................ 9-5

9.9 MPC8272 PCI Interface...................................................................................................9-5

9.9.1 PCI Interface Operation............................................................................................... 9-7

9.9.1.1 Bus Commands........................................................................................................ 9-7

9.9.1.2 PCI Protocol Fundamentals..................................................................................... 9-8

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9.9.1.2.1 Basic Transfer Control......................................................................................... 9-8

9.9.1.2.2 Addressing........................................................................................................... 9-8

9.9.1.2.3 Byte Enable Signals............................................................................................. 9-9

9.9.1.2.4 Bus Driving and Turnaround............................................................................... 9-9

9.9.1.3 Bus Transactions.................................................................................................... 9-10

9.9.1.3.1 Read and Write Transactions............................................................................. 9-10

9.9.1.3.2 Transaction Termination.................................................................................... 9-12

9.9.1.4 Other Bus Operations ............................................................................................ 9-14

9.9.1.4.1 Device Selection................................................................................................ 9-14

9.9.1.4.2 Fast Back-to-Back Transactions........................................................................ 9-15

9.9.1.4.3 Data Streaming .................................................................................................. 9-15

9.9.1.4.4 Host Mode Configuration Access...................................................................... 9-15

9.9.1.4.5 Agent Mode Configuration Access ................................................................... 9-17

9.9.1.4.6 Special Cycle Command ................................................................................... 9-17

9.9.1.4.7 Interrupt Acknowledge...................................................................................... 9-18

9.9.1.5 Error Functions...................................................................................................... 9-18

9.9.1.5.1 Parity..................................................................................................................9-18

9.9.1.5.2 Error Reporting.................................................................................................. 9-18

9.9.2 PCI Bus Arbitration................................................................................................... 9-20

9.9.2.1 Bus Parking............................................................................................................9-20

9.9.2.2 Arbitration Algorithm............................................................................................ 9-20

9.9.2.3 Master Latency Timer............................................................................................ 9-21

9.10 Address Map..................................................................................................................9-22

9.10.1 Address Map Programming.......................................................................................9-25

9.10.2 Address Translation ................................................................................................... 9-25

9.10.2.1 PCI Inbound Translation........................................................................................ 9-26

9.10.2.2 PCI Outbound Translation..................................................................................... 9-27

9.10.3 SIU Registers.............................................................................................................9-27

9.11 Configuration Registers ................................................................................................. 9-28

9.11.1 Memory-Mapped Configuration Registers................................................................ 9-28

9.11.1.1 Message Unit (I2O) Registers ............................................................................... 9-31

9.11.1.2 DMA Controller Registers..................................................................................... 9-31

9.11.1.3 PCI Outbound Translation Address Registers (POTARx) ....................................9-31

9.11.1.4 PCI Outbound Base Address Registers (POBARx) .............................................9-32

9.11.1.5 PCI Outbound Comparison Mask Registers (POCMRx) .....................................9-33

9.11.1.6 Discard Timer Control Register (PTCR) .............................................................. 9-34

9.11.1.7 General Purpose Control Register (GPCR) .......................................................... 9-34

9.11.1.8 PCI General Control Register (PCI_GCR) ...........................................................9-36

9.11.1.9 Error Status Register (ESR) .................................................................................. 9-36

9.11.1.10 Error Mask Register (EMR) ................................................................................. 9-38

9.11.1.11 Error Control Register (ECR) ............................................................................... 9-39

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9.11.1.12 PCI Error Address Capture Register (PCI_EACR) .............................................. 9-40

9.11.1.13 PCI Error Data Capture Register (PCI_EDCR) .................................................... 9-41

9.11.1.14 PCI Error Control Capture Register (PCI_ECCR) ...............................................9-41

9.11.1.15 PCI Inbound Translation Address Registers (PITARx) ........................................ 9-43

9.11.1.16 PCI Inbound Base Address Registers (PIBARx) ..................................................9-43

9.11.1.17 PCI Inbound Comparison Mask Registers (PICMRx) ........................................9-44

9.11.2 PCI Bridge Configuration Registers ........................................................................ 9-46

9.11.2.1 Vendor ID Register ............................................................................................... 9-47

9.11.2.2 Device ID Register ............................................................................................... 9-48

9.11.2.3 PCI Bus Command Register ................................................................................. 9-48

9.11.2.4 PCI Bus Status Register ........................................................................................ 9-49

9.11.2.5 Revision ID Register ............................................................................................. 9-51

9.11.2.6 PCI Bus Programming Interface Register ............................................................9-51

9.11.2.7 Subclass Code Register ......................................................................................... 9-52

9.11.2.8 PCI Bus Base Class Code Register ....................................................................... 9-52

9.11.2.9 PCI Bus Cache Line Size Register ....................................................................... 9-53

9.11.2.10 PCI Bus Latency Timer Register .......................................................................... 9-53

9.11.2.11 Header Type Register ........................................................................................... 9-54

9.11.2.12 BIST Control Register .......................................................................................... 9-54

9.11.2.13 PCI Bus Internal Memory-Mapped Registers Base Address

Register (PIMMRBAR) .................................................................................... 9-54

9.11.2.14 General-Purpose Local Access Base Address Registers (GPLABARx) .............. 9-55

9.11.2.15 Subsystem Vendor ID Register ............................................................................. 9-56

9.11.2.16 Subsystem Device ID Register ............................................................................. 9-57

9.11.2.17 PCI Bus Capabilities Pointer Register ..................................................................9-57

9.11.2.18 PCI Bus Interrupt Line Register ........................................................................... 9-58

9.11.2.19 PCI Bus Interrupt Pin Register ............................................................................. 9-58

9.11.2.20 PCI Bus MIN GNT ............................................................................................... 9-59

9.11.2.21 PCI Bus MAX LAT .............................................................................................. 9-59

9.11.2.22 PCI Bus Function Register ................................................................................... 9-60

9.11.2.23 PCI Bus Arbiter Configuration Register ............................................................... 9-61

9.11.2.24 PCI Hot Swap Register Block .............................................................................. 9-61

9.11.2.25 PCI Hot Swap Control Status Register ................................................................. 9-62

9.11.2.26 PCI Configuration Register Access from the Core ...............................................9-63

9.11.2.27 PCI Configuration Register Access in Big-Endian Mode .................................... 9-63

9.11.2.27.1 Additional Information on Endianness .............................................................9-64

9.11.2.27.2 Notes on GPCR[LE_MODE] ........................................................................... 9-64

9.11.2.28 Initializing the PCI Configuration Registers ........................................................9-65

9.12 Message Unit (I2O) ...................................................................................................... 9-67

9.12.1 Message Registers...................................................................................................... 9-67

9.12.1.1 Inbound Message Registers (IMRx) ..................................................................... 9-68

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9.12.1.2 Outbound Message Registers (OMRx) .................................................................9-69

9.12.2 Door Bell Registers ................................................................................................... 9-69

9.12.2.1 Outbound Doorbell Register (ODR) ..................................................................... 9-70

9.12.2.2 Inbound Doorbell Register (IDR) ......................................................................... 9-70

9.12.3 I

2

O Unit ....................................................................................................................9-71

9.12.3.1 PCI Configuration Identification .......................................................................... 9-72

9.12.3.2 Inbound FIFOs ...................................................................................................... 9-72

9.12.3.2.1 Inbound Free_FIFO Head Pointer Register (IFHPR) and Inbound

Free_FIFO Tail Pointer Register (IFTPR) .................................................... 9-73

9.12.3.2.2 Inbound Post_FIFO Head Pointer Register (IPHPR) and Inbound

Post_FIFO Tail Pointer Register (IPTPR) .................................................... 9-74

9.12.3.3 Outbound FIFOs ................................................................................................... 9-76

9.12.3.3.1 Outbound Free_FIFO Head Pointer Register (OFHPR) and Outbound

Free_FIFO Tail Pointer Register (OFTPR) .................................................. 9-76

9.12.3.3.2 Outbound Post_FIFO Head Pointer Register (OPHPR) and Outbound

Post_FIFO Tail Pointer Register (OPTPR) ...................................................9-77

9.12.3.4 I2O Registers ........................................................................................................ 9-79

9.12.3.4.1 Inbound FIFO Queue Port Register (IFQPR) ...................................................9-79

9.12.3.4.2 Outbound FIFO Queue Port Register (OFQPR) ...............................................9-80

9.12.3.4.3 Outbound Message Interrupt Status Register (OMISR) ...................................9-80

9.12.3.4.4 Outbound Message Interrupt Mask Register (OMIMR) ..................................9-81

9.12.3.4.5 Inbound Message Interrupt Status Register (IMISR) .......................................9-82

9.12.3.4.6 Inbound Message Interrupt Mask Register (IMIMR) .......................................9-84

9.12.3.4.7 Messaging Unit Control Register (MUCR) ...................................................... 9-85

9.12.3.4.8 Queue Base Address Register (QBAR) ............................................................ 9-86

9.13 DMA Controller............................................................................................................. 9-87

9.13.1 DMA Operation......................................................................................................... 9-87

9.13.1.1 DMA Direct Mode................................................................................................. 9-88

9.13.1.2 DMA Chaining Mode............................................................................................ 9-88

9.13.1.3 DMA Coherency.................................................................................................... 9-89

9.13.1.4 Halt and Error Conditions...................................................................................... 9-89

9.13.1.5 DMA Transfer Types............................................................................................. 9-89

9.13.1.6 DMA Registers...................................................................................................... 9-90

9.13.1.6.1 DMA Mode Register [0–3] (DMAMRx) .........................................................9-90

9.13.1.6.2 DMA Status Register [0–3] (DMASRx) .......................................................... 9-92

9.13.1.6.3 DMA Current Descriptor Address Register [0–3] (DMACDARx) .................. 9-93

9.13.1.6.4 DMA Source Address Registers [0–3] (DMASARx) ...................................... 9-94

9.13.1.6.5 DMA Destination Address Register [0–3] (DMADARx) ................................ 9-95

9.13.1.6.6 DMA Byte Count Register [0–3] (DMABCRx) ...............................................9-95

9.13.1.6.7 DMA Next Descriptor Address Registers [0–3] (DMANDARx) ....................9-96

9.13.2 DMA Segment Descriptors........................................................................................ 9-97

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9.13.2.1 Descriptor in Big-Endian Mode............................................................................. 9-98

9.13.2.2 Descriptor in Little-Endian Mode.......................................................................... 9-99

9.14 Error Handling ............................................................................................................... 9-99

9.14.1 Interrupt and Error Signals ........................................................................................ 9-99

9.14.1.1 PCI Bus Error Signals............................................................................................ 9-99

9.14.1.1.1 System Error (SERR) ...................................................................................... 9-100

9.14.1.1.2 Parity Error (PERR)......................................................................................... 9-100

9.14.1.1.3 Error Reporting................................................................................................ 9-100

9.14.1.2 Illegal Register Access Error............................................................................... 9-100

9.14.1.3 PCI Interface........................................................................................................ 9-100

9.14.1.3.1 Address Parity Error........................................................................................ 9-101

9.14.1.3.2 Data Parity Error.............................................................................................. 9-101

9.14.1.3.3 Master-Abort Transaction Termination ........................................................... 9-101

9.14.1.3.4 Target-Abort Error........................................................................................... 9-102

9.14.1.3.5 NMI ................................................................................................................. 9-102

9.14.1.4 Embedded Utilities ..............................................................................................9-102

9.14.1.4.1 Outbound Free Queue Overflow .....................................................................9-102

9.14.1.4.2 Inbound Post Queue Overflow........................................................................ 9-102

9.14.1.4.3 Inbound DoorBell Machine Check..................................................................9-102

Chapter 10

PLL and Clock Generator

10.1 MPC8272 Clock Block Diagram................................................................................... 10-1

10.1.1 Main PLL................................................................................................................... 10-1

10.1.2 Core PLL....................................................................................................................10-1

10.1.3 Skew Elimination....................................................................................................... 10-2

10.1.4 Dividers......................................................................................................................10-2

10.1.5 Internal Clock Signals................................................................................................ 10-2

10.1.6 PCI Bridge as an Agent Operating from the PCI System Clock ............................... 10-4

10.1.7 PCI Bridge as a Host Generating the PCI System Clock ..........................................10-4

10.2 External Clock Inputs .................................................................................................... 10-5

10.3 PLL Pins ....................................................................................................................... 10-5

10.4 System Clock Control Register (SCCR)........................................................................ 10-6

10.5 System Clock Mode Register (SCMR).......................................................................... 10-7

10.5.1 SCMR[CORECNF] Definitions................................................................................ 10-8

10.6 Clock Configuration Modes........................................................................................... 10-9

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Chapter 11

Memory Controller

11.1 Features.......................................................................................................................... 11-2

11.2 Basic Architecture.......................................................................................................... 11-3

11.2.1 Address and Address Space Checking....................................................................... 11-6

11.2.2 Page Hit Checking..................................................................................................... 11-6

11.2.3 Transfer Error Acknowledge (TEA) Generation....................................................... 11-7

11.2.4 Data Buffer Controls (BCTLx).................................................................................. 11-7

11.2.5 Atomic Bus Operation ............................................................................................... 11-7

11.2.6 Data Pipelining .......................................................................................................... 11-7

11.2.7 External Memory Controller Support........................................................................ 11-8

11.2.8 Data Buffer Control Signals (BCTL1 and BCLT2)................................................... 11-8

11.2.9 External Address Latch Enable Signal (ALE)........................................................... 11-8

11.2.10 Partial Data Valid Indication (PSDVAL)................................................................... 11-9

11.2.11 BADDR[27:31] Signal Connections ....................................................................... 11-10

11.3 Register Descriptions................................................................................................... 11-10

11.3.1 Base Registers (BRx)................................................................................................11-11

11.3.2 Option Registers (ORx)........................................................................................... 11-13

11.3.3 60x SDRAM Mode Register (PSDMR) .................................................................. 11-18

11.3.4 Machine A/B/C Mode Registers (MxMR) .............................................................. 11-21

11.3.5 Memory Data Register (MDR)................................................................................ 11-23

11.3.6 Memory Address Register (MAR) .......................................................................... 11-24

11.3.7 60x Bus-Assigned UPM Refresh Timer (PURT)..................................................... 11-25

11.3.8 60x Bus-Assigned SDRAM Refresh Timer (PSRT)................................................ 11-25

11.3.9 Memory Refresh Timer Prescaler Register (MPTPR)............................................. 11-26

11.3.10 60x Bus Error Status and Control Registers (TESCRx).......................................... 11-26

11.4 SDRAM Machine ........................................................................................................ 11-26

11.4.1 Supported SDRAM Configurations......................................................................... 11-29

11.4.2 SDRAM Power-On Initialization ............................................................................ 11-29

11.4.3 JEDEC-Standard SDRAM Interface Commands .................................................... 11-29

11.4.4 Page-Mode Support and Pipeline Accesses............................................................. 11-30

11.4.5 Bank Interleaving .................................................................................................... 11-30

11.4.5.1 Using BNKSEL Signals in Single-MPC8272 Bus Mode.................................... 11-31

11.4.5.2 SDRAM Address Multiplexing (SDAM and BSMA)......................................... 11-31

11.4.6 SDRAM Device-Specific Parameters...................................................................... 11-32

11.4.6.1 Precharge-to-Activate Interval............................................................................. 11-32

11.4.6.2 Activate to Read/Write Interval........................................................................... 11-33

11.4.6.3 Column Address to First Data Out—CAS Latency............................................. 11-34

11.4.6.4 Last Data Out to Precharge.................................................................................. 11-34

11.4.6.5 Last Data In to Precharge—Write Recovery....................................................... 11-35

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11.4.6.6 Refresh Recovery Interval (RFRC) ..................................................................... 11-35

11.4.6.7 External Address Multiplexing Signal................................................................. 11-36

11.4.6.8 External Address and Command Buffers (BUFCMD)........................................ 11-36

11.4.7 SDRAM Interface Timing ....................................................................................... 11-37

11.4.8 SDRAM Read/Write Transactions........................................................................... 11-40

11.4.9 SDRAM Mode-Set Command Timing.................................................................... 11-40

11.4.10 SDRAM Refresh...................................................................................................... 11-41

11.4.11 SDRAM Refresh Timing ......................................................................................... 11-42

11.4.12 SDRAM Configuration Examples........................................................................... 11-42

11.4.12.1 SDRAM Configuration Example (Page-Based Interleaving).............................. 11-42

11.4.13 SDRAM Configuration Example (Bank-Based Interleaving)................................. 11-44

11.5 General-Purpose Chip-Select Machine (GPCM).........................................................11-45

11.5.1 Timing Configuration .............................................................................................. 11-46

11.5.1.1 Chip-Select Assertion Timing ............................................................................. 11-47

11.5.1.2 Chip-Select and Write Enable Deassertion Timing............................................. 11-48

11.5.1.3 Relaxed Timing.................................................................................................... 11-49

11.5.1.4 Output Enable (OE) Timing ................................................................................ 11-51

11.5.1.5 Programmable Wait State Configuration............................................................. 11-52

11.5.1.6 Extended Hold Time on Read Accesses.............................................................. 11-52

11.5.2 External Access Termination................................................................................... 11-54

11.5.3 Boot Chip-Select Operation..................................................................................... 11-55

11.5.4 Differences between MPC8xx’s GPCM and MPC82xx’s GPCM........................... 11-56

11.6 User-Programmable Machines (UPMs)....................................................................... 11-56

11.6.1 Requests................................................................................................................... 11-57

11.6.1.1 Memory Access Requests.................................................................................... 11-58

11.6.1.2 UPM Refresh Timer Requests ............................................................................. 11-59

11.6.1.3 Software Requests—run Command .................................................................... 11-59

11.6.1.4 Exception Requests.............................................................................................. 11-60

11.6.2 Programming the UPMs .......................................................................................... 11-60

11.6.3 Clock Timing........................................................................................................... 11-60

11.6.4 The RAM Array....................................................................................................... 11-62

11.6.4.1 RAM Words......................................................................................................... 11-63

11.6.4.1.1 Chip-Select Signals (CxTx)............................................................................. 11-67

11.6.4.1.2 Byte-Select Signals (BxTx)............................................................................. 11-68

11.6.4.1.3 General-Purpose Signals (GxTx, GOx)........................................................... 11-69

11.6.4.1.4 Loop Control.................................................................................................... 11-69

11.6.4.1.5 Repeat Execution of Current RAM Word (REDO) ........................................ 11-69

11.6.4.2 Address Multiplexing .......................................................................................... 11-70

11.6.4.3 Data Valid and Data Sample Control................................................................... 11-70

11.6.4.4 Signals Negation.................................................................................................. 11-71

11.6.4.5 The Wait Mechanism........................................................................................... 11-71

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11.6.4.6 Extended Hold Time on Read Accesses ............................................................. 11-72

11.6.5 UPM DRAM Configuration Example..................................................................... 11-72

11.6.6 Differences between MPC8xx UPM and MPC82xx UPM ..................................... 11-73

11.7 Memory System Interface Example Using UPM........................................................ 11-74

11.7.0.1 EDO Interface Example....................................................................................... 11-84

11.8 Handling Devices with Slow or Variable Access Times.............................................. 11-93

11.8.1 Slow Devices Example............................................................................................ 11-93

11.9 External Master Support (60x-Compatible Mode)...................................................... 11-93

11.9.1 60x-Compatible External Masters (non-MPC8272)................................................ 11-93

11.9.2 MPC8272 External Masters..................................................................................... 11-94

11.9.3 Extended Controls in 60x-Compatible Mode.......................................................... 11-94

11.9.4 Address Incrementing for External Bursting Masters ............................................. 11-94

11.9.5 External Masters Timing.......................................................................................... 11-94

11.9.5.1 Example of External Master Using the SDRAM Machine ................................. 11-96

Chapter 12

IEEE 1149.1 Test Access Port

12.1 Overview........................................................................................................................12-1

12.2 TAP Controller...............................................................................................................12-2

12.3 Boundary Scan Register................................................................................................. 12-3

12.4 Instruction Register........................................................................................................ 12-5

12.5 MPC8272 Restrictions...................................................................................................12-7

12.6 Nonscan Chain Operation.............................................................................................. 12-7

Chapter 13

Communications Processor Module Overview

13.1 Features..........................................................................................................................13-1

13.2 MPC8272 Serial Configurations....................................................................................13-3

13.3 Communications Processor (CP)................................................................................... 13-4

13.3.1 Features......................................................................................................................13-4

13.3.2 CP Block Diagram..................................................................................................... 13-4

13.3.3 G2_LE Core Interface................................................................................................ 13-6

13.3.4 Peripheral Interface.................................................................................................... 13-6

13.3.5 Execution from RAM ................................................................................................ 13-7

13.3.6 RISC Controller Configuration Register (RCCR).....................................................13-7

13.3.7 RISC Time-Stamp Control Register (RTSCR).......................................................... 13-9

13.3.8 RISC Time-Stamp Register (RTSR)........................................................................ 13-10

13.3.9 RISC Microcode Revision Number......................................................................... 13-10

13.4 Command Set............................................................................................................... 13-11

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