NXP MPC8247 Reference guide

Type
Reference guide

This manual is also suitable for

MPC8272 PowerQUICC II™
Family Reference Manual
Supports
MPC8272
MPC8271
MPC8248
MPC8247
MPC8272RM
Rev. 2, 10/2005
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. The described
product contains a PowerPC processor core. The PowerPC name is a trademark of IBM Corp. and
used under license. All other product or service names are the property of their respective owners.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Document Number: MPC8272RM
Rev. 2, 10/2005
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters which may be
provided in Freescale Semiconductor data sheets and/or specifications can and do
vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
Semiconductor was negligent regarding the design or manufacture of the part.
How to Reach Us:
Home Page:
www.freescale.com
email:
support@freescale.com
USA/Europe or Locations Not Listed:
Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
(800) 521-6274
480-768-2130
support@freescale.com
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
support@freescale.com
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku
Tokyo 153-0064, Japan
0120 191014
+81 2666 8080
support.japan@freescale.com
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Tai Po Industrial Estate,
Tai Po, N.T., Hong Kong
+800 2666 8080
support.asia@freescale.com
For Literature Requests Only:
Freescale Semiconductor
Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
(800) 441-2447
303-675-2140
Fax: 303-675-2150
LDCForFreescaleSemiconductor
@hibbertgroup.com
Part I—Overview I
Overview 1
G2_LE Core 2
Memory Map 3
Part II—Configuration and Reset II
System Interface Unit (SIU) 4
Reset 5
Part III—The Hardware Interface III
External Signals 6
60x Signals 7
The 60x Bus 8
PCI Bridge 9
PLL and Clock Generator 10
Memory Controller 11
IEEE 1149.1 Test Access Port 12
Part IV—Communications Processor Module IV
Communications Processor Module Overview 13
Serial Interface with Time-Slot Assigner 14
CPM Multiplexing 15
Baud-Rate Generators (BRG) 16
Timers 17
SDMA Channels and IDMA Emulation 18
Serial Communications Controllers (SCCs) 19
SCC UART Mode 20
SCC HDLC Mode 21
SCC BISYNC Mode 22
SCC Transparent Mode 23
SCC Ethernet Mode 24
SCC AppleTalk Mode 25
QMC (QUICC Multi-Channel Controller) 26
Universal Serial Bus Controller 27
Serial Management Controllers (SMCs) 28
Fast Communications Controllers (FCCs) 29
ATM Controller and AAL0, AAL1, and AAL5 Protocols 30
AAL2 Protocol 31
Fast Ethernet Controller 32
FCC HDLC Controller 33
FCC Transparent Controller 34
I Part I—Overview
1 Overview
2 G2_LE Core
3 Memory Map
II Part II—Configuration and Reset
4 System Interface Unit (SIU)
5 Reset
III Part III—The Hardware Interface
6 External Signals
7 60x Signals
8 The 60x Bus
9 PCI Bridge
10 PLL and Clock Generator
11 Memory Controller
12 IEEE 1149.1 Test Access Port
IV Part IV—Communications Processor Module
13 Communications Processor Module Overview
14 Serial Interface with Time-Slot Assigner
15 CPM Multiplexing
16 Baud-Rate Generators (BRG)
17 Timers
18 SDMA Channels and IDMA Emulation
19 Serial Communications Controllers (SCCs)
20 SCC UART Mode
21 SCC HDLC Mode
22 SCC BISYNC Mode
23 SCC Transparent Mode
24 SCC Ethernet Mode
25 SCC AppleTalk Mode
26 QMC (QUICC Multi-Channel Controller)
27 Universal Serial Bus Controller
28 Serial Management Controllers (SMCs)
29 Fast Communications Controllers (FCCs)
30 ATM Controller and AAL0, AAL1 and AAL5 Protocols
31 AAL2 Protocol
32 Fast Ethernet Controller
33 FCC HDLC Controller
.
34 FCC Transparent Controller
Serial Peripheral Interface (SPI) 35
I
2
C Controller 36
Parallel I/O Ports 37
Part V—Integrated Security Engine V
Security Engine 38
Register Quick Reference Guide A
Revision History B
Glossary of Terms and Abbreviations GLO
Index IND
35 Serial Peripheral Interface (SPI)
36 I
2
C Controller
37 Parallel I/O Ports
V Part V—Integrated Security Engine
38 Security Engine (SEC)
A Register Quick Reference Guide
B Revision History
GLO Glossary of Terms and Abbreviations
IND Index
MPC8272 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor vii
Contents
Paragraph
Number Title
Page
Number
Contents
About This Book
Before Using This Manual—Important Note.............................................................. lxxvii
Audience......................................................................................................................lxxvii
Organization................................................................................................................lxxviii
Suggested Reading......................................................................................................... lxxx
Conventions .................................................................................................................. lxxxi
Acronyms and Abbreviations ......................................................................................lxxxii
PowerPC Architecture Terminology Conventions....................................................... lxxxv
Chapter 1
Overview
1.1 Features............................................................................................................................1-1
1.2 Architecture Overview..................................................................................................... 1-5
1.2.1 G2_LE Core.................................................................................................................1-6
1.2.2 System Interface Unit (SIU)........................................................................................ 1-7
1.2.3 Communications Processor Module (CPM)................................................................ 1-7
1.2.4 Security Engine (SEC)................................................................................................. 1-8
1.3 Software Compatibility.................................................................................................... 1-8
1.3.1 Signals..........................................................................................................................1-8
1.4 Differences Between the MPC860 and the MPC8272 ....................................................1-9
1.5 Serial Protocol Table...................................................................................................... 1-10
1.6 MPC8272 Configurations.............................................................................................. 1-11
1.6.1 Pin Configurations..................................................................................................... 1-11
1.6.2 Serial Performance..................................................................................................... 1-11
1.7 Application Examples.................................................................................................... 1-11
1.7.1 Examples of Communication Systems ...................................................................... 1-11
1.7.1.1 Small Office Router............................................................................................... 1-12
1.7.1.2 ADSL Small Office Router.................................................................................... 1-13
1.7.1.3 General-Purpose Controller................................................................................... 1-13
1.7.2 Bus Configurations .................................................................................................... 1-13
1.7.2.1 Basic System.......................................................................................................... 1-13
1.7.2.2 High-Performance Communication....................................................................... 1-14
1.7.2.3 High-Performance System Microprocessor........................................................... 1-15
1.7.2.4 MPC8272 as PCI Agent......................................................................................... 1-16
MPC8272 PowerQUICC II Family Reference Manual, Rev. 2
viii Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
Chapter 2
G2_LE Core
2.1 Overview.......................................................................................................................... 2-1
2.2 G2_LE Core Features ..................................................................................................... 2-3
2.2.1 Instruction Unit............................................................................................................2-5
2.2.2 Instruction Queue and Dispatch Unit........................................................................... 2-5
2.2.3 Branch Processing Unit (BPU).................................................................................... 2-6
2.2.4 Independent Execution Units....................................................................................... 2-6
2.2.4.1 Integer Unit (IU)...................................................................................................... 2-6
2.2.4.2 Floating-Point Unit (FPU)....................................................................................... 2-6
2.2.4.3 Load/Store Unit (LSU) ............................................................................................ 2-7
2.2.4.4 System Register Unit (SRU).................................................................................... 2-7
2.2.5 Completion Unit .......................................................................................................... 2-7
2.2.6 Memory Subsystem Support........................................................................................2-7
2.2.6.1 Memory Management Units (MMUs)..................................................................... 2-8
2.2.6.2 Cache Units..............................................................................................................2-8
2.3 Programming Model........................................................................................................ 2-8
2.3.1 Register Set.................................................................................................................. 2-8
2.3.1.1 PowerPC Register Set.............................................................................................. 2-9
2.3.1.2 MPC8272-Specific Registers................................................................................. 2-11
2.3.1.2.1 Hardware Implementation-Dependent Register 0 (HID0) ................................ 2-11
2.3.1.2.2 Hardware Implementation-Dependent Register 1 (HID1) ................................ 2-14
2.3.1.2.3 Hardware Implementation-Dependent Register 2 (HID2) ................................ 2-14
2.3.1.2.4 Processor Version Register (PVR)..................................................................... 2-15
2.3.2 PowerPC Instruction Set and Addressing Modes...................................................... 2-15
2.3.2.1 Calculating Effective Addresses............................................................................ 2-15
2.3.2.2 PowerPC Instruction Set........................................................................................ 2-16
2.3.2.3 MPC8272 Implementation-Specific Instruction Set..............................................2-17
2.4 Cache Implementation................................................................................................... 2-17
2.4.1 PowerPC Cache Model.............................................................................................. 2-18
2.4.2 MPC8272 Implementation-Specific Cache Implementation.....................................2-18
2.4.2.1 Data Cache............................................................................................................. 2-18
2.4.2.2 Instruction Cache................................................................................................... 2-20
2.4.2.3 Cache Locking....................................................................................................... 2-20
2.4.2.3.1 Entire Cache Locking........................................................................................ 2-20
2.4.2.3.2 Way Locking...................................................................................................... 2-20
2.5 Exception Model............................................................................................................ 2-21
2.5.1 PowerPC Exception Model........................................................................................ 2-21
2.5.2 Implementation-Specific Exception Model............................................................... 2-22
2.6 Memory Management.................................................................................................... 2-25
MPC8272 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor ix
Contents
Paragraph
Number Title
Page
Number
2.6.1 PowerPC Memory Management................................................................................ 2-25
2.6.2 Implementation-Specific MMU Features.................................................................. 2-25
2.7 Instruction Timing.......................................................................................................... 2-26
2.8 Differences Between the MPC8272 G2_LE Embedded Core and the MPC603e......... 2-27
Chapter 3
Memory Map
3.1 Internal Memory Map...................................................................................................... 3-3
Chapter 4
System Interface Unit (SIU)
4.1 System Configuration and Protection.............................................................................. 4-2
4.1.1 Bus Monitor.................................................................................................................4-3
4.1.2 Timers Clock................................................................................................................4-4
4.1.3 Time Counter (TMCNT).............................................................................................. 4-4
4.1.4 Periodic Interrupt Timer (PIT)..................................................................................... 4-5
4.1.5 Software Watchdog Timer ........................................................................................... 4-6
4.2 Interrupt Controller.......................................................................................................... 4-7
4.2.1 Interrupt Configuration................................................................................................ 4-8
4.2.1.1 Machine Check Interrupt (MCP)............................................................................. 4-9
4.2.1.2 External Interrupt (INT) .......................................................................................... 4-9
4.2.1.3 Critical Interrupt (CINT) ......................................................................................... 4-9
4.2.1.4 External Interrupt Sources in Single MPC8272 Bus Mode...................................4-10
4.2.2 Interrupt Source Priorities..........................................................................................4-10
4.2.2.1 SCC and FCC Relative Priority............................................................................. 4-12
4.2.2.2 PIT, TMCNT, PCI, and IRQ Relative Priority ...................................................... 4-13
4.2.2.3 Highest Priority Interrupt....................................................................................... 4-13
4.2.3 Masking Interrupt Sources......................................................................................... 4-13
4.2.4 Interrupt Vector Generation and Calculation............................................................. 4-14
4.2.4.1 Port C External Interrupts...................................................................................... 4-16
4.3 Programming Model...................................................................................................... 4-17
4.3.1 Interrupt Controller Registers.................................................................................... 4-17
4.3.1.1 SIU Interrupt Configuration Register (SICR)........................................................ 4-17
4.3.1.2 SIU Interrupt Priority Register (SIPRR)................................................................ 4-18
4.3.1.3 CPM Interrupt Priority Registers (SCPRR_H and SCPRR_L).............................4-19
4.3.1.4 SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L) ................................ 4-21
4.3.1.5 SIU Interrupt Mask Registers (SIMR_H and SIMR_L)........................................4-22
4.3.1.6 SIU Interrupt Vector Register (SIVEC)................................................................. 4-24
4.3.1.7 SIU External Interrupt Control Register (SIEXR)................................................. 4-25
MPC8272 PowerQUICC II Family Reference Manual, Rev. 2
x Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
4.3.2 System Configuration and Protection Registers........................................................4-26
4.3.2.1 Bus Configuration Register (BCR)........................................................................ 4-26
4.3.2.2 60x Bus Arbiter Configuration Register (PPC_ACR)...........................................4-29
4.3.2.3 60x Bus Arbitration-Level Registers (PPC_ALRH/PPC_ALRL).........................4-30
4.3.2.4 SIU Module Configuration Register (SIUMCR)...................................................4-31
4.3.2.5 Internal Memory Map Register (IMMR)............................................................... 4-33
4.3.2.6 System Protection Control Register (SYPCR)......................................................4-34
4.3.2.7 Software Service Register (SWSR)....................................................................... 4-35
4.3.2.8 60x Bus Transfer Error Status and Control Register 1 (TESCR1)........................4-36
4.3.2.9 60x Bus Transfer Error Status and Control Register 2 (TESCR2)........................4-37
4.3.2.10 Time Counter Status and Control Register (TMCNTSC)...................................... 4-38
4.3.2.11 Time Counter Register (TMCNT)......................................................................... 4-39
4.3.2.12 Time Counter Alarm Register (TMCNTAL).........................................................4-39
4.3.3 Periodic Interrupt Registers ....................................................................................... 4-40
4.3.3.1 Periodic Interrupt Status and Control Register (PISCR).......................................4-40
4.3.3.2 Periodic Interrupt Timer Count Register (PITC)...................................................4-40
4.3.3.3 Periodic Interrupt Timer Register (PITR).............................................................. 4-41
4.3.4 PCI Control Registers................................................................................................ 4-42
4.3.4.1 PCI Base Register (PCIBRx)................................................................................. 4-42
4.3.4.2 PCI Mask Register (PCIMSKx) ............................................................................ 4-43
4.4 SIU Pin Multiplexing..................................................................................................... 4-43
Chapter 5
Reset
5.1 Reset Causes .................................................................................................................... 5-1
5.1.1 Reset Actions...............................................................................................................5-2
5.1.2 Power-On Reset Flow.................................................................................................. 5-2
5.1.3 HRESET Flow............................................................................................................. 5-3
5.1.4 SRESET Flow..............................................................................................................5-3
5.2 Reset Status Register (RSR) ............................................................................................ 5-4
5.3 Reset Mode Register (RMR) ........................................................................................... 5-5
5.4 Reset Configuration.........................................................................................................5-6
5.4.1 Hard Reset Configuration Word .................................................................................. 5-7
5.4.2 Hard Reset Configuration Examples ........................................................................... 5-9
5.4.2.1 Single MPC8272 with Default Configuration.........................................................5-9
5.4.2.2 Single MPC8272 Configured from Boot EEPROM..............................................5-10
5.4.2.3 Multiple MPC8272s Configured from Boot EEPROM.........................................5-10
5.4.2.4 Multiple MPC8272s in a System with No EEPROM............................................5-12
MPC8272 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor xi
Contents
Paragraph
Number Title
Page
Number
Chapter 6
External Signals
6.1 Functional Pinout.............................................................................................................6-1
6.2 Signal Descriptions..........................................................................................................6-2
Chapter 7
60x Signals
7.1 Signal Configuration........................................................................................................ 7-2
7.2 Signal Descriptions..........................................................................................................7-2
7.2.1 Address Bus Arbitration Signals.................................................................................. 7-3
7.2.1.1 Bus Request (BR)—Output..................................................................................... 7-3
7.2.1.1.1 Address Bus Request (BR
)—Output................................................................... 7-3
7.2.1.1.2 Address Bus Request (BR
)—Input...................................................................... 7-3
7.2.1.2 Bus Grant (BG)........................................................................................................ 7-4
7.2.1.2.1 Bus Grant (BG)—Input....................................................................................... 7-4
7.2.1.2.2 Bus Grant (BG)—Output..................................................................................... 7-4
7.2.1.3 Address Bus Busy (ABB)........................................................................................ 7-5
7.2.1.3.1 Address Bus Busy (ABB)—Output..................................................................... 7-5
7.2.1.3.2 Address Bus Busy (ABB)—Input ....................................................................... 7-5
7.2.2 Address Transfer Start Signal...................................................................................... 7-5
7.2.2.1 Transfer Start (TS)................................................................................................... 7-5
7.2.2.1.1 Transfer Start (TS)—Output................................................................................ 7-5
7.2.2.2 Transfer Start (TS)—Input....................................................................................... 7-6
7.2.3 Address Transfer Signals............................................................................................. 7-6
7.2.3.1 Address Bus (A[0:31])............................................................................................. 7-6
7.2.3.1.1 Address Bus (A[0:31])—Output ......................................................................... 7-6
7.2.3.1.2 Address Bus (A[0:31])—Input............................................................................7-6
7.2.4 Address Transfer Attribute Signals.............................................................................. 7-7
7.2.4.1 Transfer Type (TT[0:4])........................................................................................... 7-7
7.2.4.1.1 Transfer Type (TT[0:4])—Output ....................................................................... 7-7
7.2.4.1.2 Transfer Type (TT[0:4])—Input.......................................................................... 7-7
7.2.4.2 Transfer Size (TSIZ[0:3])........................................................................................ 7-7
7.2.4.3 Transfer Burst (TBST)............................................................................................. 7-8
7.2.4.4 Global (GBL)........................................................................................................... 7-8
7.2.4.4.1 Global (GBL)—Output........................................................................................ 7-8
7.2.4.4.2 Global (GBL)—Input..........................................................................................7-8
7.2.4.5 Caching-Inhibited (CI)—Output ............................................................................. 7-8
7.2.4.6 Write-Through (WT)—Output ................................................................................ 7-9
7.2.5 Address Transfer Termination Signals......................................................................... 7-9
MPC8272 PowerQUICC II Family Reference Manual, Rev. 2
xii Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
7.2.5.1 Address Acknowledge (AACK)..............................................................................7-9
7.2.5.1.1 Address Acknowledge (AACK)—Output...........................................................7-9
7.2.5.1.2 Address Acknowledge (AACK)—Input .............................................................7-9
7.2.5.2 Address Retry (ARTRY)........................................................................................ 7-10
7.2.5.2.1 Address Retry (ARTRY)—Output .................................................................... 7-10
7.2.5.2.2 Address Retry (ARTRY)—Input.......................................................................7-10
7.2.6 Data Bus Arbitration Signals..................................................................................... 7-11
7.2.6.1 Data Bus Grant (DBG) .......................................................................................... 7-11
7.2.6.1.1 Data Bus Grant (DBG)—Input.......................................................................... 7-11
7.2.6.1.2 Data Bus Grant (DBG)—Output....................................................................... 7-11
7.2.6.2 Data Bus Busy (DBB) ........................................................................................... 7-12
7.2.6.2.1 Data Bus Busy (DBB)—Output ........................................................................ 7-12
7.2.6.2.2 Data Bus Busy (DBB)—Input........................................................................... 7-12
7.2.7 Data Transfer Signals................................................................................................. 7-12
7.2.7.1 Data Bus (D[0:63])................................................................................................ 7-12
7.2.7.1.1 Data Bus (D[0:63])—Output............................................................................. 7-13
7.2.7.1.2 Data Bus (D[0:63])—Input................................................................................ 7-13
7.2.8 Data Transfer Termination Signals ............................................................................ 7-13
7.2.8.1 Transfer Acknowledge (TA)..................................................................................7-13
7.2.8.1.1 Transfer Acknowledge (TA)—Input ................................................................. 7-14
7.2.8.1.2 Transfer Acknowledge (TA)—Output............................................................... 7-14
7.2.8.2 Transfer Error Acknowledge (TEA)......................................................................7-14
7.2.8.2.1 Transfer Error Acknowledge (TEA)—Input .....................................................7-15
7.2.8.2.2 Transfer Error Acknowledge (TEA)—Output...................................................7-15
7.2.8.3 Partial Data Valid Indication (PSDVAL)............................................................... 7-15
7.2.8.3.1 Partial Data Valid (PSDVAL)—Input................................................................ 7-15
7.2.8.3.2 Partial Data Valid (PSDVAL)—Output............................................................. 7-16
Chapter 8
The 60x Bus
8.1 Terminology..................................................................................................................... 8-1
8.2 Bus Configuration............................................................................................................8-2
8.2.1 Single-MPC8272 Bus Mode........................................................................................8-2
8.2.2 60x-Compatible Bus Mode..........................................................................................8-3
8.3 60x Bus Protocol Overview............................................................................................. 8-4
8.3.1 Arbitration Phase ......................................................................................................... 8-5
8.3.2 Address Pipelining and Split-Bus Transactions...........................................................8-6
8.4 Address Tenure Operations.............................................................................................. 8-7
8.4.1 Address Arbitration...................................................................................................... 8-7
8.4.2 Address Pipelining....................................................................................................... 8-8
MPC8272 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor xiii
Contents
Paragraph
Number Title
Page
Number
8.4.3 Address Transfer Attribute Signals.............................................................................. 8-9
8.4.3.1 Transfer Type Signal (TT[0:4]) Encoding............................................................... 8-9
8.4.3.2 Transfer Code Signals TC[0:2].............................................................................. 8-12
8.4.3.3 TBST and TSIZ[0:3] Signals and Size of Transfer ...............................................8-12
8.4.3.4 Burst Ordering During Data Transfers .................................................................. 8-13
8.4.3.5 Effect of Alignment on Data Transfers.................................................................. 8-14
8.4.3.6 Effect of Port Size on Data Transfers .................................................................... 8-15
8.4.3.7 60x-Compatible Bus Mode—Size Calculation .....................................................8-17
8.4.3.8 Extended Transfer Mode ....................................................................................... 8-18
8.4.4 Address Transfer Termination ................................................................................... 8-21
8.4.4.1 Address Retried with ARTRY ............................................................................... 8-21
8.4.4.2 Address Tenure Timing Configuration.................................................................. 8-23
8.4.5 Pipeline Control......................................................................................................... 8-23
8.5 Data Tenure Operations ................................................................................................. 8-24
8.5.1 Data Bus Arbitration.................................................................................................. 8-24
8.5.2 Data Streaming Mode................................................................................................ 8-25
8.5.3 Data Bus Transfers and Normal Termination............................................................8-25
8.5.4 Effect of ARTRY Assertion on Data Transfer and Arbitration ................................. 8-26
8.5.5 Port Size Data Bus Transfers and PSDVAL Termination..........................................8-26
8.5.6 Data Bus Termination by Assertion of TEA.............................................................. 8-28
8.6 Memory Coherency—MEI Protocol ............................................................................. 8-29
8.7 Processor State Signals .................................................................................................. 8-30
8.7.1 Support for the lwarx/stwcx. Instruction Pair............................................................ 8-31
8.7.2 TLBISYNC Input ...................................................................................................... 8-31
8.8 Little-Endian Mode........................................................................................................8-31
Chapter 9
PCI Bridge
9.1 Signals..............................................................................................................................9-3
9.2 Clocking...........................................................................................................................9-3
9.3 PCI Bridge Initialization..................................................................................................9-3
9.4 SDMA Interface...............................................................................................................9-4
9.5 Interrupts from PCI Bridge.............................................................................................. 9-4
9.6 60x Bus Arbitration Priority ............................................................................................ 9-4
9.7 60x Bus Masters............................................................................................................... 9-5
9.8 CompactPCI Hot Swap Specification Support................................................................ 9-5
9.9 MPC8272 PCI Interface...................................................................................................9-5
9.9.1 PCI Interface Operation............................................................................................... 9-7
9.9.1.1 Bus Commands........................................................................................................ 9-7
9.9.1.2 PCI Protocol Fundamentals..................................................................................... 9-8
MPC8272 PowerQUICC II Family Reference Manual, Rev. 2
xiv Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
9.9.1.2.1 Basic Transfer Control......................................................................................... 9-8
9.9.1.2.2 Addressing........................................................................................................... 9-8
9.9.1.2.3 Byte Enable Signals............................................................................................. 9-9
9.9.1.2.4 Bus Driving and Turnaround............................................................................... 9-9
9.9.1.3 Bus Transactions.................................................................................................... 9-10
9.9.1.3.1 Read and Write Transactions............................................................................. 9-10
9.9.1.3.2 Transaction Termination.................................................................................... 9-12
9.9.1.4 Other Bus Operations ............................................................................................ 9-14
9.9.1.4.1 Device Selection................................................................................................ 9-14
9.9.1.4.2 Fast Back-to-Back Transactions........................................................................ 9-15
9.9.1.4.3 Data Streaming .................................................................................................. 9-15
9.9.1.4.4 Host Mode Configuration Access...................................................................... 9-15
9.9.1.4.5 Agent Mode Configuration Access ................................................................... 9-17
9.9.1.4.6 Special Cycle Command ................................................................................... 9-17
9.9.1.4.7 Interrupt Acknowledge...................................................................................... 9-18
9.9.1.5 Error Functions...................................................................................................... 9-18
9.9.1.5.1 Parity..................................................................................................................9-18
9.9.1.5.2 Error Reporting.................................................................................................. 9-18
9.9.2 PCI Bus Arbitration................................................................................................... 9-20
9.9.2.1 Bus Parking............................................................................................................9-20
9.9.2.2 Arbitration Algorithm............................................................................................ 9-20
9.9.2.3 Master Latency Timer............................................................................................ 9-21
9.10 Address Map..................................................................................................................9-22
9.10.1 Address Map Programming.......................................................................................9-25
9.10.2 Address Translation ................................................................................................... 9-25
9.10.2.1 PCI Inbound Translation........................................................................................ 9-26
9.10.2.2 PCI Outbound Translation..................................................................................... 9-27
9.10.3 SIU Registers.............................................................................................................9-27
9.11 Configuration Registers ................................................................................................. 9-28
9.11.1 Memory-Mapped Configuration Registers................................................................ 9-28
9.11.1.1 Message Unit (I2O) Registers ............................................................................... 9-31
9.11.1.2 DMA Controller Registers..................................................................................... 9-31
9.11.1.3 PCI Outbound Translation Address Registers (POTARx) ....................................9-31
9.11.1.4 PCI Outbound Base Address Registers (POBARx) .............................................9-32
9.11.1.5 PCI Outbound Comparison Mask Registers (POCMRx) .....................................9-33
9.11.1.6 Discard Timer Control Register (PTCR) .............................................................. 9-34
9.11.1.7 General Purpose Control Register (GPCR) .......................................................... 9-34
9.11.1.8 PCI General Control Register (PCI_GCR) ...........................................................9-36
9.11.1.9 Error Status Register (ESR) .................................................................................. 9-36
9.11.1.10 Error Mask Register (EMR) ................................................................................. 9-38
9.11.1.11 Error Control Register (ECR) ............................................................................... 9-39
MPC8272 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor xv
Contents
Paragraph
Number Title
Page
Number
9.11.1.12 PCI Error Address Capture Register (PCI_EACR) .............................................. 9-40
9.11.1.13 PCI Error Data Capture Register (PCI_EDCR) .................................................... 9-41
9.11.1.14 PCI Error Control Capture Register (PCI_ECCR) ...............................................9-41
9.11.1.15 PCI Inbound Translation Address Registers (PITARx) ........................................ 9-43
9.11.1.16 PCI Inbound Base Address Registers (PIBARx) ..................................................9-43
9.11.1.17 PCI Inbound Comparison Mask Registers (PICMRx) ........................................9-44
9.11.2 PCI Bridge Configuration Registers ........................................................................ 9-46
9.11.2.1 Vendor ID Register ............................................................................................... 9-47
9.11.2.2 Device ID Register ............................................................................................... 9-48
9.11.2.3 PCI Bus Command Register ................................................................................. 9-48
9.11.2.4 PCI Bus Status Register ........................................................................................ 9-49
9.11.2.5 Revision ID Register ............................................................................................. 9-51
9.11.2.6 PCI Bus Programming Interface Register ............................................................9-51
9.11.2.7 Subclass Code Register ......................................................................................... 9-52
9.11.2.8 PCI Bus Base Class Code Register ....................................................................... 9-52
9.11.2.9 PCI Bus Cache Line Size Register ....................................................................... 9-53
9.11.2.10 PCI Bus Latency Timer Register .......................................................................... 9-53
9.11.2.11 Header Type Register ........................................................................................... 9-54
9.11.2.12 BIST Control Register .......................................................................................... 9-54
9.11.2.13 PCI Bus Internal Memory-Mapped Registers Base Address
Register (PIMMRBAR) .................................................................................... 9-54
9.11.2.14 General-Purpose Local Access Base Address Registers (GPLABARx) .............. 9-55
9.11.2.15 Subsystem Vendor ID Register ............................................................................. 9-56
9.11.2.16 Subsystem Device ID Register ............................................................................. 9-57
9.11.2.17 PCI Bus Capabilities Pointer Register ..................................................................9-57
9.11.2.18 PCI Bus Interrupt Line Register ........................................................................... 9-58
9.11.2.19 PCI Bus Interrupt Pin Register ............................................................................. 9-58
9.11.2.20 PCI Bus MIN GNT ............................................................................................... 9-59
9.11.2.21 PCI Bus MAX LAT .............................................................................................. 9-59
9.11.2.22 PCI Bus Function Register ................................................................................... 9-60
9.11.2.23 PCI Bus Arbiter Configuration Register ............................................................... 9-61
9.11.2.24 PCI Hot Swap Register Block .............................................................................. 9-61
9.11.2.25 PCI Hot Swap Control Status Register ................................................................. 9-62
9.11.2.26 PCI Configuration Register Access from the Core ...............................................9-63
9.11.2.27 PCI Configuration Register Access in Big-Endian Mode .................................... 9-63
9.11.2.27.1 Additional Information on Endianness .............................................................9-64
9.11.2.27.2 Notes on GPCR[LE_MODE] ........................................................................... 9-64
9.11.2.28 Initializing the PCI Configuration Registers ........................................................9-65
9.12 Message Unit (I2O) ...................................................................................................... 9-67
9.12.1 Message Registers...................................................................................................... 9-67
9.12.1.1 Inbound Message Registers (IMRx) ..................................................................... 9-68
MPC8272 PowerQUICC II Family Reference Manual, Rev. 2
xvi Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
9.12.1.2 Outbound Message Registers (OMRx) .................................................................9-69
9.12.2 Door Bell Registers ................................................................................................... 9-69
9.12.2.1 Outbound Doorbell Register (ODR) ..................................................................... 9-70
9.12.2.2 Inbound Doorbell Register (IDR) ......................................................................... 9-70
9.12.3 I
2
O Unit ....................................................................................................................9-71
9.12.3.1 PCI Configuration Identification .......................................................................... 9-72
9.12.3.2 Inbound FIFOs ...................................................................................................... 9-72
9.12.3.2.1 Inbound Free_FIFO Head Pointer Register (IFHPR) and Inbound
Free_FIFO Tail Pointer Register (IFTPR) .................................................... 9-73
9.12.3.2.2 Inbound Post_FIFO Head Pointer Register (IPHPR) and Inbound
Post_FIFO Tail Pointer Register (IPTPR) .................................................... 9-74
9.12.3.3 Outbound FIFOs ................................................................................................... 9-76
9.12.3.3.1 Outbound Free_FIFO Head Pointer Register (OFHPR) and Outbound
Free_FIFO Tail Pointer Register (OFTPR) .................................................. 9-76
9.12.3.3.2 Outbound Post_FIFO Head Pointer Register (OPHPR) and Outbound
Post_FIFO Tail Pointer Register (OPTPR) ...................................................9-77
9.12.3.4 I2O Registers ........................................................................................................ 9-79
9.12.3.4.1 Inbound FIFO Queue Port Register (IFQPR) ...................................................9-79
9.12.3.4.2 Outbound FIFO Queue Port Register (OFQPR) ...............................................9-80
9.12.3.4.3 Outbound Message Interrupt Status Register (OMISR) ...................................9-80
9.12.3.4.4 Outbound Message Interrupt Mask Register (OMIMR) ..................................9-81
9.12.3.4.5 Inbound Message Interrupt Status Register (IMISR) .......................................9-82
9.12.3.4.6 Inbound Message Interrupt Mask Register (IMIMR) .......................................9-84
9.12.3.4.7 Messaging Unit Control Register (MUCR) ...................................................... 9-85
9.12.3.4.8 Queue Base Address Register (QBAR) ............................................................ 9-86
9.13 DMA Controller............................................................................................................. 9-87
9.13.1 DMA Operation......................................................................................................... 9-87
9.13.1.1 DMA Direct Mode................................................................................................. 9-88
9.13.1.2 DMA Chaining Mode............................................................................................ 9-88
9.13.1.3 DMA Coherency.................................................................................................... 9-89
9.13.1.4 Halt and Error Conditions...................................................................................... 9-89
9.13.1.5 DMA Transfer Types............................................................................................. 9-89
9.13.1.6 DMA Registers...................................................................................................... 9-90
9.13.1.6.1 DMA Mode Register [0–3] (DMAMRx) .........................................................9-90
9.13.1.6.2 DMA Status Register [0–3] (DMASRx) .......................................................... 9-92
9.13.1.6.3 DMA Current Descriptor Address Register [0–3] (DMACDARx) .................. 9-93
9.13.1.6.4 DMA Source Address Registers [0–3] (DMASARx) ...................................... 9-94
9.13.1.6.5 DMA Destination Address Register [0–3] (DMADARx) ................................ 9-95
9.13.1.6.6 DMA Byte Count Register [0–3] (DMABCRx) ...............................................9-95
9.13.1.6.7 DMA Next Descriptor Address Registers [0–3] (DMANDARx) ....................9-96
9.13.2 DMA Segment Descriptors........................................................................................ 9-97
MPC8272 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor xvii
Contents
Paragraph
Number Title
Page
Number
9.13.2.1 Descriptor in Big-Endian Mode............................................................................. 9-98
9.13.2.2 Descriptor in Little-Endian Mode.......................................................................... 9-99
9.14 Error Handling ............................................................................................................... 9-99
9.14.1 Interrupt and Error Signals ........................................................................................ 9-99
9.14.1.1 PCI Bus Error Signals............................................................................................ 9-99
9.14.1.1.1 System Error (SERR) ...................................................................................... 9-100
9.14.1.1.2 Parity Error (PERR)......................................................................................... 9-100
9.14.1.1.3 Error Reporting................................................................................................ 9-100
9.14.1.2 Illegal Register Access Error............................................................................... 9-100
9.14.1.3 PCI Interface........................................................................................................ 9-100
9.14.1.3.1 Address Parity Error........................................................................................ 9-101
9.14.1.3.2 Data Parity Error.............................................................................................. 9-101
9.14.1.3.3 Master-Abort Transaction Termination ........................................................... 9-101
9.14.1.3.4 Target-Abort Error........................................................................................... 9-102
9.14.1.3.5 NMI ................................................................................................................. 9-102
9.14.1.4 Embedded Utilities ..............................................................................................9-102
9.14.1.4.1 Outbound Free Queue Overflow .....................................................................9-102
9.14.1.4.2 Inbound Post Queue Overflow........................................................................ 9-102
9.14.1.4.3 Inbound DoorBell Machine Check..................................................................9-102
Chapter 10
PLL and Clock Generator
10.1 MPC8272 Clock Block Diagram................................................................................... 10-1
10.1.1 Main PLL................................................................................................................... 10-1
10.1.2 Core PLL....................................................................................................................10-1
10.1.3 Skew Elimination....................................................................................................... 10-2
10.1.4 Dividers......................................................................................................................10-2
10.1.5 Internal Clock Signals................................................................................................ 10-2
10.1.6 PCI Bridge as an Agent Operating from the PCI System Clock ............................... 10-4
10.1.7 PCI Bridge as a Host Generating the PCI System Clock ..........................................10-4
10.2 External Clock Inputs .................................................................................................... 10-5
10.3 PLL Pins ....................................................................................................................... 10-5
10.4 System Clock Control Register (SCCR)........................................................................ 10-6
10.5 System Clock Mode Register (SCMR).......................................................................... 10-7
10.5.1 SCMR[CORECNF] Definitions................................................................................ 10-8
10.6 Clock Configuration Modes........................................................................................... 10-9
MPC8272 PowerQUICC II Family Reference Manual, Rev. 2
xviii Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
Chapter 11
Memory Controller
11.1 Features.......................................................................................................................... 11-2
11.2 Basic Architecture.......................................................................................................... 11-3
11.2.1 Address and Address Space Checking....................................................................... 11-6
11.2.2 Page Hit Checking..................................................................................................... 11-6
11.2.3 Transfer Error Acknowledge (TEA) Generation....................................................... 11-7
11.2.4 Data Buffer Controls (BCTLx).................................................................................. 11-7
11.2.5 Atomic Bus Operation ............................................................................................... 11-7
11.2.6 Data Pipelining .......................................................................................................... 11-7
11.2.7 External Memory Controller Support........................................................................ 11-8
11.2.8 Data Buffer Control Signals (BCTL1 and BCLT2)................................................... 11-8
11.2.9 External Address Latch Enable Signal (ALE)........................................................... 11-8
11.2.10 Partial Data Valid Indication (PSDVAL)................................................................... 11-9
11.2.11 BADDR[27:31] Signal Connections ....................................................................... 11-10
11.3 Register Descriptions................................................................................................... 11-10
11.3.1 Base Registers (BRx)................................................................................................11-11
11.3.2 Option Registers (ORx)........................................................................................... 11-13
11.3.3 60x SDRAM Mode Register (PSDMR) .................................................................. 11-18
11.3.4 Machine A/B/C Mode Registers (MxMR) .............................................................. 11-21
11.3.5 Memory Data Register (MDR)................................................................................ 11-23
11.3.6 Memory Address Register (MAR) .......................................................................... 11-24
11.3.7 60x Bus-Assigned UPM Refresh Timer (PURT)..................................................... 11-25
11.3.8 60x Bus-Assigned SDRAM Refresh Timer (PSRT)................................................ 11-25
11.3.9 Memory Refresh Timer Prescaler Register (MPTPR)............................................. 11-26
11.3.10 60x Bus Error Status and Control Registers (TESCRx).......................................... 11-26
11.4 SDRAM Machine ........................................................................................................ 11-26
11.4.1 Supported SDRAM Configurations......................................................................... 11-29
11.4.2 SDRAM Power-On Initialization ............................................................................ 11-29
11.4.3 JEDEC-Standard SDRAM Interface Commands .................................................... 11-29
11.4.4 Page-Mode Support and Pipeline Accesses............................................................. 11-30
11.4.5 Bank Interleaving .................................................................................................... 11-30
11.4.5.1 Using BNKSEL Signals in Single-MPC8272 Bus Mode.................................... 11-31
11.4.5.2 SDRAM Address Multiplexing (SDAM and BSMA)......................................... 11-31
11.4.6 SDRAM Device-Specific Parameters...................................................................... 11-32
11.4.6.1 Precharge-to-Activate Interval............................................................................. 11-32
11.4.6.2 Activate to Read/Write Interval........................................................................... 11-33
11.4.6.3 Column Address to First Data Out—CAS Latency............................................. 11-34
11.4.6.4 Last Data Out to Precharge.................................................................................. 11-34
11.4.6.5 Last Data In to Precharge—Write Recovery....................................................... 11-35
MPC8272 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor xix
Contents
Paragraph
Number Title
Page
Number
11.4.6.6 Refresh Recovery Interval (RFRC) ..................................................................... 11-35
11.4.6.7 External Address Multiplexing Signal................................................................. 11-36
11.4.6.8 External Address and Command Buffers (BUFCMD)........................................ 11-36
11.4.7 SDRAM Interface Timing ....................................................................................... 11-37
11.4.8 SDRAM Read/Write Transactions........................................................................... 11-40
11.4.9 SDRAM Mode-Set Command Timing.................................................................... 11-40
11.4.10 SDRAM Refresh...................................................................................................... 11-41
11.4.11 SDRAM Refresh Timing ......................................................................................... 11-42
11.4.12 SDRAM Configuration Examples........................................................................... 11-42
11.4.12.1 SDRAM Configuration Example (Page-Based Interleaving).............................. 11-42
11.4.13 SDRAM Configuration Example (Bank-Based Interleaving)................................. 11-44
11.5 General-Purpose Chip-Select Machine (GPCM).........................................................11-45
11.5.1 Timing Configuration .............................................................................................. 11-46
11.5.1.1 Chip-Select Assertion Timing ............................................................................. 11-47
11.5.1.2 Chip-Select and Write Enable Deassertion Timing............................................. 11-48
11.5.1.3 Relaxed Timing.................................................................................................... 11-49
11.5.1.4 Output Enable (OE) Timing ................................................................................ 11-51
11.5.1.5 Programmable Wait State Configuration............................................................. 11-52
11.5.1.6 Extended Hold Time on Read Accesses.............................................................. 11-52
11.5.2 External Access Termination................................................................................... 11-54
11.5.3 Boot Chip-Select Operation..................................................................................... 11-55
11.5.4 Differences between MPC8xx’s GPCM and MPC82xx’s GPCM........................... 11-56
11.6 User-Programmable Machines (UPMs)....................................................................... 11-56
11.6.1 Requests................................................................................................................... 11-57
11.6.1.1 Memory Access Requests.................................................................................... 11-58
11.6.1.2 UPM Refresh Timer Requests ............................................................................. 11-59
11.6.1.3 Software Requests—run Command .................................................................... 11-59
11.6.1.4 Exception Requests.............................................................................................. 11-60
11.6.2 Programming the UPMs .......................................................................................... 11-60
11.6.3 Clock Timing........................................................................................................... 11-60
11.6.4 The RAM Array....................................................................................................... 11-62
11.6.4.1 RAM Words......................................................................................................... 11-63
11.6.4.1.1 Chip-Select Signals (CxTx)............................................................................. 11-67
11.6.4.1.2 Byte-Select Signals (BxTx)............................................................................. 11-68
11.6.4.1.3 General-Purpose Signals (GxTx, GOx)........................................................... 11-69
11.6.4.1.4 Loop Control.................................................................................................... 11-69
11.6.4.1.5 Repeat Execution of Current RAM Word (REDO) ........................................ 11-69
11.6.4.2 Address Multiplexing .......................................................................................... 11-70
11.6.4.3 Data Valid and Data Sample Control................................................................... 11-70
11.6.4.4 Signals Negation.................................................................................................. 11-71
11.6.4.5 The Wait Mechanism........................................................................................... 11-71
MPC8272 PowerQUICC II Family Reference Manual, Rev. 2
xx Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
11.6.4.6 Extended Hold Time on Read Accesses ............................................................. 11-72
11.6.5 UPM DRAM Configuration Example..................................................................... 11-72
11.6.6 Differences between MPC8xx UPM and MPC82xx UPM ..................................... 11-73
11.7 Memory System Interface Example Using UPM........................................................ 11-74
11.7.0.1 EDO Interface Example....................................................................................... 11-84
11.8 Handling Devices with Slow or Variable Access Times.............................................. 11-93
11.8.1 Slow Devices Example............................................................................................ 11-93
11.9 External Master Support (60x-Compatible Mode)...................................................... 11-93
11.9.1 60x-Compatible External Masters (non-MPC8272)................................................ 11-93
11.9.2 MPC8272 External Masters..................................................................................... 11-94
11.9.3 Extended Controls in 60x-Compatible Mode.......................................................... 11-94
11.9.4 Address Incrementing for External Bursting Masters ............................................. 11-94
11.9.5 External Masters Timing.......................................................................................... 11-94
11.9.5.1 Example of External Master Using the SDRAM Machine ................................. 11-96
Chapter 12
IEEE 1149.1 Test Access Port
12.1 Overview........................................................................................................................12-1
12.2 TAP Controller...............................................................................................................12-2
12.3 Boundary Scan Register................................................................................................. 12-3
12.4 Instruction Register........................................................................................................ 12-5
12.5 MPC8272 Restrictions...................................................................................................12-7
12.6 Nonscan Chain Operation.............................................................................................. 12-7
Chapter 13
Communications Processor Module Overview
13.1 Features..........................................................................................................................13-1
13.2 MPC8272 Serial Configurations....................................................................................13-3
13.3 Communications Processor (CP)................................................................................... 13-4
13.3.1 Features......................................................................................................................13-4
13.3.2 CP Block Diagram..................................................................................................... 13-4
13.3.3 G2_LE Core Interface................................................................................................ 13-6
13.3.4 Peripheral Interface.................................................................................................... 13-6
13.3.5 Execution from RAM ................................................................................................ 13-7
13.3.6 RISC Controller Configuration Register (RCCR).....................................................13-7
13.3.7 RISC Time-Stamp Control Register (RTSCR).......................................................... 13-9
13.3.8 RISC Time-Stamp Register (RTSR)........................................................................ 13-10
13.3.9 RISC Microcode Revision Number......................................................................... 13-10
13.4 Command Set............................................................................................................... 13-11
  • Page 1 1
  • Page 2 2
  • Page 3 3
  • Page 4 4
  • Page 5 5
  • Page 6 6
  • Page 7 7
  • Page 8 8
  • Page 9 9
  • Page 10 10
  • Page 11 11
  • Page 12 12
  • Page 13 13
  • Page 14 14
  • Page 15 15
  • Page 16 16
  • Page 17 17
  • Page 18 18
  • Page 19 19
  • Page 20 20
  • Page 21 21
  • Page 22 22
  • Page 23 23
  • Page 24 24
  • Page 25 25
  • Page 26 26
  • Page 27 27
  • Page 28 28
  • Page 29 29
  • Page 30 30
  • Page 31 31
  • Page 32 32
  • Page 33 33
  • Page 34 34
  • Page 35 35
  • Page 36 36
  • Page 37 37
  • Page 38 38
  • Page 39 39
  • Page 40 40
  • Page 41 41
  • Page 42 42
  • Page 43 43
  • Page 44 44
  • Page 45 45
  • Page 46 46
  • Page 47 47
  • Page 48 48
  • Page 49 49
  • Page 50 50
  • Page 51 51
  • Page 52 52
  • Page 53 53
  • Page 54 54
  • Page 55 55
  • Page 56 56
  • Page 57 57
  • Page 58 58
  • Page 59 59
  • Page 60 60
  • Page 61 61
  • Page 62 62
  • Page 63 63
  • Page 64 64
  • Page 65 65
  • Page 66 66
  • Page 67 67
  • Page 68 68
  • Page 69 69
  • Page 70 70
  • Page 71 71
  • Page 72 72
  • Page 73 73
  • Page 74 74
  • Page 75 75
  • Page 76 76
  • Page 77 77
  • Page 78 78
  • Page 79 79
  • Page 80 80
  • Page 81 81
  • Page 82 82
  • Page 83 83
  • Page 84 84
  • Page 85 85
  • Page 86 86
  • Page 87 87
  • Page 88 88
  • Page 89 89
  • Page 90 90
  • Page 91 91
  • Page 92 92
  • Page 93 93
  • Page 94 94
  • Page 95 95
  • Page 96 96
  • Page 97 97
  • Page 98 98
  • Page 99 99
  • Page 100 100
  • Page 101 101
  • Page 102 102
  • Page 103 103
  • Page 104 104
  • Page 105 105
  • Page 106 106
  • Page 107 107
  • Page 108 108
  • Page 109 109
  • Page 110 110
  • Page 111 111
  • Page 112 112
  • Page 113 113
  • Page 114 114
  • Page 115 115
  • Page 116 116
  • Page 117 117
  • Page 118 118
  • Page 119 119
  • Page 120 120
  • Page 121 121
  • Page 122 122
  • Page 123 123
  • Page 124 124
  • Page 125 125
  • Page 126 126
  • Page 127 127
  • Page 128 128
  • Page 129 129
  • Page 130 130
  • Page 131 131
  • Page 132 132
  • Page 133 133
  • Page 134 134
  • Page 135 135
  • Page 136 136
  • Page 137 137
  • Page 138 138
  • Page 139 139
  • Page 140 140
  • Page 141 141
  • Page 142 142
  • Page 143 143
  • Page 144 144
  • Page 145 145
  • Page 146 146
  • Page 147 147
  • Page 148 148
  • Page 149 149
  • Page 150 150
  • Page 151 151
  • Page 152 152
  • Page 153 153
  • Page 154 154
  • Page 155 155
  • Page 156 156
  • Page 157 157
  • Page 158 158
  • Page 159 159
  • Page 160 160
  • Page 161 161
  • Page 162 162
  • Page 163 163
  • Page 164 164
  • Page 165 165
  • Page 166 166
  • Page 167 167
  • Page 168 168
  • Page 169 169
  • Page 170 170
  • Page 171 171
  • Page 172 172
  • Page 173 173
  • Page 174 174
  • Page 175 175
  • Page 176 176
  • Page 177 177
  • Page 178 178
  • Page 179 179
  • Page 180 180
  • Page 181 181
  • Page 182 182
  • Page 183 183
  • Page 184 184
  • Page 185 185
  • Page 186 186
  • Page 187 187
  • Page 188 188
  • Page 189 189
  • Page 190 190
  • Page 191 191
  • Page 192 192
  • Page 193 193
  • Page 194 194
  • Page 195 195
  • Page 196 196
  • Page 197 197
  • Page 198 198
  • Page 199 199
  • Page 200 200
  • Page 201 201
  • Page 202 202
  • Page 203 203
  • Page 204 204
  • Page 205 205
  • Page 206 206
  • Page 207 207
  • Page 208 208
  • Page 209 209
  • Page 210 210
  • Page 211 211
  • Page 212 212
  • Page 213 213
  • Page 214 214
  • Page 215 215
  • Page 216 216
  • Page 217 217
  • Page 218 218
  • Page 219 219
  • Page 220 220
  • Page 221 221
  • Page 222 222
  • Page 223 223
  • Page 224 224
  • Page 225 225
  • Page 226 226
  • Page 227 227
  • Page 228 228
  • Page 229 229
  • Page 230 230
  • Page 231 231
  • Page 232 232
  • Page 233 233
  • Page 234 234
  • Page 235 235
  • Page 236 236
  • Page 237 237
  • Page 238 238
  • Page 239 239
  • Page 240 240
  • Page 241 241
  • Page 242 242
  • Page 243 243
  • Page 244 244
  • Page 245 245
  • Page 246 246
  • Page 247 247
  • Page 248 248
  • Page 249 249
  • Page 250 250
  • Page 251 251
  • Page 252 252
  • Page 253 253
  • Page 254 254
  • Page 255 255
  • Page 256 256
  • Page 257 257
  • Page 258 258
  • Page 259 259
  • Page 260 260
  • Page 261 261
  • Page 262 262
  • Page 263 263
  • Page 264 264
  • Page 265 265
  • Page 266 266
  • Page 267 267
  • Page 268 268
  • Page 269 269
  • Page 270 270
  • Page 271 271
  • Page 272 272
  • Page 273 273
  • Page 274 274
  • Page 275 275
  • Page 276 276
  • Page 277 277
  • Page 278 278
  • Page 279 279
  • Page 280 280
  • Page 281 281
  • Page 282 282
  • Page 283 283
  • Page 284 284
  • Page 285 285
  • Page 286 286
  • Page 287 287
  • Page 288 288
  • Page 289 289
  • Page 290 290
  • Page 291 291
  • Page 292 292
  • Page 293 293
  • Page 294 294
  • Page 295 295
  • Page 296 296
  • Page 297 297
  • Page 298 298
  • Page 299 299
  • Page 300 300
  • Page 301 301
  • Page 302 302
  • Page 303 303
  • Page 304 304
  • Page 305 305
  • Page 306 306
  • Page 307 307
  • Page 308 308
  • Page 309 309
  • Page 310 310
  • Page 311 311
  • Page 312 312
  • Page 313 313
  • Page 314 314
  • Page 315 315
  • Page 316 316
  • Page 317 317
  • Page 318 318
  • Page 319 319
  • Page 320 320
  • Page 321 321
  • Page 322 322
  • Page 323 323
  • Page 324 324
  • Page 325 325
  • Page 326 326
  • Page 327 327
  • Page 328 328
  • Page 329 329
  • Page 330 330
  • Page 331 331
  • Page 332 332
  • Page 333 333
  • Page 334 334
  • Page 335 335
  • Page 336 336
  • Page 337 337
  • Page 338 338
  • Page 339 339
  • Page 340 340
  • Page 341 341
  • Page 342 342
  • Page 343 343
  • Page 344 344
  • Page 345 345
  • Page 346 346
  • Page 347 347
  • Page 348 348
  • Page 349 349
  • Page 350 350
  • Page 351 351
  • Page 352 352
  • Page 353 353
  • Page 354 354
  • Page 355 355
  • Page 356 356
  • Page 357 357
  • Page 358 358
  • Page 359 359
  • Page 360 360
  • Page 361 361
  • Page 362 362
  • Page 363 363
  • Page 364 364
  • Page 365 365
  • Page 366 366
  • Page 367 367
  • Page 368 368
  • Page 369 369
  • Page 370 370
  • Page 371 371
  • Page 372 372
  • Page 373 373
  • Page 374 374
  • Page 375 375
  • Page 376 376
  • Page 377 377
  • Page 378 378
  • Page 379 379
  • Page 380 380
  • Page 381 381
  • Page 382 382
  • Page 383 383
  • Page 384 384
  • Page 385 385
  • Page 386 386
  • Page 387 387
  • Page 388 388
  • Page 389 389
  • Page 390 390
  • Page 391 391
  • Page 392 392
  • Page 393 393
  • Page 394 394
  • Page 395 395
  • Page 396 396
  • Page 397 397
  • Page 398 398
  • Page 399 399
  • Page 400 400
  • Page 401 401
  • Page 402 402
  • Page 403 403
  • Page 404 404
  • Page 405 405
  • Page 406 406
  • Page 407 407
  • Page 408 408
  • Page 409 409
  • Page 410 410
  • Page 411 411
  • Page 412 412
  • Page 413 413
  • Page 414 414
  • Page 415 415
  • Page 416 416
  • Page 417 417
  • Page 418 418
  • Page 419 419
  • Page 420 420
  • Page 421 421
  • Page 422 422
  • Page 423 423
  • Page 424 424
  • Page 425 425
  • Page 426 426
  • Page 427 427
  • Page 428 428
  • Page 429 429
  • Page 430 430
  • Page 431 431
  • Page 432 432
  • Page 433 433
  • Page 434 434
  • Page 435 435
  • Page 436 436
  • Page 437 437
  • Page 438 438
  • Page 439 439
  • Page 440 440
  • Page 441 441
  • Page 442 442
  • Page 443 443
  • Page 444 444
  • Page 445 445
  • Page 446 446
  • Page 447 447
  • Page 448 448
  • Page 449 449
  • Page 450 450
  • Page 451 451
  • Page 452 452
  • Page 453 453
  • Page 454 454
  • Page 455 455
  • Page 456 456
  • Page 457 457
  • Page 458 458
  • Page 459 459
  • Page 460 460
  • Page 461 461
  • Page 462 462
  • Page 463 463
  • Page 464 464
  • Page 465 465
  • Page 466 466
  • Page 467 467
  • Page 468 468
  • Page 469 469
  • Page 470 470
  • Page 471 471
  • Page 472 472
  • Page 473 473
  • Page 474 474
  • Page 475 475
  • Page 476 476
  • Page 477 477
  • Page 478 478
  • Page 479 479
  • Page 480 480
  • Page 481 481
  • Page 482 482
  • Page 483 483
  • Page 484 484
  • Page 485 485
  • Page 486 486
  • Page 487 487
  • Page 488 488
  • Page 489 489
  • Page 490 490
  • Page 491 491
  • Page 492 492
  • Page 493 493
  • Page 494 494
  • Page 495 495
  • Page 496 496
  • Page 497 497
  • Page 498 498
  • Page 499 499
  • Page 500 500
  • Page 501 501
  • Page 502 502
  • Page 503 503
  • Page 504 504
  • Page 505 505
  • Page 506 506
  • Page 507 507
  • Page 508 508
  • Page 509 509
  • Page 510 510
  • Page 511 511
  • Page 512 512
  • Page 513 513
  • Page 514 514
  • Page 515 515
  • Page 516 516
  • Page 517 517
  • Page 518 518
  • Page 519 519
  • Page 520 520
  • Page 521 521
  • Page 522 522
  • Page 523 523
  • Page 524 524
  • Page 525 525
  • Page 526 526
  • Page 527 527
  • Page 528 528
  • Page 529 529
  • Page 530 530
  • Page 531 531
  • Page 532 532
  • Page 533 533
  • Page 534 534
  • Page 535 535
  • Page 536 536
  • Page 537 537
  • Page 538 538
  • Page 539 539
  • Page 540 540
  • Page 541 541
  • Page 542 542
  • Page 543 543
  • Page 544 544
  • Page 545 545
  • Page 546 546
  • Page 547 547
  • Page 548 548
  • Page 549 549
  • Page 550 550
  • Page 551 551
  • Page 552 552
  • Page 553 553
  • Page 554 554
  • Page 555 555
  • Page 556 556
  • Page 557 557
  • Page 558 558
  • Page 559 559
  • Page 560 560
  • Page 561 561
  • Page 562 562
  • Page 563 563
  • Page 564 564
  • Page 565 565
  • Page 566 566
  • Page 567 567
  • Page 568 568
  • Page 569 569
  • Page 570 570
  • Page 571 571
  • Page 572 572
  • Page 573 573
  • Page 574 574
  • Page 575 575
  • Page 576 576
  • Page 577 577
  • Page 578 578
  • Page 579 579
  • Page 580 580
  • Page 581 581
  • Page 582 582
  • Page 583 583
  • Page 584 584
  • Page 585 585
  • Page 586 586
  • Page 587 587
  • Page 588 588
  • Page 589 589
  • Page 590 590
  • Page 591 591
  • Page 592 592
  • Page 593 593
  • Page 594 594
  • Page 595 595
  • Page 596 596
  • Page 597 597
  • Page 598 598
  • Page 599 599
  • Page 600 600
  • Page 601 601
  • Page 602 602
  • Page 603 603
  • Page 604 604
  • Page 605 605
  • Page 606 606
  • Page 607 607
  • Page 608 608
  • Page 609 609
  • Page 610 610
  • Page 611 611
  • Page 612 612
  • Page 613 613
  • Page 614 614
  • Page 615 615
  • Page 616 616
  • Page 617 617
  • Page 618 618
  • Page 619 619
  • Page 620 620
  • Page 621 621
  • Page 622 622
  • Page 623 623
  • Page 624 624
  • Page 625 625
  • Page 626 626
  • Page 627 627
  • Page 628 628
  • Page 629 629
  • Page 630 630
  • Page 631 631
  • Page 632 632
  • Page 633 633
  • Page 634 634
  • Page 635 635
  • Page 636 636
  • Page 637 637
  • Page 638 638
  • Page 639 639
  • Page 640 640
  • Page 641 641
  • Page 642 642
  • Page 643 643
  • Page 644 644
  • Page 645 645
  • Page 646 646
  • Page 647 647
  • Page 648 648
  • Page 649 649
  • Page 650 650
  • Page 651 651
  • Page 652 652
  • Page 653 653
  • Page 654 654
  • Page 655 655
  • Page 656 656
  • Page 657 657
  • Page 658 658
  • Page 659 659
  • Page 660 660
  • Page 661 661
  • Page 662 662
  • Page 663 663
  • Page 664 664
  • Page 665 665
  • Page 666 666
  • Page 667 667
  • Page 668 668
  • Page 669 669
  • Page 670 670
  • Page 671 671
  • Page 672 672
  • Page 673 673
  • Page 674 674
  • Page 675 675
  • Page 676 676
  • Page 677 677
  • Page 678 678
  • Page 679 679
  • Page 680 680
  • Page 681 681
  • Page 682 682
  • Page 683 683
  • Page 684 684
  • Page 685 685
  • Page 686 686
  • Page 687 687
  • Page 688 688
  • Page 689 689
  • Page 690 690
  • Page 691 691
  • Page 692 692
  • Page 693 693
  • Page 694 694
  • Page 695 695
  • Page 696 696
  • Page 697 697
  • Page 698 698
  • Page 699 699
  • Page 700 700
  • Page 701 701
  • Page 702 702
  • Page 703 703
  • Page 704 704
  • Page 705 705
  • Page 706 706
  • Page 707 707
  • Page 708 708
  • Page 709 709
  • Page 710 710
  • Page 711 711
  • Page 712 712
  • Page 713 713
  • Page 714 714
  • Page 715 715
  • Page 716 716
  • Page 717 717
  • Page 718 718
  • Page 719 719
  • Page 720 720
  • Page 721 721
  • Page 722 722
  • Page 723 723
  • Page 724 724
  • Page 725 725
  • Page 726 726
  • Page 727 727
  • Page 728 728
  • Page 729 729
  • Page 730 730
  • Page 731 731
  • Page 732 732
  • Page 733 733
  • Page 734 734
  • Page 735 735
  • Page 736 736
  • Page 737 737
  • Page 738 738
  • Page 739 739
  • Page 740 740
  • Page 741 741
  • Page 742 742
  • Page 743 743
  • Page 744 744
  • Page 745 745
  • Page 746 746
  • Page 747 747
  • Page 748 748
  • Page 749 749
  • Page 750 750
  • Page 751 751
  • Page 752 752
  • Page 753 753
  • Page 754 754
  • Page 755 755
  • Page 756 756
  • Page 757 757
  • Page 758 758
  • Page 759 759
  • Page 760 760
  • Page 761 761
  • Page 762 762
  • Page 763 763
  • Page 764 764
  • Page 765 765
  • Page 766 766
  • Page 767 767
  • Page 768 768
  • Page 769 769
  • Page 770 770
  • Page 771 771
  • Page 772 772
  • Page 773 773
  • Page 774 774
  • Page 775 775
  • Page 776 776
  • Page 777 777
  • Page 778 778
  • Page 779 779
  • Page 780 780
  • Page 781 781
  • Page 782 782
  • Page 783 783
  • Page 784 784
  • Page 785 785
  • Page 786 786
  • Page 787 787
  • Page 788 788
  • Page 789 789
  • Page 790 790
  • Page 791 791
  • Page 792 792
  • Page 793 793
  • Page 794 794
  • Page 795 795
  • Page 796 796
  • Page 797 797
  • Page 798 798
  • Page 799 799
  • Page 800 800
  • Page 801 801
  • Page 802 802
  • Page 803 803
  • Page 804 804
  • Page 805 805
  • Page 806 806
  • Page 807 807
  • Page 808 808
  • Page 809 809
  • Page 810 810
  • Page 811 811
  • Page 812 812
  • Page 813 813
  • Page 814 814
  • Page 815 815
  • Page 816 816
  • Page 817 817
  • Page 818 818
  • Page 819 819
  • Page 820 820
  • Page 821 821
  • Page 822 822
  • Page 823 823
  • Page 824 824
  • Page 825 825
  • Page 826 826
  • Page 827 827
  • Page 828 828
  • Page 829 829
  • Page 830 830
  • Page 831 831
  • Page 832 832
  • Page 833 833
  • Page 834 834
  • Page 835 835
  • Page 836 836
  • Page 837 837
  • Page 838 838
  • Page 839 839
  • Page 840 840
  • Page 841 841
  • Page 842 842
  • Page 843 843
  • Page 844 844
  • Page 845 845
  • Page 846 846
  • Page 847 847
  • Page 848 848
  • Page 849 849
  • Page 850 850
  • Page 851 851
  • Page 852 852
  • Page 853 853
  • Page 854 854
  • Page 855 855
  • Page 856 856
  • Page 857 857
  • Page 858 858
  • Page 859 859
  • Page 860 860
  • Page 861 861
  • Page 862 862
  • Page 863 863
  • Page 864 864
  • Page 865 865
  • Page 866 866
  • Page 867 867
  • Page 868 868
  • Page 869 869
  • Page 870 870
  • Page 871 871
  • Page 872 872
  • Page 873 873
  • Page 874 874
  • Page 875 875
  • Page 876 876
  • Page 877 877
  • Page 878 878
  • Page 879 879
  • Page 880 880
  • Page 881 881
  • Page 882 882
  • Page 883 883
  • Page 884 884
  • Page 885 885
  • Page 886 886
  • Page 887 887
  • Page 888 888
  • Page 889 889
  • Page 890 890
  • Page 891 891
  • Page 892 892
  • Page 893 893
  • Page 894 894
  • Page 895 895
  • Page 896 896
  • Page 897 897
  • Page 898 898
  • Page 899 899
  • Page 900 900
  • Page 901 901
  • Page 902 902
  • Page 903 903
  • Page 904 904
  • Page 905 905
  • Page 906 906
  • Page 907 907
  • Page 908 908
  • Page 909 909
  • Page 910 910
  • Page 911 911
  • Page 912 912
  • Page 913 913
  • Page 914 914
  • Page 915 915
  • Page 916 916
  • Page 917 917
  • Page 918 918
  • Page 919 919
  • Page 920 920
  • Page 921 921
  • Page 922 922
  • Page 923 923
  • Page 924 924
  • Page 925 925
  • Page 926 926
  • Page 927 927
  • Page 928 928
  • Page 929 929
  • Page 930 930
  • Page 931 931
  • Page 932 932
  • Page 933 933
  • Page 934 934
  • Page 935 935
  • Page 936 936
  • Page 937 937
  • Page 938 938
  • Page 939 939
  • Page 940 940
  • Page 941 941
  • Page 942 942
  • Page 943 943
  • Page 944 944
  • Page 945 945
  • Page 946 946
  • Page 947 947
  • Page 948 948
  • Page 949 949
  • Page 950 950
  • Page 951 951
  • Page 952 952
  • Page 953 953
  • Page 954 954
  • Page 955 955
  • Page 956 956
  • Page 957 957
  • Page 958 958
  • Page 959 959
  • Page 960 960
  • Page 961 961
  • Page 962 962
  • Page 963 963
  • Page 964 964
  • Page 965 965
  • Page 966 966
  • Page 967 967
  • Page 968 968
  • Page 969 969
  • Page 970 970
  • Page 971 971
  • Page 972 972
  • Page 973 973
  • Page 974 974
  • Page 975 975
  • Page 976 976
  • Page 977 977
  • Page 978 978
  • Page 979 979
  • Page 980 980
  • Page 981 981
  • Page 982 982
  • Page 983 983
  • Page 984 984
  • Page 985 985
  • Page 986 986
  • Page 987 987
  • Page 988 988
  • Page 989 989
  • Page 990 990
  • Page 991 991
  • Page 992 992
  • Page 993 993
  • Page 994 994
  • Page 995 995
  • Page 996 996
  • Page 997 997
  • Page 998 998
  • Page 999 999
  • Page 1000 1000
  • Page 1001 1001
  • Page 1002 1002
  • Page 1003 1003
  • Page 1004 1004
  • Page 1005 1005
  • Page 1006 1006
  • Page 1007 1007
  • Page 1008 1008
  • Page 1009 1009
  • Page 1010 1010
  • Page 1011 1011
  • Page 1012 1012
  • Page 1013 1013
  • Page 1014 1014
  • Page 1015 1015
  • Page 1016 1016
  • Page 1017 1017
  • Page 1018 1018
  • Page 1019 1019
  • Page 1020 1020
  • Page 1021 1021
  • Page 1022 1022
  • Page 1023 1023
  • Page 1024 1024
  • Page 1025 1025
  • Page 1026 1026
  • Page 1027 1027
  • Page 1028 1028
  • Page 1029 1029
  • Page 1030 1030
  • Page 1031 1031
  • Page 1032 1032
  • Page 1033 1033
  • Page 1034 1034
  • Page 1035 1035
  • Page 1036 1036
  • Page 1037 1037
  • Page 1038 1038
  • Page 1039 1039
  • Page 1040 1040
  • Page 1041 1041
  • Page 1042 1042
  • Page 1043 1043
  • Page 1044 1044
  • Page 1045 1045
  • Page 1046 1046
  • Page 1047 1047
  • Page 1048 1048
  • Page 1049 1049
  • Page 1050 1050
  • Page 1051 1051
  • Page 1052 1052
  • Page 1053 1053
  • Page 1054 1054
  • Page 1055 1055
  • Page 1056 1056
  • Page 1057 1057
  • Page 1058 1058
  • Page 1059 1059
  • Page 1060 1060
  • Page 1061 1061
  • Page 1062 1062
  • Page 1063 1063
  • Page 1064 1064
  • Page 1065 1065
  • Page 1066 1066
  • Page 1067 1067
  • Page 1068 1068
  • Page 1069 1069
  • Page 1070 1070
  • Page 1071 1071
  • Page 1072 1072
  • Page 1073 1073
  • Page 1074 1074
  • Page 1075 1075
  • Page 1076 1076
  • Page 1077 1077
  • Page 1078 1078
  • Page 1079 1079
  • Page 1080 1080
  • Page 1081 1081
  • Page 1082 1082
  • Page 1083 1083
  • Page 1084 1084
  • Page 1085 1085
  • Page 1086 1086
  • Page 1087 1087
  • Page 1088 1088
  • Page 1089 1089
  • Page 1090 1090
  • Page 1091 1091
  • Page 1092 1092
  • Page 1093 1093
  • Page 1094 1094
  • Page 1095 1095
  • Page 1096 1096
  • Page 1097 1097
  • Page 1098 1098
  • Page 1099 1099
  • Page 1100 1100
  • Page 1101 1101
  • Page 1102 1102
  • Page 1103 1103
  • Page 1104 1104
  • Page 1105 1105
  • Page 1106 1106
  • Page 1107 1107
  • Page 1108 1108
  • Page 1109 1109
  • Page 1110 1110
  • Page 1111 1111
  • Page 1112 1112
  • Page 1113 1113
  • Page 1114 1114
  • Page 1115 1115
  • Page 1116 1116
  • Page 1117 1117
  • Page 1118 1118
  • Page 1119 1119
  • Page 1120 1120
  • Page 1121 1121
  • Page 1122 1122
  • Page 1123 1123
  • Page 1124 1124
  • Page 1125 1125
  • Page 1126 1126
  • Page 1127 1127
  • Page 1128 1128
  • Page 1129 1129
  • Page 1130 1130
  • Page 1131 1131
  • Page 1132 1132
  • Page 1133 1133
  • Page 1134 1134
  • Page 1135 1135
  • Page 1136 1136
  • Page 1137 1137
  • Page 1138 1138
  • Page 1139 1139
  • Page 1140 1140
  • Page 1141 1141
  • Page 1142 1142
  • Page 1143 1143
  • Page 1144 1144
  • Page 1145 1145
  • Page 1146 1146
  • Page 1147 1147
  • Page 1148 1148
  • Page 1149 1149
  • Page 1150 1150
  • Page 1151 1151
  • Page 1152 1152
  • Page 1153 1153
  • Page 1154 1154
  • Page 1155 1155
  • Page 1156 1156
  • Page 1157 1157
  • Page 1158 1158
  • Page 1159 1159
  • Page 1160 1160
  • Page 1161 1161
  • Page 1162 1162
  • Page 1163 1163
  • Page 1164 1164
  • Page 1165 1165
  • Page 1166 1166
  • Page 1167 1167
  • Page 1168 1168
  • Page 1169 1169
  • Page 1170 1170
  • Page 1171 1171
  • Page 1172 1172
  • Page 1173 1173
  • Page 1174 1174
  • Page 1175 1175
  • Page 1176 1176
  • Page 1177 1177
  • Page 1178 1178
  • Page 1179 1179
  • Page 1180 1180
  • Page 1181 1181
  • Page 1182 1182
  • Page 1183 1183
  • Page 1184 1184
  • Page 1185 1185
  • Page 1186 1186
  • Page 1187 1187
  • Page 1188 1188
  • Page 1189 1189
  • Page 1190 1190
  • Page 1191 1191
  • Page 1192 1192
  • Page 1193 1193
  • Page 1194 1194
  • Page 1195 1195
  • Page 1196 1196
  • Page 1197 1197
  • Page 1198 1198
  • Page 1199 1199
  • Page 1200 1200
  • Page 1201 1201
  • Page 1202 1202
  • Page 1203 1203
  • Page 1204 1204
  • Page 1205 1205
  • Page 1206 1206
  • Page 1207 1207
  • Page 1208 1208
  • Page 1209 1209
  • Page 1210 1210
  • Page 1211 1211
  • Page 1212 1212
  • Page 1213 1213
  • Page 1214 1214
  • Page 1215 1215
  • Page 1216 1216
  • Page 1217 1217
  • Page 1218 1218
  • Page 1219 1219
  • Page 1220 1220
  • Page 1221 1221
  • Page 1222 1222
  • Page 1223 1223
  • Page 1224 1224
  • Page 1225 1225
  • Page 1226 1226
  • Page 1227 1227
  • Page 1228 1228
  • Page 1229 1229
  • Page 1230 1230
  • Page 1231 1231
  • Page 1232 1232
  • Page 1233 1233
  • Page 1234 1234
  • Page 1235 1235
  • Page 1236 1236
  • Page 1237 1237
  • Page 1238 1238
  • Page 1239 1239
  • Page 1240 1240
  • Page 1241 1241
  • Page 1242 1242
  • Page 1243 1243
  • Page 1244 1244
  • Page 1245 1245
  • Page 1246 1246
  • Page 1247 1247
  • Page 1248 1248
  • Page 1249 1249
  • Page 1250 1250
  • Page 1251 1251
  • Page 1252 1252
  • Page 1253 1253
  • Page 1254 1254
  • Page 1255 1255
  • Page 1256 1256
  • Page 1257 1257
  • Page 1258 1258
  • Page 1259 1259
  • Page 1260 1260
  • Page 1261 1261
  • Page 1262 1262
  • Page 1263 1263
  • Page 1264 1264
  • Page 1265 1265
  • Page 1266 1266
  • Page 1267 1267
  • Page 1268 1268
  • Page 1269 1269
  • Page 1270 1270
  • Page 1271 1271
  • Page 1272 1272
  • Page 1273 1273
  • Page 1274 1274
  • Page 1275 1275
  • Page 1276 1276
  • Page 1277 1277
  • Page 1278 1278
  • Page 1279 1279
  • Page 1280 1280
  • Page 1281 1281
  • Page 1282 1282
  • Page 1283 1283
  • Page 1284 1284
  • Page 1285 1285
  • Page 1286 1286
  • Page 1287 1287
  • Page 1288 1288
  • Page 1289 1289
  • Page 1290 1290
  • Page 1291 1291
  • Page 1292 1292
  • Page 1293 1293
  • Page 1294 1294
  • Page 1295 1295
  • Page 1296 1296

NXP MPC8247 Reference guide

Type
Reference guide
This manual is also suitable for

Ask a question and I''ll find the answer in the document

Finding information in a document is now easier with AI