N720V5
Hardware User Guide
Issue 1.2
Date 2020-09-18
Neoway Product Document
N720V5
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
i
Copyright © Neoway Technology Co., Ltd 2020. All rights reserved.
No part of this document may be reproduced or transmitted in any form or by any means without prior
written consent of Neoway Technology Co., Ltd.
is the trademark of Neoway Technology Co., Ltd.
All other trademarks and trade names mentioned in this document are the property of their respective
holders.
Notice
This document provides guide for users to use N720V5.
This document is intended for system engineers (SEs), development engineers, and test engineers.
THIS GUIDE PROVIDES INSTRUCTIONS FOR CUSTOMERS TO DESIGN THEIR APPLICATIONS.
PLEASE FOLLOW THE RULES AND PARAMETERS IN THIS GUIDE TO DESIGN AND COMMISSION.
NEOWAY WILL NOT TAKE ANY RESPONSIBILITY OF BODILY HURT OR ASSET LOSS CAUSED BY
IMPROPER OPERATIONS.
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE DUE TO
PRODUCT VERSION UPDATE OR OTHER REASONS.
EVERY EFFORT HAS BEEN MADE IN PREPARATION OF THIS DOCUMENT TO ENSURE ACCURACY
OF THE CONTENTS, BUT ALL STATEMENTS, INFORMATION, AND RECOMMENDATIONS IN THIS
DOCUMENT DO NOT CONSTITUTE A WARRANTY OF ANY KIND, EXPRESS OR IMPLIED.
Neoway provides customers complete technical support. If you have any question, please contact your
account manager or email to the following email addresses:
Website: http://www.neoway.com
N720V5
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
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Contents
1 About N720V5 ........................................................................................... 1
1.1 Product Overview ......................................................................................................................... 1
1.2 Block Diagram .............................................................................................................................. 1
1.3 Basic Features ............................................................................................................................. 2
2 Module Pins ............................................................................................... 4
2.1 Pad Layout ................................................................................................................................... 4
2.2 Pin Description ............................................................................................................................. 6
3 Application Interfaces .............................................................................. 11
3.1 Power Interfaces ......................................................................................................................... 11
3.1.1 VBAT ................................................................................................................................... 11
3.1.2 VDDIO_1P8 ....................................................................................................................... 16
3.1.3 VDDIO_3P3 ....................................................................................................................... 16
3.2 Control Interfaces ....................................................................................................................... 17
3.2.1 PWRKEY_N ...................................................................................................................... 17
3.2.2 PWRKEY ........................................................................................................................... 20
3.2.3 RESET_N .......................................................................................................................... 20
3.3 Peripheral Interfaces .................................................................................................................. 22
3.3.1 USB ................................................................................................................................... 22
3.3.2 UART ................................................................................................................................. 23
3.3.3 USIM .................................................................................................................................. 27
3.3.4 *PCM ................................................................................................................................. 29
3.4 RF Interface ................................................................................................................................ 30
3.4.1 ANT_MAIN/ANT_DIV ........................................................................................................ 30
3.4.2 Antenna Assembling .......................................................................................................... 32
3.5 Other Interfaces ......................................................................................................................... 34
3.5.1 ADC ................................................................................................................................... 34
3.5.2 SLEEP ............................................................................................................................... 34
3.5.3 NET_LIGHT ....................................................................................................................... 36
3.5.4 RING .................................................................................................................................. 37
3.5.5 USB_BOOT ....................................................................................................................... 37
4 Electric Features and Reliability .............................................................. 39
4.1 Electric Features ........................................................................................................................ 39
4.2 Temperature Features ................................................................................................................ 39
4.3 ESD Protection ........................................................................................................................... 39
5 RF Features ............................................................................................. 41
5.1 Operating Bands ........................................................................................................................ 41
5.2 TX Power and RX Sensitivity ..................................................................................................... 41
6 Mechanical Features ............................................................................... 43
6.1 Dimensions ................................................................................................................................. 43
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6.2 Label ........................................................................................................................................... 44
6.3 Packing ....................................................................................................................................... 44
6.3.1 Tray .................................................................................................................................... 44
6.3.2 Moisture ............................................................................................................................. 46
7 Mounting N720V5 onto the Application Board ......................................... 47
7.1 Bottom Dimensions .................................................................................................................... 47
7.2 Application Foot Print ................................................................................................................. 48
7.3 Stencil ......................................................................................................................................... 48
7.4 Solder Paste ............................................................................................................................... 48
7.5 SMT Furnace Temperature Curve .............................................................................................. 49
8 Safety Recommendations ....................................................................... 51
A Conformity and Compliance .................................................................... 52
B Abbreviation ............................................................................................ 53
N720V5
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
iv
Table of Figures
Figure 1-1 Block diagram ................................................................................................................... 2
Figure 2-1 Pin definition of N720V5 ................................................................................................... 5
Figure 3-1 Recommended design 1 ................................................................................................. 12
Figure 3-2 Recommended design 2 ................................................................................................. 13
Figure 3-3 Recommended design 3 ................................................................................................. 14
Figure 3-4 Recommended design 4 ................................................................................................. 15
Figure 3-5 Reference design of startup controlled by button ........................................................... 17
Figure 3-6 Reference design of startup controlled by MCU ............................................................. 18
Figure 3-7 Startup timing .................................................................................................................. 19
Figure 3-8 Shutdown timing ............................................................................................................. 20
Figure 3-9 Reference design of startup controlled by high level ...................................................... 20
Figure 3-10 Reset controlled by button ............................................................................................ 21
Figure 3-11 Reset circuit with triode separating ............................................................................... 21
Figure 3-12 Reset timing of N720V5 ................................................................................................ 22
Figure 3-13 USB connection ............................................................................................................ 23
Figure 3-14 UART connection .......................................................................................................... 24
Figure 3-15 Recommended level shifting circuit 1 ........................................................................... 25
Figure 3-16 Recommended level shifting circuit 2 ........................................................................... 26
Figure 3-17 Recommended level shifting circuit 3 ........................................................................... 27
Figure 3-18 Reference design of USIM card interface ..................................................................... 28
Figure 3-19 PCM connection ........................................................................................................... 29
Figure 3-20 L network ...................................................................................................................... 30
Figure 3-21 T network ...................................................................................................................... 30
Figure 3-22 Pi network ..................................................................................................................... 31
Figure 3-23 Recommended RF PCB design ................................................................................... 31
Figure 3-24 Specifications of MM9329-2700RA1 ............................................................................ 32
Figure 3-25 RF connections ............................................................................................................. 33
N720V5
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
v
Figure 3-26 Antenna layout .............................................................................................................. 33
Figure 3-27 Layout around the antenna ........................................................................................... 34
Figure 3-28 Process of entering sleep mode ................................................................................... 35
Figure 3-29 Incoming call service process ....................................................................................... 35
Figure 3-30 Outgoing call service process ....................................................................................... 35
Figure 3-31 Process of exiting from sleep mode ............................................................................. 36
Figure 3-32 Driving LED with a triode .............................................................................................. 36
Figure 3-33 Pulse wave for an incoming call ................................................................................... 37
Figure 3-34 RING indicator for SMS ................................................................................................ 37
Figure 3-35 Reference design of USB_BOOT ................................................................................. 38
Figure 6-1 N720V5 dimensions (Unit: mm) ...................................................................................... 43
Figure 6-2 N720V5 tray .................................................................................................................... 45
Figure 6-3 N720V5 vacuum bag ...................................................................................................... 45
Figure 7-1 N720V5 bottom dimensions (Unit: mm) .......................................................................... 47
Figure 7-2 Recommended PCB foot print (Unit: mm) ...................................................................... 48
Figure 7-3 SMT furnace temperature curve ..................................................................................... 49
N720V5
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
vi
Table of Tables
Table 1-1 Variant and frequency bands .............................................................................................. 1
Table 2-1 IO definition ........................................................................................................................ 6
Table 4-1 Electric features of N720V5 ............................................................................................. 39
Table 4-2 Temperature features of N720V5 ..................................................................................... 39
Table 4-3 N720V5 ESD protection ................................................................................................... 40
Table 5-1 Operating bands of N720V5 ............................................................................................. 41
Table 5-2 RF TX power of N720V5 .................................................................................................. 41
Table 5-3 RX sensitivity of N720V5 GSM ........................................................................................ 42
Table 5-4 RX sensitivity of N720V5 UMTS ...................................................................................... 42
Table 5-5 RX sensitivity of N720V5 Cat4 ......................................................................................... 42
N720V5
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
vii
About This Document
Scope
This document is applicable to N720V5 series.
It defines the features, indicators, and test standards of the N720V5 module and provides reference
for the hardware design of each interface.
Audience
This document is intended for system engineers (SEs), development engineers, and test engineers.
Change History
Issue
Date
Change
Changed By
1.0
2018-05
Initial draft
Tony Zhao
1.1
2018-08
⚫ Modified 83rd pin to NET_LIGHT and 80th pin to RESERVED
⚫ Modified temperature ranges
Jerry Xiao
1.2
2018-09
⚫ Added LTE B8
⚫ Modified description
Jerry Xiao
Conventions
Symbol
Indication
This warning symbol means danger. You are in a situation that could cause fatal
device damage or even bodily damage.
Means reader be careful. In this situation, you might perform an action that could
result in module or product damages.
N720V5
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
viii
Means note or tips for readers to use the module
Related Documents
Neoway_N720V5_Datasheet
Neoway_N720V5_Product_Specifications
Neoway_N720V5_AT_Command_Mannual
Neoway_N720V5_EVK_User_Guide
N720V5
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
1
1 About N720V5
1.1 Product Overview
N720V5 is an industrial-grade LTE module that supports LTE-FDD, LTE-TDD, WCDMA, and GSM
cellular networks.
N720V5 includes only one variant by now. Table 1-1 lists the variant and frequency bands supported.
Table 1-1 Variant and frequency bands
Function
Version
Category
Band
GNSS
N720V5
CN
Cat4
LTE FDD: B1, B3, B5, B8
LTE TDD:B38, B39, B40, B41
UMTS: B1, B8
GSM/GPRS/EDGE: 900/1800 MHz
Not supported
N720V5 adopts 100-pin LGA package and its dimensions are 30 mm x 28 mm x 2.8 mm. With
industrial-grade performance, it is well applicable to electrical terminals, PoC terminals, POS, and
other IoT terminals.
1.2 Block Diagram
N720V5 consists of the following functionality modules:
⚫ Baseband
⚫ Crystal oscillator
⚫ Power management unit
⚫ Digital interfaces (USIM, PCM, UART)
⚫ Analog interfaces (ADC, USB)
⚫ RF section
N720V5
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
2
Figure 1-1 Block diagram
VBAT Power
Manager RF transceiver
RF Section
Base Band
Digital Interface
USBUART
SIM
PC
ANT_MAIN ANT_AUX
PWRKEY
RESET
ADC
USIM PCM
26M
crystal
Flash
Analog Inteface
1.3 Basic Features
Parameter
Description
Physical features
Dimensions: (30.0±0.1) mm × (28.0±0.1) mm × (2.8±0.1) mm
Package: 100-pin LGA
Weight: around 5.1 g
Temperature ranges
Operating: -40 °C to +85 °C 1
1
When the module work at a temperature between -40 °C and -30 °C or between +75 °C and +85 °C , its RF
performance might degrade.
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Hardware User Guide
Copyright © Neoway Technology Co., Ltd
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Storage: -40 °C to +90 °C
Power supply
VBAT: 3.3V to 4.3V, TYP: 3.8V
Current
Sleep: < 8 mA
Idle: < 31 mA
MIPS processor
ARM 946 processor
Main frequency: 0.8 GHz
128kB L2 cache
Memory
RAM: 32 MB
ROM: 128 MB
Band
See Table 1-1
Wireless rate
GPRS: Max 85.6 Kbit/s(DL) / Max 85.6 Kbit/s(UL)
EDGE: Max 236.8 Kbit/s(DL) / Max 236.8 Kbit/s(UL)
WCDMA: DC-HSPA+, Max 42 Mbit/s(DL)/Max 5.76 Mbit/s(UL)
FDD-LTE: non-CA cat4, Max 150 Mbit/s(DL)/Max 50 Mbit/s (UL)
TDD-LTE: non-CA cat4, Max 150 Mbit/s(DL)/Max 50 Mbit/s (UL)
Transmit power
EGSM900: +33 dBm (Power Class 4)
DCS1800: +30 dBm (Power Class 1)
EDGE 900 MHz: +27 dBm (Power Class E2)
EDGE1800 MHz: +26 dBm (Power Class E2)
UMTS: +23 dBm (Power Class 3)
LTE: +23 dBm (Power Class 3)
Application Interfaces
2G/3G/4G antenna, 4G diversity antenna, 50 Ω characteristic impedance
Two UART interfaces, at most 3.6 Mbit/s
One USIM interface, 1.8 V/3 V
One USB2.0 high-speed interface
One 12-bit ADC interface, detectable voltage ranging from 0 V to 1.4V
One PCM interface
N720V5
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
5
Figure 2-1 Pin definition of N720V5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
97 98
100 99
GND
RESERVED
POWER PWEKEY
/RESET USIM USB
UART
ANT OTHERS
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
GND
RESERVED
RESERVED
GND
RESERVED
RESERVED
GND
RING
*PCM_SYNC
*PCM_DIN
*PCM_DOUT
*PCM_CLK
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
UART2_CTS
UART2_RTS
VDDIO_3P3
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
*I2S_MCLK
RESERVED
RESERVED
RESERVED
RESERVED
DEBUG_UART1_TXD
DEBUG_UART1_RXD
RESERVED
RESERVED
RESERVED
VBAT
VBAT
VBAT
GND
GND
RESET_N
PWRKEY_N
PWRKEY
USIM_VCC
USIM_DATA
USIM_CLK
USIM_RESET
USIM_DET
USB_VBUS
USB_DM
USB_DP
RESERVED
GND
VDDIO_1P8
UART2_TXD
UART2_RXD
USB_BOOT
RESERVED
GND
ANT_DIV
GND
RESERVED
GND
RESERVED
ADC
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
NET_LIGHT
RESERVED
RESERVED
RESERVED
SLEEP
RESERVED
GND
ANT_MAIN
GND
GND GND
GND GND
GND GND
GND GND
*PCM
*PCM: This function is in development phase.
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Hardware User Guide
Copyright © Neoway Technology Co., Ltd
6
2.2 Pin Description
Table 3-1 lists the definition of IO types
Table 2-1 IO definition
IO Type
B
Digital input/output, COMS logic level
DO
Digital output, COMS logic level
DI
Digital input, COMS logic level
PO
Power output
PI
Power supply input
AO
Analog output
AI
Analog input
AIO
Analog input/output
Level Feature
P1
Dual-voltage USIM interface
voltage, 1.8V/3.0V
1.8 V level feature:
VIH=1.26~2.1 V
VIL=-0.3~0.54 V
VOH=1.44~1.8 V
VOL=0~0.36 V
3.0 V level feature
VIH=2~3.3 V
VIL=-0.3~0.57 V
VOH=2.4~3.0 V
VOL=0~0.6 V
P3
1.8V digital IO
VIH =1.26~2.1 V, VIL = -0.3~0.54 V
VOH =1.44~1.8 V, VOL=0~0.36 V
Table 2-2 Pin description
Signal
Pin
I/O
Function
Level
Feature
Remarks
VBAT
27,
28,
29
PI
Main power
supply input
Vmax=4.3 V
Vmin=3.3 V
Vnorm=3.8 V
Requires at most 2A from
external power supply
VDDIO _1P8
45
PO
1.8 V power
output
Vnorm=1.8 V
Imax=50 mA
Used only for level
shifting.
Leave this pin floating if it
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Hardware User Guide
Copyright © Neoway Technology Co., Ltd
7
is not used.
VDDIO _3P3
53
PO
3.3 V power
output
Vnorm=3.3 V
Imax=100 mA
Used only for level
shifting.
Leave this pin floating if it
is not used.
GND
1, 14, 17, 20, 26, 30, 31, 44, 49, 74, 75, 77, 91,
93, 95, 97, 98, 99, 100
Ensure that all GND pins
are connected to the
ground plane.
RESET_N
32
DI
Module reset
input
VIH max=VBAT
- 0.3 V
VIL =0~1.8 V
Triggered by negative
pulse
Leave this pin floating if it
is not used.
It is connected to VBAT
through an internal
pull-up resistor and its
default output level is
equal to VBAT.
PWRKEY_N
33
DI
Module ON/OFF
control
VIH max=VBAT
- 0.3 V
VIL =0~1.8V
Triggered by low level
Leave this pin floating if it
is not used.
It is connected to VBAT
through an internal
pull-up resistor and its
default output level is
equal to VBAT.
PWRKEY
34
DI
Module ON/OFF
control
VIH min=1.1 V
VIH norm=1.8 V
VIH max=VBAT
- 0.3 V
Triggered by high level
Leave this pin floating if it
is not used
Status indication
SLEEP
79
DI
Sleep mode
control
P3
Triggered by low level
Leave this pin floating if it
is not used
RING
13
DO
Startup/incoming
call or SMS
indicator
P3
Leave this pin floating if it
is not used.
NET_LIGHT
83
DO
Network status
indicator
P3
Leave this pin floating if it
is not used.
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UART1 port
DEBUG_UART1_TXD
69
DO
Data
transmitting
P3
Used to capture logs
Leave this pin floating if it
is not used.
DEBUG_UART1_RXD
70
DI
Data receiving
P3
UART2 port
UART2_RTS
52
DO
Request to send
P3
Leave this pin floating if it
is not used.
UART2_CTS
51
DI
Clear to send
P3
Leave this pin floating if it
is not used.
UART2_RXD
47
DI
Data receiving
P3
Used for data
transmission. Leave this
pin floating if it is not
used.
UART2_TXD
46
DO
Data
transmitting
P3
USIM interface
USIM_VCC
35
PO
USIM power
output
1.8V USIM:
Vmin=1.2 V
Vmax=1.9 V
3.0V USIM:
Vmin=2.5 V
Vmax=3.0 V
IOmax =50 mA
The module selects 1.8 V
or 3.0 V automatically.
USIM_DATA
36
DIO
USIM data IO
P1
Connect it to USIM_VCC
through a 10 kΩ pull-up
resistor.
USIM_CLK
37
DO
USIM clock
P1
USIM_RESET
38
DO
USIM reset
P1
USIM_DET
39
DI
USIM detection
P3
USB interface
USB_VBUS
40
PI
Voltage
detection
Vmin=3.3 V
Vmax=5.2 V
Vnorm=5 V
Used for firmware
download and data
transmission.
Routed DM and DP
signals in differential
mode, control impedance
USB_DM
41
AIO
USB data
negative signal
In
compliance
with USB2.0
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USB_DP
42
AIO
USB data
positive signal
In
compliance
with USB2.0
of 90 Ω
Leave this pin floating if it
is not used.
ADC interface
ADC
89
AI
Analog-to-digital
signal
conversion
Vmax=1.4V;
Vmin=0V
12-bit, detectable voltage
ranging from 0V to 1.4 V
Leave this pin floating if it
is not used.
*PCM interface
*PCM_SYNC
12
B
PCM
synchronous
signal
P3
Multiplexing as I2S_WS
Leave this pin floating if it
is not used
*PCM_CLK
9
DO
PCM clock
signal
P3
Multiplexing as
I2S_SCLK
Leave this pin floating if it
is not used
*PCM_DIN
11
DI
PCM data
receiving
P3
Multiplexing as I2S_RX
Leave this pin floating if it
is not used
*PCM_DOUT
10
DO
PCM data
transmitting
P3
Multiplexing as I2S_TX
Leave this pin floating if it
is not used
*I2S_MCLK
64
DO
I2S main clock
P3
The default frequency is
26 MHz.
Leave this pin floating if it
is not used
RF Interface
ANT_MAIN
76
Main antenna
50 Ω impedance for
traces
ANT_DIV
94
Diversity
antenna
50 Ω impedance for
traces
Forcible download control interface
USB_BOOT
48
DI
Forcible
download
control
P3
Short connect to the
ground.
Pull it low for less 5
seconds.
N720V5
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
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Trace length should not
be longer than 30 mm.
Junction capacitor of
ESD protector should not
be larger than 20 pF.
The module enters
download mode if it is
connected through USB.
Leave this pin floating if it
is not used.
RESERVED
2, 3, 4, 5, 6, 7, 8, 15, 16, 18, 19, 21, 22, 23, 24,
25, 43, 50, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
65, 66, 67, 68, 71, 72, 73, 80, 81, 82, 84, 85, 86,
87, 88, 90, 92, 96
Leave these pins floating.
Do not use them or
connect to ground.
*This function is in development phrase.
N720V5
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
11
3 Application Interfaces
N720V5 provides power supply, control, communications, peripheral, audio, RF, and other interfaces
to meet customer requirements in different application scenarios.
This chapter describes how to design each interface and provides reference designs and guidelines.
3.1 Power Interfaces
Schematic design and PCB layout of power supply are the most critical process in application design
and determine the performance of customers' applications. Please read the design guidelines of
power supply and comply with the correct design principles to obtain the optimal circuit performance.
Signal
Pin
I/O
Function
Remarks
VBAT
27, 28, 29
PI
Main power supply input
3.3 V to 4.3 V (TYP: 3.8 V)
VDDIO_1P8
45
PO
1.8 V power output
Output 50 mA at most, used only for
level shifting.
Add ESD protector when using this pin.
VDDIO_3P3
53
PO
3.3 V power output
Output 100 mA at most, used only for
level shifting.
Add ESD protector when using this pin.
GND
1, 14, 17, 20, 26, 30, 31, 44, 49, 74, 75, 77,
91, 93, 95, 97, 98, 99, 100
Ensure that all GND pins are connected
to the ground.
3.1.1 VBAT
The power supply design consists of two parts: schematic design and PCB layout.
Schematic Design
Design the circuit of the power supply for N720V5 based on the input voltage you choose. Generally
there are three types of input voltages:
⚫ 3.3 V to 4.3 V (3.8 V typically, output by cellphone battery)
⚫ 4.3 V to 5.5 V (5.0 V typically, output by computer through USB)
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