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Hardware User Guide
Issue 1.4 Date 2019-10-22
A70 Series Hardware User Guide
Copyright
Copyright © Neoway Technology Co., Ltd
i
Copyright © Neoway Technology Co., Ltd 2019. All rights reserved.
No part of this document may be reproduced or transmitted in any form or by any means without prior written
consent of Neoway Technology Co., Ltd.
is the trademark of Neoway Technology Co., Ltd.
All other trademarks and trade names mentioned in this document are the property of their respective
holders.
Notice
This document provides guide for users to use A70 Series.
This document is intended for system engineers (SEs), development engineers, and test engineers.
THIS GUIDE PROVIDES INSTRUCTIONS FOR CUSTOMERS TO DESIGN THEIR APPLICATIONS.
PLEASE FOLLOW THE RULES AND PARAMETERS IN THIS GUIDE TO DESIGN AND COMMISSION.
NEOWAY WILL NOT TAKE ANY RESPONSIBILITY OF BODILY HURT OR ASSET LOSS CAUSED BY
IMPROPER OPERATIONS.
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE DUE TO
PRODUCT VERSION UPDATE OR OTHER REASONS.
EVERY EFFORT HAS BEEN MADE IN PREPARATION OF THIS DOCUMENT TO ENSURE ACCURACY
OF THE CONTENTS, BUT ALL STATEMENTS, INFORMATION, AND RECOMMENDATIONS IN THIS
DOCUMENT DO NOT CONSTITUTE A WARRANTY OF ANY KIND, EXPRESS OR IMPLIED.
Neoway provides customers complete technical support. If you have any question, please contact your
account manager or email to the following email addresses:
Website: http://www.neoway.com
A70 Series Hardware User Guide
Contents
Copyright © Neoway Technology Co., Ltd
ii
Contents
1 About A70 Series .................................................................................... 12
1.1 Product Overview ....................................................................................................................... 12
1.2 Block Diagram ............................................................................................................................ 15
1.3 Basic Features ........................................................................................................................... 15
2 Module Pins ........................................................................................... 18
2.1 Pad Layout ................................................................................................................................. 18
2.2 Pin Description ........................................................................................................................... 19
3 Application Interfaces ............................................................................. 29
3.1 Power Interfaces ........................................................................................................................ 29
3.1.1 VBAT_BB and VBAT_RF ................................................................................................... 30
3.1.2 VDD_1P8 ........................................................................................................................... 35
3.1.3 Voltage Drop Detection ..................................................................................................... 36
3.2 Control Interfaces ....................................................................................................................... 37
3.2.1 PWRKEY_N ...................................................................................................................... 37
3.2.2 RESET_N .......................................................................................................................... 39
3.3 Peripheral Interfaces .................................................................................................................. 41
3.3.1 USB ................................................................................................................................... 42
3.3.2 HSIC .................................................................................................................................. 44
3.3.3 USIM .................................................................................................................................. 45
3.3.4 SDC/eMMC ....................................................................................................................... 46
3.3.5 UART ................................................................................................................................. 52
3.3.6 I2S/PCM ............................................................................................................................ 55
3.3.7 SPI ..................................................................................................................................... 61
3.3.8 I2C ..................................................................................................................................... 63
3.4 Network and Connection ............................................................................................................ 67
3.4.1 Ethernet ............................................................................................................................. 67
3.4.2 SDIO/WLAN ...................................................................................................................... 69
3.4.3 Bluetooth ........................................................................................................................... 73
3.5 Audio Interface ........................................................................................................................... 74
3.5.1 Audio Circuit ...................................................................................................................... 74
3.5.2 AVDD_1P8 ......................................................................................................................... 75
3.5.3 Analog Audio Input Interfaces ............................................................................................ 75
3.5.4 Analog Audio Output Interfaces ......................................................................................... 77
3.6 RF Interface ............................................................................................................................... 80
3.6.1 ANT_MAIN/ANT_DIV antenna interface ........................................................................... 80
3.6.2 ANT_GNSS Interface ........................................................................................................ 83
3.6.3 Antenna Detection ............................................................................................................. 86
3.6.4 Antenna Switch .................................................................................................................. 91
3.6.5 Antenna Assembling .......................................................................................................... 92
3.7 GPIO .......................................................................................................................................... 94
A70 Series Hardware User Guide
Contents
Copyright © Neoway Technology Co., Ltd
iii
3.8 MUX Interfaces .......................................................................................................................... 95
3.9 Other Interfaces ......................................................................................................................... 98
3.9.1 GNSS_LNA_EN ................................................................................................................ 98
3.9.2 ADC ................................................................................................................................... 98
3.9.3 SLEEP ............................................................................................................................... 98
3.9.4 USB_BOOT ..................................................................................................................... 100
3.9.5 Reserved ......................................................................................................................... 101
4 Electric Feature and Reliability ............................................................. 102
4.1 Electric Features ...................................................................................................................... 102
4.2 Temperature Feature ................................................................................................................ 105
4.3 ESD Protection ......................................................................................................................... 105
5 RF Features ......................................................................................... 107
5.1 Operating Bands ...................................................................................................................... 107
5.2 TX Power and RX Sensitivity ................................................................................................... 108
5.3 GNSS Feature .......................................................................................................................... 109
6 Mechanical Features ............................................................................. 111
6.1 Dimensions................................................................................................................................ 111
6.2 Label .......................................................................................................................................... 112
6.3 Package .................................................................................................................................... 113
6.3.1 Reel .................................................................................................................................. 113
6.3.2 Moisture ............................................................................................................................ 115
7 Mounting A70 onto the Application Board ............................................. 116
7.1 Application Foot Print ................................................................................................................ 116
7.2 Stencil ........................................................................................................................................ 117
7.3 Solder Paste .............................................................................................................................. 117
7.4 SMT Furnace Temperature Curve ............................................................................................. 117
8 Safety Recommendations .................................................................... 119
Conformity and Compliance ................................................................. 120
A.1 Approvals ................................................................................................................................. 120
A.2 Chinese Notice ........................................................................................................................ 120
A.2.1 CCC Class A Digital Device Notice ................................................................................. 120
A.2.2 Environmental Protection Notice ..................................................................................... 120
Key Component List ............................................................................. 121
Abbreviation ......................................................................................... 124
A70 Series Hardware User Guide
Table of Figures
Copyright © Neoway Technology Co., Ltd
iv
Table of Figures
Figure 1-1 Block Diagram ................................................................................................................ 15
Figure 2-1 Pin assignment ............................................................................................................... 18
Figure 3-1 Current peaks and voltage drops ................................................................................... 30
Figure 3-2 Recommended schematic design 1 ............................................................................... 31
Figure 3-3 Recommended schematic design 2 ............................................................................... 32
Figure 3-4 Recommended schematic design 3 ............................................................................... 32
Figure 3-5 Recommended schematic design 4 ............................................................................... 33
Figure 3-6 Reference PCB layout of VBAT_BB and VBAT_RF ....................................................... 35
Figure 3-7 Circuit of voltage drop detection ..................................................................................... 36
Figure 3-8 Reference design of startup controlled by button ........................................................... 37
Figure 3-9 Reference design of startup controlled by MCU ............................................................. 38
Figure 3-10 Reference design of automatic start once powered up ................................................ 38
Figure 3-11 A70 startup/shutdown timing ......................................................................................... 39
Figure 3-12 Reset controlled by button ............................................................................................ 40
Figure 3-13 Reset circuit with triode separating ............................................................................... 40
Figure 3-14 Reset timing of A70....................................................................................................... 40
Figure 3-15 USB connection ............................................................................................................ 42
Figure 3-16 Reference design of USB OTG function ...................................................................... 43
Figure 3-17 HSIC connection ........................................................................................................... 44
Figure 3-18 Reference design of USIM card interface .................................................................... 45
Figure 3-19 SD connection .............................................................................................................. 47
Figure 3-20 eMMC connection ......................................................................................................... 49
Figure 3-21 SDC/eMMC SDR timing ............................................................................................... 50
Figure 3-22 SDC/eMMC DDR timing ............................................................................................... 51
Figure 3-23 UART3 connection ........................................................................................................ 52
Figure 3-24 UART5 connection ........................................................................................................ 52
Figure 3-25 Recommended level shifting circuit 1 ........................................................................... 53
A70 Series Hardware User Guide
Table of Figures
Copyright © Neoway Technology Co., Ltd
v
Figure 3-26 Recommended level shifting circuit 2 ........................................................................... 54
Figure 3-27 Recommended level shifting circuit 3 ........................................................................... 55
Figure 3-28 I2Sconnection ............................................................................................................... 56
Figure 3-29 I2S timing ...................................................................................................................... 57
Figure 3-30 PCM connection ........................................................................................................... 58
Figure 3-31 PCM sync signal timing in primary mode ..................................................................... 58
Figure 3-32 PCM data input timing in primary mode ....................................................................... 59
Figure 3-33 PCM data input timing in primary mode ....................................................................... 59
Figure 3-34 PCM sync signal timing in auxiliary mode .................................................................... 60
Figure 3-35 PCM data input timing in auxiliary mode ...................................................................... 60
Figure 3-36 PCM data output timing in auxiliary mode .................................................................... 60
Figure 3-37 SPI connection .............................................................................................................. 62
Figure 3-38 SPI timing ..................................................................................................................... 62
Figure 3-39 I2C connection .............................................................................................................. 64
Figure 3-40 I2C data transmission ................................................................................................... 64
Figure 3-41 I2C timing ...................................................................................................................... 65
Figure 3-42 SGMII connection ......................................................................................................... 67
Figure 3-43 Connection between MDIO and PHY ........................................................................... 68
Figure 3-44 MDIO input timing ......................................................................................................... 69
Figure 3-45 MDIO output timing ....................................................................................................... 69
Figure 3-46 WLAN connection ......................................................................................................... 70
Figure 3-47 SDIO SDR timing .......................................................................................................... 72
Figure 3-48 SDIO DDR timing.......................................................................................................... 72
Figure 3-49 Bluetooth connection .................................................................................................... 73
Figure 3-50 Audio circuit .................................................................................................................. 75
Figure 3-51 Reference design of differential MIC input ................................................................... 76
Figure 3-52 Reference design of differential EAR output ................................................................ 77
Figure 3-53 Reference design of single-ended EAR output ............................................................ 78
Figure 3-54 Reference design of capacitorless EAR output ............................................................ 79
Figure 3-55 L network ...................................................................................................................... 80
Figure 3-56 T network ...................................................................................................................... 81
A70 Series Hardware User Guide
Table of Figures
Copyright © Neoway Technology Co., Ltd
vi
Figure 3-57 Pi network ..................................................................................................................... 81
Figure 3-58 Recommended RF PCB design 1 ................................................................................ 82
Figure 3-59 Recommended RF PCB design 2 ................................................................................ 82
Figure 3-60 GNSS RF structure ....................................................................................................... 83
Figure 3-61 Reference Design of Passive GNSS Antenna .............................................................. 83
Figure 3-62 Reference design of active GNSS antenna .................................................................. 84
Figure 3-63 Reference layout of GNSS antenna traces .................................................................. 85
Figure 3-64 Reference design of detection of DC terminated antenna ........................................... 86
Figure 3-65 Reference design of antenna detection ........................................................................ 88
Figure 3-66 Reference design of detection of DC grounded antenna ............................................. 89
Figure 3-67 Reference design of active antenna detection ............................................................. 90
Figure 3-68 Circuit of antenna switch in normal situation ................................................................ 91
Figure 3-69 Circuit if antenna switching ........................................................................................... 92
Figure 3-70 Specifications of MM9329-2700RA1 ............................................................................ 93
Figure 3-71 RF connections ............................................................................................................. 93
Figure 3-72 Process of entering sleep mode ................................................................................... 99
Figure 3-73 Incoming call service process ....................................................................................... 99
Figure 3-74 Outgoing call service process ....................................................................................... 99
Figure 3-75 Process of exiting from sleep mode ........................................................................... 100
Figure 3-76 Reference design of USB_BOOT ............................................................................... 100
Figure 6-1 A70 dimensions ............................................................................................................. 111
Figure 6-2 A70 Label ....................................................................................................................... 112
Figure 6-3 A70V2 Label .................................................................................................................. 112
Figure 6-4 A70V3 Label .................................................................................................................. 113
Figure 6-5 A70 reel packaging ........................................................................................................ 114
Figure 6-6 A70 reel dimensions ...................................................................................................... 114
Figure 7-1 Recommended PCB Foot Print ..................................................................................... 116
Figure 7-2 SMT furnace temperature curve .................................................................................... 117
A70 Series Hardware User Guide
Table of Tables
Copyright © Neoway Technology Co., Ltd
vii
Table of Tables
Table 1-1 Hardware Configuration information ................................................................................ 12
Table 1-2 Variant and frequency bands............................................................................................ 13
Table 2-1 IO definition ...................................................................................................................... 19
Table 2-2 Level Feature ................................................................................................................... 19
Table 2-3 Pin Description ................................................................................................................. 20
Table 3-1 VDD_1P8 electrical features ............................................................................................ 35
Table 3-2 VDD_1P8 feature parameters .......................................................................................... 36
Table 3-3 Compliant standards of peripheral interfaces .................................................................. 41
Table 3-4 SD card feature parameters ............................................................................................. 47
Table 3-5 eMMC feature parameters ............................................................................................... 48
Table 3-6 Timing parameters of SDC/eMMC interface .................................................................... 51
Table 3-7 Timing parameters of I2S interface .................................................................................. 57
Table 3-8 PCM work modes ............................................................................................................. 57
Table 3-9 Parameters of PCM timing in primary mode .................................................................... 59
Table 3-10 Parameters of PCM timing in auxiliary mode ................................................................. 61
Table 3-11 Timing parameters of SPI interface ................................................................................ 63
Table 3-12 I2C feature parameters .................................................................................................. 63
Table 3-13 I2C timing parameters (standard mode) ........................................................................ 65
Table 3-14 I2C timing parameters (fast mode) ................................................................................. 66
Table 3-15 I2C timing parameters (fast mode plus) ......................................................................... 66
Table 3-16 SDIO/WLAN feature parameters .................................................................................... 70
Table 3-17 Timing parameters of SDIO/WLAN interface ................................................................. 72
Table 3-18 MUX pins ........................................................................................................................ 95
Table 4-1 Operating conditions of A70 ........................................................................................... 102
Table 4-2 Current consumption of A70 ........................................................................................... 102
Table 4-3 Current features of A70V2 .............................................................................................. 103
Table 4-4 Current features of A70V3 .............................................................................................. 104
A70 Series Hardware User Guide
Table of Tables
Copyright © Neoway Technology Co., Ltd
viii
Table 4-5 Temperature feature of A70 ............................................................................................ 105
Table 4-6 A70 ESD protection ........................................................................................................ 106
Table 5-1 Operating bands of A70.................................................................................................. 107
Table 5-2 RF TX power of A70 ....................................................................................................... 108
Table 5-3 RF RX sensitivity of A70 ................................................................................................. 108
Table 6-1 Label Dimensions ............................................................................................................ 112
A70 Series Hardware User Guide
About This Document
Copyright © Neoway Technology Co., Ltd
ix
About This Document
Scope
This document is applicable to A70 Series.
It defines the features, indicators, and test standards of the modules and provides reference for the
hardware design of each interface.
Audience
This document is intended for system engineers (SEs), development engineers, and test engineers.
Change History
Issue
Date
Change
Changed By
1.0
2017-09
Initial draft
Li Huixiang
1.1
2017-12
⚫ Added WCDMA B5
⚫ Changed the definitions of some pins:
⚫ K2: RESERVED
⚫ L1: RESET_N
⚫ AF20: GPIO_10
⚫ AG21: GPIO_11
⚫ K4: DTR
⚫ C13: GPIO_76
⚫ AF18: DSRC_SLEEP_CLK
⚫ Deleted the description of SHDN_N and modified
DTR description
⚫ Added DC-DC reference circuit, added
connections of HSIC, I2C, and SPI
⚫ Modified EAR single-ended design
⚫ Modified UART reference design, updated
recommended level shifting circuit 2, and added
level shifting circuit 3.
⚫ Added the description of Bluetooth function and
reference design.
⚫ Modified ADC precision to 15 bit
Li Huixiang
A70 Series Hardware User Guide
About This Document
Copyright © Neoway Technology Co., Ltd
x
⚫ Updated internal connection of GPS
⚫ Updated module packaging and recommended
PCB pads
⚫ Changed the usage of some abbreviations: Wi-Fi
to WLAN; SIM to UIM
1.2
2018-03
⚫ Added A70V3
⚫ Added antenna check design and antenna switch
description
⚫ Added connection of GPS LNA
⚫ Added GNSS features
⚫ Added currents in flight mode and sleep mode
⚫ Added operating temperature range and modified
the storage temperature range
⚫ Updated block diagram and reference design of
USB connection
⚫ Updated reference design of SPI connection, and
reference design of TP54340 power supply
⚫ Updated the usage of GPIO_78 and GPIO_79
⚫ Modified the pin numbers of GPIO_10 and
GPIO_11
⚫ Deleted trace requirements for dual-layer PCB and
added trace requirements form some interfaces
⚫ Modified some description.
Li Huixiang
1.3
2018-09
⚫ Modified the pin definition according to Neoway
Module Pin Definition.
⚫ Added variant information
⚫ Deleted IO type of P6 and added P8
⚫ Changed the default function of S4 to GPIO_43
⚫ Modified eMMC features and reference designs
⚫ Added MUX pins
Li Huixiang
1.4
2019-09
⚫ Updated the configurations and the frequency
bands of the variants of A70 series.
⚫ Added the hardware configuration information of
A70 series.
Zheng Chengxing
A70 Series Hardware User Guide
About This Document
Copyright © Neoway Technology Co., Ltd
xi
Conventions
Symbol
Indication
This warning symbol means danger. You are in a situation that could cause fatal
device damage or even bodily damage.
Means reader be careful. In this situation, you might perform an action that could
result in module or product damages.
Means note or tips for readers to use the module
Related Documents
Neoway_A70 Series_Datasheet
Neoway_A70 Series_Product_Specifications
Neoway_A70 Series_AT_Command_Mannual
Neoway_A70 Series_EVK_User_Guide
A70 Series Hardware User Guide
Chapter 1 About A70 Series
Copyright © Neoway Technology Co., Ltd
12
1 About A70 Series
A70 series are a set of automotive-grade LTE modules that are developed on Qualcomm platform.
They supports LTE-FDD, LTE-TDD, WCDMA, TD-SCDMA, CDMA, and GSM cellular networks.
A70 in this document refers to A70, A70V2, and A70V3 if not specified.
1.1 Product Overview
A70 series include multiple variants. Table 1-1 lists the hardware configuration information and Table
1-2 lists the variants and frequency bands supported.
Table 1-1 Hardware Configuration information
A70
A70V2
A70V3
Hardware
Platform
MDM9628 (Automotive-
grade1)
MDM9607 (Industrial-
grade)
MDM9628 (Industrial-
grade)
FLASH
Automotive-grade
Consumer-grade
Industrial-grade
1
Automotive-grade RF: the OEMs of key RF components declare that the component complies with automotive-grade
standard or they can provide PPAP report as required.
A70 Series Hardware User Guide
Chapter 1 About A70 Series
Copyright © Neoway Technology Co., Ltd
13
Table 1-2 Variant and frequency bands
Model
Variant
Category
Band
Baseband
Chipset
RF
GNSS
CODEC
Antenna
Switch
A70
CN
Cat4
LTE FDD: B1, B3, B5, B8, B262
LTE TDD: B34, B38, B39, B40,
B41
TD-SCDMA: B34, B39
UMTS: B1, B5, B8
EV-DO: BC0
CDMA 1x BC0
GSM/GPRS/EDGE: 900/1800
MHz
MDM9628
Automotive-grade
Optional
Optional
Optional
A70V2
CN
Cat4
LTE FDD: B1, B3, B5, B8, B26
LTE TDD: B34, B38, B39, B40,
B41
TD-SCDMA: B34, B39
UMTS: B1, B5, B8
EV-DO: BC0
CDMA 1x BC0
GSM/GPRS/EDGE: 900/1800
MHz
MDM9607
Industrial-grade
Optional
Optional, not
supported by
default
Optional, not
supported by
default
A70V3
CN
Cat4
LTE FDD: B1, B3, B5, B8, B26
LTE TDD: B34, B38, B39, B40,
B41
TD-SCDMA: B34, B39
UMTS: B1, B5, B8
MDM9628
Industrial-grade
Optional
Optional, not
supported by
default
Optional, not
supported by
default
2
The frequency band is optional.
A70 Series Hardware User Guide
Chapter 1 About A70 Series
Copyright © Neoway Technology Co., Ltd
14
EV-DO: BC0
CDMA 1x BC0
GSM/GPRS/EDGE: 900/1800
MHz
A70 adopts 284-pin LGA package and its dimensions are 37 mm x 37 mm x 2.7 mm. With automotive-grade performance, this module is well applicable
to in-vehicle OEM applications.
A70 Series Hardware User Guide
Chapter 1 About A70 Series
Copyright © Neoway Technology Co., Ltd
15
1.2 Block Diagram
A70 consists of the following functionality modules:
⚫ Baseband and memory
⚫ Crystal oscillation and power (VBAT_BB, VBAT_RF, VDD_1P8, AVDD_1P8, voltage drop
detection)
⚫ Digital interfaces (USIM, USB, HSIC, UART, SPI, SDIO, SDC/eMMC, GPIO, I2C, I2S/PCM and
SGMII)
⚫ Analog interfaces (ADC)
⚫ Analog audio interfaces (optional)
⚫ RF interfaces (main antenna, diversity antenna, GNSS antenna, antenna switch)
Figure 1-1 Block Diagram
1.3 Basic Features
Parameter
Description
Physical features
⚫ Dimensions: (37.0±0.1) mm × (37.0±0.1) mm × (2.7±0.2) mm
⚫ Package: 284-pin LGA
Base
Band
RF transceiver
RF Section
Power
Manager
MCP
VBAT_BB
VBAT _RF
CODEC
(Optional)
Interface
ADC AUDIO
(Optional)
Control
I2S
PCM
I2C
MAIN DIV GNSS
GPIO
SDC
eMMC
SDIOSPI
UART
HSICUSB
SGMII
MDIO
USIM2
USIM1
LDO
LDO
(Optional)
VDD _1P8
EN
Power Drop
Dectector
VBAT_BB
Switch Switch
AVDD_1P8
AVDD_1P8
(Optional)
(Optional)
19.2MHz
Crystal
A70 Series Hardware User Guide
Chapter 1 About A70 Series
Copyright © Neoway Technology Co., Ltd
16
⚫ Weight: around 8.4g
Temperature ranges
Operating: -30°C to +75°C
Extended: -40°C to +85°C3
Storage: -45°C to +105°C
Operating voltage
VBAT_BB/VBAT_RF: 3.4V to 4.2V, TYP: 3.8V
Current4
Flight mode
1.24mA
Sleep Mode
GSM DRX=6: 2.2mA
GSM DRX=9: 1.45mA
WCDMA DRX=2: 2 mA
WCDMA DRX=9: 1.54mA
LTE (Paging Cycle 320ms): 6.5 mA
LTE (Paging Cycle 2.56s): 1.67mA
Active
VBAT_BB: 1.5A Max
VBAT_RF: 2.5A Max
VBAT_BB+VBAT_RF: 3A Max5
MIPS processor
ARM Cortex-A7 processor, 1.3 GHz main frequency, 256kB L2 cache
Memory
RAM: 256MB
ROM: 512MB
Band
See Table 1-2.
Wireless data rate
GPRS: Max 85.6 Kbit/s(DL) / Max 85.6 Kbit/s(UL)
EDGE: Max 236.8 Kbit/s(DL) / Max 236.8 Kbit/s(UL)
CDMA2000@1x, 1xEV-DOrA: Max 3.1 Mbit/s (DL) / Max 1.8 Mbit/s (UL)
TD-SCDMA: Max 4.2 Mbit/s (DL)/Max 2.2 Mbit/s (UL)
WCDMA: DC-HSPA+, Max 42 Mbit/s(DL)/Max 5.76 Mbit/s(UL)
FDD-LTE: non-CA cat4, Max 150 Mbit/s(DL)/Max 50 Mbit/s (UL)
TDD-LTE: non-CA cat4, Max 130 Mbit/s(DL)/Max 35 Mbit/s(UL)
Transmit power
EGSM900: +33 dBm (Power Class 4)
DCS1800: +30 dBm (Power Class 1)
EDGE 900MHz: +27 dBm (Power Class E2)
EDGE1800MHz: +26 dBm (Power Class E2)
TD-SCDMA: +23 dBm (Power Class 3)
CDMA 1X/EVDO: +23 dBm (Power Class 3)
UMTS: +23 dBm (Power Class 3)
LTE: +23 dBm (Power Class 3)
Application Interfaces
2G/3G/4G antenna, 4G diversity antenna, GNSS antenna, 50Ω
impedance
3 RF performance might not meet 3GPP/3GPP2 standards in extended temperature but it does not affect functioning.
4 Indicates current features of A70CN. For current features of other variants, see Chapter 4.
5 indicates that VBAT_BB and VBAT_RF share one power supply.
A70 Series Hardware User Guide
Chapter 1 About A70 Series
Copyright © Neoway Technology Co., Ltd
17
Two UART interfaces, at most 4 Mbit/s
Two USIM interfaces, compatible with 1.8V/2.85V USIM cards, dual-SIM
single-standby
One USB2.0 high-speed interface
One HSIC interface, used to connect high-speed chipset
Three 15-bit ADC interfaces, detectable voltage ranging from 0.1 to 1.7V
One SPI interface, maximum frequency of 50MHz, support master mode
only
One SDIO interface, used to control WLAN
One dual-voltage SD3.0 interface, used to control SD card or 4-bit
eMMC chipset
One I2S interface, used for digital audio transmission or configured as
PCM interface
One I2C interface, used to control external sensor, master mode only
One SGMII interface, used to connect to Ethernet PHY chipset
One MDIO interface, used to control PHY chipset (multiplexed from
USIM2)
Two analog audio input interfaces (only supported by variants with
CODEC chipset)
Two analog audio output interfaces (only supported by variants with
CODEC chipset)
One analog power output interface (only supported by variants with
CODEC chipset)
One general power output interface, typically outputs 1.8V, a maximum
current of 200 mA.
13 GPIO pins, five among which support interrupt.
AT commands
3GPP Release 13
Neoway extended commands
Emergency response
ERA-GLONASS, eCall (only for A70 and A70V3)
Dedicated in-vehicle
communications
technology
DSRC-V2V, V2P 802.11p (only for A70 and A70V3, requiring a third-
party module)
SMS
PDU, TXT
Data
PPP, RNDIS, ECM, RMNET
Protocol
TCP, UDP, MQTT, FTP/FTPS, HTTP/HTTP(S), SSL, TLS
Certification approval
CCC, SRRC,CTA, RoSH
A70 Series Hardware User Guide
Chapter 2 Module Pins
Copyright © Neoway Technology Co., Ltd
18
2 Module Pins
There are 284 pins on A70 and their pads are introduced in LGA package.
2.1 Pad Layout
Figure 2-1 shows the pad layout of A70 pins.
Figure 2-1 Pin assignment
GND
GND
GND
GND
RESERVED
GND
GND
GND
SPI_MISO
RESERVED
VDD_SDC_
PULL
SDC_DATA
2
SDC_DATA
0
GND
GPIO_11
UART3_CT
S
UART3_TX
D
GND
ANT_DIV
GND
RESERVED
GND
GND
ANT_GNSS
GND
GND
SPI_MOSI
EMMC_RES
ET_N
SDC_DATA
3
SDC_DATA
1
SDC_CLK
GPIO_10
UART3_RT
S
UART3_RX
D
WLAN_SDI
O_DATA3
GND
GND
GND
GPIO_51
GPIO_52
GND
GND
GND
SPI_CS_N
RESERVED
SDC_PWR_
EN
SDC_DET
SDC_CMD
GND
GND
WCI_LTE_R
XD
WLAN_SDI
O_DATA2
WLAN_SDI
O_DATA1
GND
GND
RESERVED
RESERVED
GNSS_LNA
_EN
GND
GPIO_53
GND
SPI_CLK
GND
GND
GND
RESERVED
DSRC_SLE
EP_CLK
WLAN_EN
WCI_LTE_T
XD
WLAN_SDI
O_DATA0
GND
GND
GND
GND
GND
GND
RESERVED
RESERVED
RESERVED
GND
GND
GND
GND
BT_EN
WLAN_SLE
EP_CLK
RFCLK2_Q
CA
WLAN_PWR
_EN
WLAN_SDI
O_CMD
RESERVED
RESERVED
UART5_RX
D
RESERVED
GND
WLAN_SDI
O_CLK
GND
RESERVED
UART5_TX
D
GND
I2S_MCLK
I2S_RX
I2S_SCLK
RESERVED
RESERVED
GPIO_58
GPIO_78
GND
GND
GND
GND
GND
GND
I2S_WS
I2S_TX
GND
GPIO_76
GPIO_79
GPIO_77
GND
GND
GND
GND
MIC2_P
GND
GND
GND
RESERVED
GND
GND
GND
GND
GND
GND
GND
MIC2_N
EAR2_N
EAR1_P
RESERVED
RESERVED
RESERVED
GND
GND
GND
GND
MIC1_P
MIC1_N
EAR2_P
EAR1_N
RESERVED
GND
GND
GND
GND
GND
GND
GND
MIC_BIAS
GND
GND
GND
GND
RESERVED
GND
GND
GND
GND
GND
I2C_SCL
I2C_SDA
AVDD_1P8
GND
GND
RESERVED
GND
GND
GND
GND
GND
GND
RESERVED
GND
GND
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
USIM2_VCC
RESERVED
SGMII_RX_
N
RESERVED
RESERVED
GND
GND
USIM2_CLK
SGMII_RX_
P
GND
GND
GND
GND
GND
GPIO_25
GND
GND
USIM1_DET
USIM1_CLK
USIM1_VCC
ADC3
ADC1
GND
GND
USIM2_RES
ET
USIM2_DAT
A
SGMII_TX_
N
GND
GND
GND
RESERVED
SLEEP
GPIO_24
RESERVED
GPIO_43
USIM1_RES
ET
USIM1_DAT
A
RESERVED
ADC2
GND
GND
GND
USIM2_DET
SGMII_TX_
P
GND
GND
GND
GND
RESERVED
RESERVED
RESERVED
VDD_1P8
GND
GND
GND
GND
VBAT_BB
VBAT_BB
RESERVED
USB_ID
GND
GND
ANT_MAIN
GND
GND
GND
RESERVED
RESERVED
RESERVED
GND
VBAT_RF
VBAT_RF
VBAT_RF
GND
VBAT_BB
VBAT_BB
HSIC_DATA
USB_VBUS
USB_DP
GND
GND
GND
GND
PWRKEY_N
RESET_N
GND
GND
VBAT_RF
VBAT_RF
VBAT_RF
GND
GND
VBAT_BB
VBAT_BB
HSIC_STB
USB_DM
GND
A B C D E F G H J K L M N P R S T U V W X Y AA AB AC AD AE AF AG AH AJ AK AL AM AN
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A B C D E F G H J K L M N P R S T U V W X Y AA AB AC AD AE AF AG AH AJ AK AL AM AN
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RESERVED
ANTGND
CONTROL
GPIO RESERVED UIM
ADC
USB SGMII
I2C
AUDIO
I2S
WLAN UART SDC/eMMC
SPI OTHERS
POWER
A70 Series Hardware User Guide
Chapter 2 Module Pins
Copyright © Neoway Technology Co., Ltd
19
2.2 Pin Description
Table 2-1 lists the definition of IO types.
Table 2-1 IO definition
IO Type
Description
B
Digital input/output, COMS level
DO
Digital output, COMS level
DI
Digital input, COMS level
OD
Open drain
PO
Power output
PI
Power supply input
AO
Analog output
AI
Analog input
AIO
Analog input/output
Table 2-2 Level Feature
I/O
Pin type
Voltage Feature
Output Current
Feature
P1
USIM1 interface
voltage, compatible with
1.8V/2.85V
1.8V
VIH=1.26 V~2.1 V
VIL=-0.3 V~0.36 V
VOH=1.44 V~1.8 V
VOL=0 V~0.4 V
2.85V
VIH=2 V~3.15 V,
VIL=-0.3 V~0.57 V
VOH=2.28 V~2.85 V
VOL=0 V~0.4 V
2 mA~16 mA,
adjustable at a
spacing of 2 mA
P2
USIM2 interface
voltage, compatible with
1.8V/2.85V
1.8V
VIH=1.26 V~2.1 V
VIL=-0.3 V~0.36 V
VOH=1.44 V~1.8 V
VOL=0 V~0.4 V
2.85V
VIH=2 V~3.15 V,
VIL=-0.3 V~0.57 V
VOH=2.28 V~2.85 V
VOL=0 V~0.4 V
2 mA~16 mA,
adjustable at a
spacing of 2 mA
P3
1.8V digital IO
VIH min=1.2 V, VIL max= 0.3 V
VOH min=1.35 V, VOL max= 0.45 V
2 mA~16 mA,
adjustable at a
spacing of 2 mA
P4
SDC interface voltage,
compatible with
1.8V/2.85V
1.8V
VIH=1.27 V~2 V,
VIL= -0.3 V~0.58V
VOH=1.4 V~1.8 V,
VOL=0 V~0.45 V
2.85V
VIH=1.8 V~3.15 V,
VIL= -0.3 V~0.7 V
VOH=2.1 V~2.85 V,
VOL=0 V~0.36 V
2 mA~16 mA,
adjustable at a
spacing of 2 mA
P5
HSIC interface voltage,
VIH=0.78V~1.2V, VIL =0V~0.42V
2 mA~16 mA,
/
