PEX 8311RDK
Errata Revision 1.1
August 2007
Errata Documentation
1. Voltage Regulator U9
Note. This erratum only pertains to PEX 8311RDK Revision 1.0 boards.
Description:
On the PCI 8311RDK board, the part originally selected for U9 was incapable of producing 2.5V
output from a 3.3V input. It was replaced with the LT1963A, which fixes the problem. However,
the pinout of the LT1963A does not match the pinout of the original part. For this reason, Revision
1.0 boards are assembled with the LT1963 mounted rotated relative to the the PCB pads, with
pin 2 soldered to pad 1, pin3 soldered to pad 2, and pin1 wired to pad 3. The schematics show
the circuit connections after these reworks are added.
2. PMEOUT# signal pull-up resistor R1147
Note. This erratum only pertains to PEX 8311RDK Revision 1.0 boards.
Description:
PMEOUT# pin of the 8311 is not connected in the Revision 1.0 board. This pin should be pulled
up or tied to ground to prevent possible oscillation of the input. No functional problems have been
associated with this erratum.
Workaround:
R1147 (schematic sheet 3) was added to the schematic to correct the problem in the design,
however, physical constraints prevent addition of this resistor to the current revision PCB.
3. VB14 Resistor R661
Note This erratum only pertains to PEX 8311RDK Revision 1.0 boards.
Description:
The voltage regulator U3 generates the 1.5V supply for the PEX8311RDK. There is relatively little
spare current available from U3 to power additional logic. If FP2 is populated with an Altera
Cyclone array then the FPGA will require more current from the 1.5V supply than can be provided
by U3. Ideally it should be possible to use the uncommitted USRVCC (U14) to provide the 1.5V
supply to the FPGA. Although R321 can be used to link pin 64 of the array to VB14, the link from
VB14 to the USRVCC (R661) is not present on the Revision 1.0 board.
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