Broadcom PEX 8647 Silicon Errata List User guide

PEX 8647

Silicon Revisions and Errata List

CONFIDENTIAL PROPRIETARY INFORMATION

NDA REQUIRED

Version 1.9

June 2011

Website: www.plxtech.com

Technical Support: www.plxtech.com/support

June 16, 2011

PEX 8647 Errata v1.9

A. Affected Products and Silicon Revisions

This document details Errata for the following products and silicon revisions:

Product Description Revision Status

PEX 8647 48-Lane, 3-Port PCIe Gen 2 Switch

AA General Sampling

AB Conditional Production

BB Full Production

B. Device Documentation Version

The following documentation is the baseline functional description of the silicon:

Document Version Description Publication Date

PEX 8647 Data Book

1.2 Data Book October 2010

C. Errata Documentation Revision History

Revision Publication Date Description

0.5 February 2008



Initial publication of errata list based on errata found

during simulation and evaluation of early silicon samples

(Erratum 1, 2, & 3)

0.6 March 2008



Added Erratum 4

 Added Erratum 5

 Added Erratum 6

 Added Erratum 7

 Edited Errata Summary Table (Erratum 2)

0.7 April 2008



Added Erratum 8

 Added Erratum 9

 Added Erratum 10

0.8 May 2008



Added Erratum 11

 Added Erratum 12

 Added Erratum 13

 Added Erratum 14

0.9 July 2008



Added Erratum 15

 Added Erratum 16

 Added Erratum 17

 Edited Erratum 14

0.91 October 2008

 Added Erratum 18

0.92 November 2008

 Added Erratum 19

1.0 February 2009



Added Erratum 20

 Added Erratum 21

 Added Erratum 22

1.1 March 2009

 Added Erratum 23

1.2 April 2009

 Edited Erratum 20 (Workaround #2)

1.3 June 2009



Edited Erratum 18 (Added Workarounds, Affects BB

Silicon Revision as well)

1.4 September 2009



Added Erratum 23

 Added Erratum 24

 Edited Erratum 20 (Modified the Description)

PEX 8647 Errata v1.9

Revision Publication Date Description

1.5 December 2009



Added Erratum 25

 Added Caution 1

1.6 January 2010



Edited Erratum 25 (Corrected register bit reference)

 Edited Caution 1 (Updated Workaround and Impact)

1.7 March 2010

 Added Caution 2

1.8 July 2010

 Added Erratum 26

1.9 June 2011



Added Erratum 27

 Added Erratum 28

 Added Erratum 29

D. Errata Summary

# Description

Risk

Category

Devices

Excepted

Silicon Revisions Affected?

AA AB BA BB

1

Receivers Detected on Lanes that

Do Not Exit Electrical Idle Polling

Low None Yes Yes Yes Yes

2

Speed Change Bit (TS1) Asserted

After L1 PM State Exit

Low None

No

No No

Yes

PEX 8647 Errata v1.9

F. Errata List

Note: Throughout this document, unless specified otherwise, “Switch” is used to indicate the

PEX 8647 switch.

1. Undependable Lane Reversal with Partial Lanes

Risk Category: Low Silicon Revisions Affected: AA

Description

This erratum only affects designs using lane reversal with partial lanes (some of

the lanes being reversed are not connected to anything) and there is more than 1

port on that station. It does not affect x16 ports.

For example, if a 2-lane (x2) link is being used on a 4-lane (x4) slot and the lanes

are reversed so that Lane 1 is connected to Lane 0 of another device, the link

may not come up if another port on the same station is already linked up.

The same is true if a 2-lane (x2) or 4-lane (x4) device is connected to an 8-lane

(x8) slot and the lanes are reversed to make Lane 1 or Lane 3 to be connected to

the other device’s Lane 0.

Solution/Workaround

None.

Impact

Lane reversal cannot be used for some port configurations if partial lanes are

being used.

Back to Errata Summary Table

2. Improper Data Rate & De-Emphasis Level Sequence

Risk Category: Low Silicon Revisions Affected: AA

Description

The PCI Express Gen2 specification states that data rate and de-emphasis level

settings should repeat the following sequence every time it enters polling

compliance state:

Data Rate = 2.5 GT/s, De-emphasis Level = -3.5 dB.

Data Rate = 5.0 GT/s, De-emphasis Level = -3.5 dB

Data Rate = 5.0 GT/s, De-emphasis Level = -6.0 dB

In the case of the Switch, the sequence is as follows:

Data Rate = 2.5 GT/s, De-emphasis Level = -3.5 dB.

Data Rate = 5.0 GT/s, De-emphasis Level = -6.0 dB

PEX 8647 Errata v1.9

The “Data Rate = 5.0 GT/s, De emphasis Level = -3.5 dB” setting can be

achieved by writing to the Link Control2 register bit 4 and bit 12 and bits 3:0.

Solution/Workaround

None.

Impact

To achieve a data rate of 5.0GT/s and de-emphasis level of -3.5dB, the Link

Control2 register needs to be written to. One of the specification-defined ways to

achieve this (as described above) cannot be used.

Back to Errata Summary Table

3. Surprise Down Error Messages Not Generated

Risk Category: Low Silicon Revisions Affected: AA

Description

The Uncorrectable Error Status register bit 5, Surprise Down Error Status, will not

be set when a link goes down, and the corresponding error message will not be

generated. Also, the data link layer state changed bit in the slot status register is

not reliable.

Solution/Workaround

None.

Impact

Rather than getting an error message in case of a Surprise Down, the system will

need to rely on completion timeouts or polling the link status register for the link-

width.

Back to Errata Summary Table

4. Exiting ASPM Causes Link Down

Risk Category: Medium Silicon Revisions Affected: AA

Description

Going in and out of Active State Power Management States sometimes results in

link retrain or negotiating down the link width.

Solution/Workaround

None (user needs to turn off ASPM).

Impact

If a system BIOS or software is not able to handle link down or link retrain, the

system will hang. Most systems allow ASPM to be turned off, but some systems

may require it.

Back to Errata Summary Table

PEX 8647 Errata v1.9

5. Unsuccessful Dynamic Link Width/Speed Change

Risk Category: Low Silicon Revisions Affected: AA

Description

Dynamically changing link speed or link width from Gen 1 to Gen 2, or vice-

versa, could result in lower speed/width than expected (observed once or twice in

a million events).

Solution/Workaround

Control link speed/width through software controllable registers for dynamic

changes during run time, confirm speed/width and re-program if not correct

value.

Impact

Systems that do not use hardware initiated dynamic speed/width changes should

not be affected by this. In systems where applicable, it may cause the link to

settle in Gen 1 or link up with the wrong width.

Back to Errata Summary Table

6. ARI Forwarding Supported & Forwarding Enable Bits

Risk Category: Medium Silicon Revisions Affected: AA

Description

ARI Forwarding supported bit in Device Capabilities2 Register for a switch

upstream port should be 1’b0 and ARI Forwarding Enable bit in the Device

Control2 Register for the upstream port of a switch should be hardwired to 1’b0.

In the Switch, however, ARI Forwarding supported bit is 1’b1 for the upstream

port and the ARI forwarding enable bit for the upstream port is Read/Writeable.

Solution/Workaround

User needs to disable the upstream port ARI forwarding supported bit using

EEPROM. This also disables the ARI forwarding enable bit Read/Writeable

privilege for the upstream port.

Impact

If customer system is planning to use ARI, EEPROM or I

2

C cycle will be needed

to write to ARI forwarding supported bit before BIOS scan.

Back to Errata Summary Table

PEX 8647 Errata v1.9

7. Incorrect Modified Compliance Pattern Disparity

Risk Category: Medium Silicon Revisions Affected: AA, AB

Description

The compliance patterns for Lanes 1 thru 7 in each octal of the Switch is

incorrect.

The delay sequence specified by the PCIe 2.0 spec is D D K28.5- D21.5 K28.5+

D10.2 D D where D symbols are K28.5 characters with appropriate disparity.

Lane 0 exhibits the following pattern: K28.5- K28.5+ K28.5- D21.5 K28.5+ D10.2

K28.5- K28.5+ followed by repeating sequences of K28.5- D21.5 K28.5+ D10.2

Lanes 1 thru 7 exhibit the following K28.5+ K28.5- K28.5+ D21.5 K28.5- D10.2

K28.5+ K28.5- followed by repeating sequences of K28.5+ D21.5 K28.5- D10.2.

Solution/Workaround

None.

Impact

The wrong sequence of K28.5+ D21.5 K28.5- D10.2 acts to degrade the high

frequency content of the Compliance Pattern.

Back to Errata Summary Table

8. Flow Control Protocol Error Severity and Surprise Down

Severity in Upstream Port

Risk Category: Low Silicon Revisions Affected: AA

Description

The Flow Control Protocol Error Severity in all ports and the Surprise Down

Severity in the upstream port is hardwired to 1’b0. However, per the PCIe

Specification, it should be hardwired to 1’b1.

Solution/Workaround

None.

Impact

None.

Back to Errata Summary Table

PEX 8647 Errata v1.9

9. Completion Timeout Error Severity

Risk Category: Low Silicon Revisions Affected: AA

Description

In the Switch, the Completion Timeout Error Severity bit is Read/Writeable.

However, per the PCIe Specification, switches do not generate non posted

transactions so all ports of a switch should hardwire this bit to 1’b0.

Solution/Workaround

None.

Impact

None.

Back to Errata Summary Table

10. Stuck in Recovery

Risk Category: Low Silicon Revisions Affected: AA

Description

There is a state transition in the Recovery state where the Switch does not start

the timers that should cause a timeout if Recovery is not successful. This

transition is from Recovery Idle to Recovery.RcvrLock. This erratum is applicable

in Gen 1 mode as well as Gen 2 mode.

Solution/Workaround

None.

Impact

In a very noisy system, the Switch could get stuck in Recovery when it should

timeout and go to Detect.

Back to Errata Summary Table

11. Scrambler Disable Training Control Bit

Risk Category: Low Silicon Revisions Affected: AA, AB

Description

The Scrambler Disable Training Control bit needs to be latched in the

Configuration Complete state and should not be latched in the Recovery state.

However, the Switch latches the Scrambling Disable Training Control bit in the

Recovery state.

PEX 8647 Errata v1.9

Solution/Workaround

Program the corresponding station Port0 Offset 230h Bit[1] to disable scrambling

for Port0, Bit[5] to disable scrambling for Port1, Bit[9] to disable scrambling for

Port2, and Bit[13] to disable scrambling for Port3.

Impact

Customer will not be able to disable scrambling in the Configuration state. If the

customer tries to enable scramble again, the link will not come up.

Back to Errata Summary Table

12. Extended Synch Bit Non-functional in Gen 2 Mode

Risk Category: Low Silicon Revisions Affected: AA, AB

Description

The Extended Synch bit functionality is non-functional in Gen 2 mode. If the

Extended Synch bit is set in Recovery.RcvrLock state, the transmitter is

supposed to send a minimum of 1024 consecutive TS1 ordered sets before

transitioning to Recovery.RcvrCfg state. However, the Switch keeps on sending

TS1 ordered sets and does not move to Recovery.RcvrCfg state. After a 24ms

timeout, the Switch will attempt to reset the link speed back to Gen 1.

Solution/Workaround

None.

Impact

Customer cannot use the Extended Synch bit in the Switch.

Back to Errata Summary Table

13. Idle_to_Rlock Transitioned Flag Broken in Recovery State in

Gen 2 Mode

Risk Category: Low Silicon Revisions Affected: AA, AB

Description

The idle_to_rlock_transitioned flag does not assert when the Recovery state

machine transitions from Recovery.Idle state to Recovery.RcvrLock state while in

Gen 2 mode. This causes the Recovery state machine to continuously cycle

between Recovery.RcvrLock->Recovery.RcvrCfg->Recovery.Idle states as long

as it is receiving TS2 training sets with valid link and lane numbers. This in turn

leads to a longer than necessary timeout and a delayed return to Detect state.

Solution/Workaround

None.

Impact

It will take a bad link a little longer to go down due to a longer timeout.

PEX 8647 Errata v1.9

Back to Errata Summary Table

14. EEPROM Loading of Port Configurations

Risk Category: Low Silicon Revisions Affected: AA, AB, BB

Description

The EEPROM load of Station 1 and Station 2 port configurations (0x574h) does

not update unless the Station 0 port configuration is also changed during the

EERPOM load.

Solution/Workaround

The EEPROM load to change port configurations needs 1 extra write from the

EEPROM. The first write changes the Station 0 port configuration to a non-strap

value. The second write changes port configurations for all stations to the desired

value.

Impact

The customer may need to execute 1 extra write through the EEPROM if only the

Station 1 and/or Station 2 port configuration(s) need to be changed.

Back to Errata Summary Table

15. Bad DLLP/TLP Errors in ASPM L1 or L0s

Risk Category: Medium Silicon Revisions Affected: AA, AB

Description

If ASPM L1 or L0s is enabled on the Switch, Bad DLLP/TLP errors are logged in

the Switch and spurious NAKs are sent out.

Solution/Workaround

None (user needs to turn off ASPM).

Impact

ASPM L1 and L0s cannot be used.

Back to Errata Summary Table

16. Cannot Support 600ppm Offset in Asynchronous Systems

Risk Category: Low Silicon Revisions Affected: AA, AB, BB

Description

The Switch supports up to a 500ppm offset from other devices in an

asynchronous system as opposed to the 600ppm that the PCIe Base

Specification, r2.0 requires.

PEX 8647 Errata v1.9

Solution/Workaround

Reference clocks need to have tighter control.

Impact

Most clock sources compliant to PCI Express CEM specification exhibit less than

100ppm of frequency variation (including temperature and aging variance). There

should be no impact due to this erratum in CEM Express compliant systems.

Back to Errata Summary Table

17. Link Speed Change with L1 ASPM Enabled

Risk Category: Medium Silicon Revisions Affected: AA, AB

Description

If L1 ASPM is enabled and speed change is requested for a particular link of the

Switch, and the retrain link bit is set, the link will come out of low power state but

the speed change will not take place.

Solution/Workaround

If the link speed does not change on the first try, try again.

Impact

If ASPM is enabled, link speed change may not execute properly.

Back to Errata Summary Table

18. Rx Pins Do Not Work with AC-JTAG Instructions

Risk Category: Low Silicon Revisions Affected: AA, AB, BB

Description

The level output on the Switch RX pins used by the AC JTAG instructions is not

stable and consequently it is not latched in the Switch by the boundary scan

chain.

Solution/Workaround

There are two workarounds:

1. Bring up the links and check the widths using the PEX_PORT_GOOD# pins.

The link width and speed can also be checked using I

2

C.

2. The external device can put the Switch into loopback mode and then check

the integrity of the link. External devices connected to the Switch can also be

put in loopback mode using the Switch and the link integrity can be checked

using PRBS or other user-programmable test patterns.

PEX 8647 Errata v1.9

Impact

The RX pins of the Switch cannot be used with AC-JTAG instructions. The TX

pins of the Switch are not affected and can be used with AC-JTAG instructions.

Back to Errata Summary Table

19. Unexpected DL_DOWN in the Middle of TLP Can Cause FC

Credit Loss

Risk Category: Low Silicon Revisions Affected: AA, AB

Description

If a TLP starts on a port of the Switch and a device connected to the Switch is

disconnected either by removing its power supply or by physically disconnecting

it, it is possible that one TLP will not be de-allocated and will consume memory

space until the Switch is reset either by a Fundamental Reset or by a Hot Reset

from the upstream port. The same issue can occur if the noise on the link

manifests itself as an “STP” symbol.

A DL_DOWN due to noise where the device connected to the Switch is sending

at least a few training sets before the link goes down will not have this issue. If

DL_DOWN is caused by noise, the device connected to the Switch is supposed

to go into recovery and send training sets for at least 24ms before the link goes

down. If the Switch receives 2 consecutive good training sets, this erratum will

not occur.

Solution/Workaround

Set the “Link Disable” or “Secondary Bus Reset” bit before removing the link.

Impact

Surprise removal of a device connected to the Switch multiple times can lead to

reduced Switch performance.

Back to Errata Summary Table

20. Incorrect TCB Capture of Training Sets

Risk Category: Low Silicon Revisions Affected: AA, AB, BB

Description

In the case where excess noise exists on a link, the combination of a “COM”

symbol followed by noise can result in the incorrect misinterpretation of Ordered

Sets. The misinterpretation of said sequence might cause the LTSSM to remain

in Loopback State until an assertion of a Hot Reset or a Fundamental Reset is

detected. Due to what is required to create this condition, this problem has only

manifested itself in asynchronous clocked systems.

Solution/Workaround

There are 3 possible workarounds for this erratum:

PEX 8647 Errata v1.9

1. Assert a Hot Rest or Fundamental Reset to the device.

2. Set register 0x228h[5] = 1 in order to mask Training Control Bits (TCB) in

the training sets. Note that setting this bit affects all ports in the station and

if the upstream port is part of the affected station, can cause the upstream

port to ignore the Hot Reset TCB – preventing the switch to be reset from

such a training set.

3. Disable and then enable the failing port using register 0x234h to clear the

LTSSM.

Impact

The link might fail to achieve link-up status due to the noise on the link.

Back to Errata Summary Table

21. Correctable Error Status Bit Set Erroneously

Risk Category: Low Silicon Revisions Affected: AA, AB, BB

Description

When L0s ASPM is enabled, spurious receiver errors could get logged which

could result in ERR_CORR messages being received by the host.

Solution/Workaround

When L0s ASPM is enabled, set the Correctable Error Mask bit 0xFC8h[0]=1 to

prevent the ERR_CORR message from being sent out due to receiver errors.

Note that when this bit is set, other types of errors could still trigger ERR_CORR

messages if they occur.

Impact

Spurious ERR_CORR messages could be received and the switch might set the

Correctable Error Detected Bit (0x72h[0]) when L0s ASPM is enabled. Although

this erratum occurs when ASPM is enabled, it does not affect the functionality of

ASPM.

Back to Errata Summary Table

22. Unreliable Port Disable/Re-enable when using 0x234h[19:16]

Risk Category: Low Silicon Revisions Affected: AA, AB, BB

Description

If a customer uses register 0x234h[19:16] to disable a particular port when the

link is at Gen 2 speed, the link may not come up when the customer re-enables

the port by clearing these bits back to the default value.

Solution/Workaround

1. To bring a link down, set link disable 0x78h[4] and then set 0x78h[5] to retrain

the link.

PEX 8647 Errata v1.9

2. To disable a port, bring the target link speed to Gen 1 by writing to 0x98h[3:0],

waiting for 10 microseconds, and then using port disable to disable the port.

3. If enabling the port after disabling it does not bring the link up, disable it one

more time and enable it again. This will bring the link up.

Impact

At Gen 2 speed, customer cannot reliably use the port disable/re-enable

functionality of register 0x234h[12:16].

Back to Errata Summary Table

23. Incorrect ACS P2P Completion Routing

Risk Category: Low Silicon Revisions Affected: AA, AB, BB

Description

If the ACS P2P Completion Redirect bit in the ACS Control and Capability

register is set for a downstream port, completions directed to a peer port from a

peer port without the TLP Relaxed Ordering (RO) bit set should be routed to the

upstream port. However, when the following 2 conditions are met, the Switch

incorrectly routes such completions to the peer port instead:

a) The ACS P2P Egress Control bit is active in the ACS Control and

Capability Register.

b) The Egress Control Vector bit in the ACS Control and Capability register

for the associated egress peer is inactive.

Solution/Workaround

There are two possible workarounds:

1. Do not set the ACS P2P Egress control bit in the ACS Control and

Capability register if the ACS P2P Completion Redirect bit is being used in

the switch.

2. Ensure that the Egress Control Vector in the ACS Control and Capability

register of both the peer ports enable or disable the other port in a

symmetric manner. For example, if Peer Port 1 enables Peer Port 2

Egress Control and Peer Port 2 enables Peer Port 1 in the Egress Control

Vector, it is symmetric. Or, if Peer Port 1 disables Peer Port 2 Egress

Control and Peer Port 2 disables Peer Port 1 in the Egress Control Vector,

it is symmetric.

Impact

When the ACS P2P Completion Redirect bit is set, the ACS Egress Control

Vector may affect the ACS P2P Completion Redirect functionality by causing

completions (as described in the Description) to be routed to the incorrect port.

Back to Errata Summary Table

PEX 8647 Errata v1.9

24. ACS Upstream Forwarding Issue

Risk Category: Low Silicon Revisions Affected: AA, AB, BB

Description

If the ACS Upstream Forwarding bit in the ACS Control and Capability register is

set in the downstream port of the Switch, and a completion is received at the

ingress of the downstream port intended for the egress of the same downstream

port, it should be routed upstream. However, with the Switch, if the above

mentioned completion has the TLP Relaxed Ordering (RO) bit set, it is not routed

upstream.

Solution/Workaround

There are two possible workarounds:

1. Don’t set the RO bits in the peer requests.

2. If the RO bit is set, then do not set the ACS Upstream Forwarding bit.

There should be no need to set this bit unless switches are cascaded.

Impact

RO completions that should be routed upstream when ACS upstream forwarding

is enabled are not routed upstream.

Back to Errata Summary Table

25. Analog Loopback Slave Mode Support

Risk Category: Low Silicon Revisions Affected: AA, AB, BB

Description

Analog Loop Back Slave Mode is non-functional for asynchronous systems. For

synchronous systems, analog loop back slave mode is functional when the

following bit is set in the Physical Layer Safety Bits register (0x22C[2]=1).

Solution/Workaround

There are two possible workarounds:

1. For Asynchronous systems, use Line Loop Back instead.

2. For Synchronous systems, set the following bit in the Physical Layer

Safety Bits register (0x22C[2]=1).

Impact

Analog Loop Back Slave Mode cannot be used in Asynchronous Systems.

Back to Errata Summary Table

PEX 8647 Errata v1.9

26. Port Arbitration Table can’t be Loaded using the EEPROM

Risk Category: Low Silicon Revisions Affected: AA, AB, BB

Description

The values written to the port arbitration cable from the EEPROM get overwritten

when the upstream data link layer comes up.

Solution/Workaround

Use I2C or software to overwrite the port arbitration tables after the upstream

DLL comes up.

Impact

EEPROM unable to set Port Arbitration tables.

Back to Errata Summary Table

27. AC JTAG Functionality Does Not Work

Risk Category: Low Silicon Revisions Affected: AA

Description

The level output on the RX pins used by the AC JTAG instructions is not stable and

consequently it is not latched by the boundary scan chain. The TX pins does not

toggle at the right cycle in AC JTAG mode

.

Solution/Workaround

There are two workarounds:

1. Bring up the links and check the widths using the PEX_PORT_GOOD#

pins. The link width and speed can also be checked using I2C.

2. The external device can put the switch into loopback mode and then

check the integrity of the link. External devices connected to the switch

can also be put in loopback mode using the switch and the link integrity

can be checked using PRBS or other user-programmable test patterns

.

Impact

The RX /TX pins of the switch cannot be used with AC JTAG instructions.

Back to Errata Summary Table

PEX 8647 Errata v1.9

28. Upstream Port LTSSM Exits From Hot-Reset State After it

Receives TS1 With Hot-Reset TCB Clear

Risk Category: Low Silicon Revisions Affected: AA, AB, BB

Description

Upstream device initiates the hot-reset sequence. The Switch upstream port

LTSSM transmits TS1 with Hot-reset TCB set. The Switch upstream port LTSSM

should stay in hot-reset state for 2ms and transition to Detect state after 2ms

timeout. But it is falsely looking for TS1 with hot-reset TCB clear from the

upstream device to enable the 2ms timer.

Solution/Workaround

None.

Impact

LTSSM stays in hot-reset state until the upstream device go to Polling.Active

state.

Back to Errata Summary Table

29. PCIe Links Dropped When JTAG BYPASS is Enabled

Risk Category: Low Silicon Revisions Affected: AA, AB, BB

Description

After functional bring up of the Switch if the BYPASS instruction is loaded into JTAG

TAP the Serdes enters JTAG mode and drops link

.

Solution/Workaround

None.

Impact

The Switch does not maintain PCIE links when JTAG operations are done (including

BYPASS instruction loaded into Test Access Port )

.

Back to Errata Summary Table

PEX 8647 Errata v1.9

G. Cautions

Note: Cautions are not Errata. In Cautions, the Switch is not violating the PCIe Specification.

However, our Switch may be behaving unexpectedly due to another non-compliant device

connected to the Switch or due to ambiguity in the Specification itself.

1. Receivers Detected on Lanes that Do Not Exit Electrical Idle

Polling

Risk Category: Low Silicon Revisions Affected: AA, AB, BB

Description

If unused lanes of a multilane link are terminated, the link will not come up. When

the Switch detects a receiver on some lanes but these lanes do not detect an exit

from electrical idle in the Polling State, the link is supposed to negotiate out these

non functioning lanes and still link up to a reduced link width. In the case of the

Switch, however, the link does not come up. The inability of the Switch to

negotiate out these terminated but unused lanes is limited to the LTSSM Polling

State only. If lanes are found to be terminated in the Configuration or Recovery

State, the Switch will negotiate out these lanes and will link up successfully to a

reduced link width.

Solution/Workaround

There are two possible workarounds:

1. Do not terminate unused lanes.

2. Use the “Never Detect Electrical Idle” bit if unused lanes are

terminated.

Impact

Failure to link up in case of terminated unused lanes.

Back to Errata Summary Table

PEX 8647 Errata v1.9

2. Speed Change Bit (TS1) Asserted After L1 PM State Exit

Risk Category: Low Silicon Revisions Affected: BB only

(

Revisions AA, AB, and BA have alternate detection mechanisms to prevent this event)

Description

After exiting L1 Power State, downstream Ports on the Switch can assert the

Speed Change Request bit in TS1. The Switch is susceptible even if it’s

connected to a Gen 1 only device. On exit from L1 Power State and during the

Recovery the Switch misinterprets noise on the link as Data Rate Identifier Bit[2]

being set (TS - Symbol 4: Bit[2]). This causes the Switch to initiate speed change

by setting the Speed Change bit in TS1. If the downstream device is Gen 1 only,

it cannot interpret the Speed Change Bit and eventually the link goes down.

Solution/Workaround

If the device connected to any downstream port of the Switch is a Gen1 device,

write the target link speed in the Link control 2 register to be Gen1 speed before

enabling ASPM L1 or PCI PM L1.

Impact

The link can go down if a downstream port of the Switch is connected to a Gen1

only device, the link is noisy and ASPM or PCI PM L1 is enabled.

Back to Errata Summary Table

Broadcom PEX 8647 Silicon Errata List User guide

Broadcom PEX 8647 Silicon Errata List User guide

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