PCI 9030RDK-LITE
Errata Revision 2.3
June 2005
Errata Documentation
1. TRST# (Test Reset) Pin Is Floating
Note. This erratum only pertains to PCI 9030RDK-LITE boards shipped prior to
October 1, 2003.
Description:
On the PCI 9030RDK-LITE board, the TRST# pin is not connected, which could put the PCI 9030
into an undefined state during PCI RST# assertion, precluding normal chip logic operation.
Implementing the following workarounds will put the JTAG state machine into the reset state,
which enables normal chip logic operation.
Workarounds (do one of the following):
1. For board revision 90-0014-001-A:
If JTAG is not used, pull down the TRST# pin by connecting a 5.6K Ohm resistor
between pins 4 and 6 of J2, the JTAG header. Pin 4 is TRST#, and pin 6 is grounded.
2. For all other boards:
If R33 (at the left side of the JTAG header J2) is not installed, populate with a 10K ohm
resistor.
3. If JTAG functionality is to be implemented, please refer to both the PCI specification and
the JTAG specification (IEEE 1149.1) requirements for the JTAG pins.
2. ISA Connector Footprint Reversed
Note. This erratum only pertains to revision 90-0014-001-A of the PCI
9030RDK-LITE. It has been fixed in all later revisions.
Description:
The ISA connector footprint labeling and the ISA connector 5V, 12V, -12V, power and ground
rails are reversed on the PCI 9030RDK-LITE. The A1 and C1 fingers should be on the
component side, and the B1 and D1 fingers should be on the solder side of the RDK. Power is
routed to the ISA footprint, according to the current (incorrect) labeling, as follows:
- 5V is routed to A3, A29, and C16, rather than B3, B29, and D16, respectively.
- 12V is routed to A9, rather than B9.
- -12V is routed to A7, rather than B7.
- GND is routed to A1, A10, A31, and C18, rather than B1, B10, B31, and D18, respectively.
- No other signal connections from the board to the ISA connector footprint exist.
- 1 - PCI 9030/LITE-RDK-ER-P0-2.3
Workaround:
If an ISA connector is to be added to the PCI 9030RDK-LITE, the connector leads to A1, A3,
A7, A9, A10, A29, A31, C16, and C18 (all on the solder side of the board) should not be
soldered to these footprint fingers. Instead, these connector leads should be isolated from the
footprint finger contacts by bending the leads out, and then connect them to B1, B3, B7, B9,
B10, B29, B31, D16, and D18, respectively by using wire.
3. CLK Trace Length
Note. This erratum only pertains to revision 90-0014-001-A of the PCI
9030RDK-LITE. It has been fixed in all later revisions.
Description:
PCI Specification r2.2 Section 4.4.3.1 requires that the CLK signal trace length on expansion
boards must be 2.5” ± 0.1”. On the PCI 9030RDK-LITE, the CLK trace length is less than the
required value.
Workaround:
Designs based upon the PCI 9030RDK-LITE should ensure that the PCI CLK trace complies
with the PCI Local Bus Specification trace length requirement.
4. The Reset Button Does Not Function
Note. This erratum only pertains to revision 90-0014-001-A of the PCI
9030RDK-LITE. It has been fixed in all later revisions.
Description:
Due to a board layout error, Pin 3 of the reset button (U13) is improperly grounded, which
prevents the reset circuit from functioning.
Workaround (execute the following three steps in order):
1. Face the board component side to you and place the RS-232 serial port to your left side.
The reset button is at the top-left corner of the board.
2. Disconnect the top left pin of the reset button from the board pad.
3. Wire the bottom left pin of the reset button to the top left pin board pad.
- 2 - PCI 9030/LITE-RDK-ER-P0-2.3
5VCC
3.3V
GND
3.3V
GND
J3
LAH5
Serial
EPROM
J5
U12
U11
PCI 9030
ISA Connector Footprint
16 pin
SOIC
16 pin
SOIC
16 pin
SOIC
16 pin
SOIC
20 pin
SSOIC
20 pin
SOIC
20 pi n
SOIC
20 pi n
SOIC
208/144/80
PQFP
footprints
44 pin
TQFP
20 pin
PLCC
54 pin TSOP
54 pin TSOP
84/68/44/28
PLCC
footprints
25x25 0.1" through hole
prototyping area
176/100/48
PQFP
footprints
48 pin
SSOP
48 pin
SSOP
POM Connector
24 pin
SSOP
24 pin
SSOP
LAH1
LAH2
LAH6
U5
LAH4
LAH3
DPRAM
U7
DPRAM
U8
U1
DC/DC
Converter
16 pin
SSOP
16 pin
SSOP
OSC
U3
28 pin SOIC
FP1 for flash
memo ry
28 pin SOIC
OSC
U14
S1
U13
48 pin
SSOP
48 pin
SSOP
LEDs
26x26 0.05"
pitch BGA
landscape
Reset Button
RS-232 Serial Port
5. PCI 9030 Pins 52 And 53 Connections Swapped
Note. This erratum only pertains to revision 90-0014-001-A of the PCI
9030RDK-LITE. It has been fixed in all later revisions.
Description:
Due to a mistake in Version 1.0 of the PCI 9030 Data Book, the connections to Pin 52 (LEDon#)
and Pin 53 (V
I/O
) of the PCI 9030 are swapped on the PCI 9030RDK-LITE board. (Note. The
referenced mistake has been corrected in all revisions of the PCI 9030 Data Book subsequent to
Version 1.0.)
Workaround:
All the modifications will be implemented on the component side of the RDK board. Please
see Figure-1 for the location.
1. Carefully cut the trace located just below the label R8. (Figure-2).
2. Solder one end of a 30 gauge wire to the via at the upper left hand corner of the “R” in
the label R8. (Figure-2)
3. Solder the other end of the 30 gauge wire to the trace that is directly below the “C” in the
word “TECHNOLOGY” that leads to the PCI edge connector. WARNING: DO NOT
SOLDER TO THE PAD ON THE PCI EDGE CONNECTOR OR ANYHWERE WITHIN
6mm ABOVE THE PAD. (Figure-3)
4. Remove R9 from the board.
- 3 - PCI 9030/LITE-RDK-ER-P0-2.3
Figure-1
Cut trace here
Figure-2
Solder wire here
6m
m
Figure-3
Solder wire here
Do not solder anywhere
within this area
6. PME# MOSFET Source/Drain Reversed
(revised from Rev. 2.2)
Note. This erratum pertains to all revisions of the PCI 9030RDK-LITE.
Description:
The MOSFET used in the PME# circuit has an internal protection diode, and consequently
MOSFET source/drain orientation is not reversible within this circuit. The orientation shown in the
schematic and used in the RDK can provide a low impedance path to ground when power is off,
in violation of the PCI Bus Power Management Interface Specification. Thus inserting the RDK
into a PCI slot while the system is in a low-power state could cause the system to detect PME#
assertion and consequently wake up.
Additionally, the MOSFET gate voltage from voltage divider R34 and R44 (both 240K) is too high,
and could allow the MOSFET to turn on briefly, asserting PME#, if the Drain voltage sags.
Change the R34 value from 240K to 330K.
- 4 - PCI 9030/LITE-RDK-ER-P0-2.3
Workaround:
Reverse U15 pins 2 and 3 to match the correct MOSFET orientation detailed below:
PLX PME#
PCI PME#
D
S
G
330K
240K
0.1µF
Vdd
N-Channel MOSFET
FDN335N
Also change the value of the resistor between the MOSFET gate and the supply voltage to
330K as shown in the circuit above.
Copyright © 2005 by PLX Technology, Inc. All rights reserved. PLX is a trademark of PLX Technology, Inc. which may be
registered in some jurisdictions. All other product names that appear in this material are for identification purposes only
and are acknowledged to be trademarks or registered trademarks of their respective companies. Information supplied by
PLX is believed to be accurate and reliable, but PLX Technology, Inc. assumes no responsibility for any errors that may
appear in this material. PLX Technology reserves the right, without notice, to make changes in product design or
specification.
- 5 - PCI 9030/LITE-RDK-ER-P0-2.3
/
