Broadcom PEX 8112 AA Errata List User guide

Brand: Broadcom

Model: PEX 8112 AA Errata List

Type: User guide

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PEX 8112AA Errata Documentation

A. Affected Silicon Revision

This document details Errata for the following silicon:

Product

Revision

Description

Status

PEX 8112

Single Lane

PCI Express-to-PCI Bridge

Full Production

B. Documentation Revision

The following documentation is the silicon baseline functional description:

Document

Version

Description

Publication Date

PEX 8112AA Data Book

1.2

Data Book

October, 2008

C. Errata Documentation Revision History

Revision

Publication Date

Description

1.0

April 2007

Baseline.

1.1

August 2007

Added erratum 2 and 3.

1.2

January 2008

Deleted the incorrect workaround description in erratum 3.

1.3

March 2012

Added erratum 4.

1.4

May 2012

Added erratum 5, documentation corrections

1.5

June 2012

Added erratum 6, documentation corrections

D. Errata Summary

Mode

Description

F, R

1. 66MHz PCI Bus Timing Violations

F, R

PCLKO 66MHz waveforms out of specification

L1 Entry/Exit Problem

PEX 8112 may not start PCI access within 16 clocks of GNT# assertion in

specific cases.

Transmitted Error Messages have Requester ID = 0x0000

F, R

PCI Memory Read Multiple (MRM) or Memory Read Line (MRL) with

Address 4 Bytes Below 4K Boundary may be Forwarded to PCI Express

PEX 8112AA

Errata Documentation

Revision 1.5

June 2012

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with Incorrect Byte Enable Field

Legend:

 F = Forward Bridge mode

 R = Reverse Bridge mode

 F, R = Forward or Reverse Bridge mode

E. Errata Details

1. 66MHz PCI Bus Timing Violations

Description

In Forward or Reverse Bridge mode, at 66 MHz, the PCI clock to output timing

requirement of 6 ns is violated by 296 ps, resulting in a clock to output delay of 6.296

ns. The PCI input setup requirement of 3 ns (for point-to-point and bused signals,

respectively) is violated by 799 ps. There are no timing violations on the PCI input setup

requirement of 5ns.

Solution/Workaround

None.

Impact

In most applications, there is sufficient margin to cover these minor violations.

2. PCLKO 66MHz waveforms out of specification

Description

When the PCLKO output is programmed for 66MHz, the high time is only 5 nsec. The

PCI specification requires that the high and low times be between 6 and 9 nsec. Also,

there is excessive jitter due to several factors:

1. Jitter of the 100MHz Refclk.

2. Duty cycle of the 100MHz Refclk

3. Internal Refclk clock tree skew.

4. Skew through clock divider logic.

Since the 66MHz PCLKO rising and falling edges are triggered by both the rising and

falling edges of Refclk, the output will always be susceptible to jitter based on item 2.

The PCIe spec allows for a duty cycle of 40% to 60%, resulting in up to 2 nsec of jitter

on PCLKO. Items 3 and 4 could contribute several hundred picoseconds of jitter, too.

Workaround

Use an external PCI clock source.

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Impact

For 66MHz applications, an external clock source is required for devices that have clock

inputs that require a 50% duty cycle clock

3. L1 Entry/Exit Problem

Description

In Reverse Bridge mode, there are three types of problems associated with the L1

ASPM link state in PEX 8112’s downstream PCI Express interface that have been

identified. One of these problems can occur when PEX 8112’s PCI Express link is

entering L1 state. The other two problems can occur when PEX 8112’s PCI Express

link is exiting L1 state. These cases are described as follows:

Case #1 PCI Express Bus Deadlock on PEX 8112 Entry to L1

A bus deadlock condition can occur on PCI Express when PEX 8112 is transitioning its

downstream PCI Express link to the L1 link state, if the following sequence of events

occurs.

1. The PCI host places PEX 8112’s downstream PCI Express device into D3

hot

power management D-state.

2. The downstream device begins its transition into the L1 state and starts

transmitting PM_Enter_L1 messages upstream to the PEX 8112.

3. Before PEX 8112 receives and responds to the downstream device’s

PM_Enter_L1 message, PEX 8112 receives a PCI Configuration Read/Write

access from the PCI Host addressed to the downstream PCI Express device.

This access is then forwarded to the downstream device by PEX 8112 as a

CfgRd (or CfgWr) TLP. At this point, PEX 8112 expects to receive a

completion from the downstream device, so it can in-turn complete the

access from the PCI Host.

4. The downstream PCIe device, however, having already started its transition

to the L1 state, is not allowed to transmit a completion to the CfgRd/Wr TLP

until it has received a PM_Req_ACK message from the PEX 8112. (See PCI

Express Base 1.0a, sec 5.3.2.1)

In this case, the PEX 8112 will not transmit PM_Req_ACK to the downstream device

until it receives the completion, and the downstream device is not permitted to return

the completion for the pending CfgRd/Wr request until it receives PM_Req_ACK from

PEX 8112, resulting in a deadlock.

Case #2. Corrupted TLP or PCI Express Link Failure on L1 Exit

The PEX 8112, when transitioning its downstream PCI Express link out of L1 link state,

may transmit a corrupted (mal-formed) TLP, and in some cases fail completely (lock-

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up), requiring hardware reset or power cycling of the system, if the following sequence

of events occurs:

1. The PCI host places PEX 8112 into D3

hot

power management D-state.

2. Upon transition to D3

hot

, PEX 8112 successfully transitions its downstream PCI

Express link to L1 state, as required.

3. With PEX 8112’s PCI Express link in L1 state, the PCI host initiates a PCI

Configuration Read access (or write) on PEX 8112’s upstream PCI bus

addressed to the downstream PCI Express device.

In this case, PEX 8112 is expected to transition its downstream PCI Express link from

L1 to L0, forward (transmit) the CfgRd (or CfgWr) request TLP to its downstream

device, and return it’s completion to the PCI host. The problem, however, is that PEX

8112 attempts to transmit the forwarded CfgRD (or CfgWr) TLP before its PCI Express

link has completed its transition to L0. When this happens, the PEX 8112 may fail in

one or both of the ways described below:

 Transmission of a corrupted (mal-formed) CfgRd/CfgWr TLP to PCI Express

 Complete failure (lock-up) of the PEX 8112’s PCI Express interface, requiring

hardware reset or cycling of system power to clear.

Workaround

None.

Impact

PCI Host bridges and/or BIOS firmware that perform configuration access to PEX

8112’s downstream device after placing it and/or the PEX 8112 into D3

hot

D-State may

end up in an infinite loop retrying the CfgRd, causing the system to hang when entering

stand-by or hibernate system power states.

4. PEX 8112 May Not Start a PCI Access within 16 Clocks of GNT#

Assertion in Specific Cases

Description

When PEX 8112 is configured as a Forward bridge using an external PCI arbiter

(EXTARB = High), if a non-posted request (Memory Read, Configuration Read, etc.) is

received on PCI Express targeting PCI bus and this request is immediately followed by

two or more Vendor-Defined Messages, PEX 8112 may fail to start the non-posted

request on PCI bus within 16 clocks of receiving GNT#, as required by the PCI Local

Bus Specification, v 2.3, section 3.4.1. PEX 8112 will assert REQ# upon receiving the

initial non-posted request, but will delay starting this access on PCI bus while the

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Vendor-Defined messages are being decoded and discarded. Depending on when

GNT# is received, this delay may exceed the 16 clock rule.

Workaround

1. Use Internal Arbiter mode (EXTARB = Low).

2. Avoid sending back-to-back MessageD or Message requests to PEX 8112 in the

presence of downstream non-posted requests.

3. Disable any “broken master” feature of the external arbiter that would cause

removal of GNT# after 16 clocks. If the external arbiter can tolerate the added

delay, traffic will resume normally with no loss of data.

Impact

In the system where this problem was discovered, the external arbiter was removing

GNT# after 16 clocks, resulting in a system hang.

5. Transmitted Error Messages Have Requester ID=0x0000

Description

When PEX 8112 is configured as a Forward bridge and error message generation is

enabled as described in section 10.1 of the PEX 8112 Data Book, certain error

messages generated will have a Requester ID = 0x0000, regardless of the value

programmed in the Primary Bus Number register (18h). Affected message types are

listed below:

 ERR_COR messages, including

- Receiver Error

- Bad TLP

- Bad DLLP

- Replay Timeout

- Replay Number Rollover

 ERR _NONFATAL messages, including

- Poisoned TLP

- Unsupported Request

- Completion Timeout

- Completer Abort

- Unexpected Completion

 ERR_FATAL messages, including

- Link Training Error

- Data Link Layer Protocol Error

- Flow Control Protocol Error

- Received Malformed TLP

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Workaround

1. Do not enable error message generation (default). Program DEVCTL[2:0] =

000b

Impact

Error messages with an invalid Requester ID field can cause unpredictable response by

the PCI Express Root Complex.

6. PCI Memory Read Multiple (MRM) or Memory Read Line (MRL) with

Address 4 Bytes Below 4K Boundary may be Forwarded to PCI

Express with Incorrect Byte Enable Field

Description

A PCI Memory Read Multiple (MRM) or Memory Read Line (MRL) command with an

address 4 bytes below the 4K address boundary should be forwarded to PCI Express

as a MemRd Request TLP for 1 DW with BE=1111_0000, regardless of the state of the

PCI BE[3:0] signals (PCI byte enables are ‘don’t care’). Actual behavior of the PEX

8112 in this case will be to generate a MemRd Request TLP for 1 DW with

BE=xxxx_0000, where xxxx = BE[3:0]# (PCI byte enables are forwarded to PCI

Express).

Workarounds

1. Insure that MRM commands have byte enables asserted.

2. Avoid using MRM command to access addresses 4 bytes below 4K boundary

Impact

In the system where this issue was seen, the PCI master was sending MRM command

with all byte enables de-asserted. This resulted in a PCI Express MemRd TLP with

BE=0000_0000 (dummy read), and data returned were invalid.

F. Documentation Corrections and Updates

1. Figure 19-2, Serial EEPROM Timing Diagram. T

VAL

is incorrectly shown. T

VAL

measured from the rising edge of EECLK, not the falling edge.

2. Section 4.1.1.5, replace the phrase “when the secondary bus RST# is asserted” with

the phrase “when the Bridge Control Register[Secondary Bus Reset] bit is set

(3Eh[6] = 1b)”.

registered in some jurisdictions. All other product names that appear in this material are for identification purposes only and are

acknowledged to be trademarks or registered trademarks of their respective companies. Information supplied by PLX is believed to

be accurate and reliable, but PLX Technology, Inc. assumes no responsibility for any errors that may appear in this material. PLX

Technology reserves the right, without notice, to make changes in product design or specification.

Broadcom PEX 8112 AA Errata List User guide

Broadcom PEX 8112 AA Errata List User guide

Broadcom PEX 8112 AA Errata List User guide

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