Broadcom PEX 8648 Silicon Errata List User guide

PEX 8648

Silicon Revisions and Errata List

CONFIDENTIAL PROPRIETARY INFORMATION

NDA REQUIRED

Version 1.9

June 2011

Website: www.plxtech.com

Technical Support: www.plxtech.com/support

June 16, 2011

PEX 8648 Errata v1.9

A. Affected Products and Silicon Revisions

This document details Errata for the following products and silicon revisions:

Product Description Revision Status

PEX 8648 48-Lane, 12-Port PCIe Gen 2 Switch

AA General Sampling

AB Conditional Production

BB Full Production

B. Device Documentation Version

The following documentation is the baseline functional description of the silicon:

Document Version Description Publication Date

PEX 8648 Data Book

1.2 Data Book October 2010

C. Errata Documentation Revision History

Revision Publication Date Description

0.5 February 2008



Initial publication of errata list based on errata found

during simulation and evaluation of early silicon samples

(Erratum 1, 2, 3, & 4)

0.6 March 2008



Added Erratum 5

 Added Erratum 6

 Added Erratum 7

 Added Erratum 8

 Added Erratum 9

 Edited Errata Summary Table (Erratum 3)

0.7 April 2008



Added Erratum 10

 Added Erratum 11

 Added Erratum 12

 Added Erratum 13

0.8 May 2008



Added Erratum 14

 Added Erratum 15

 Added Erratum 16

 Added Erratum 17

0.9 July 2008



Added Erratum 18

 Added Erratum 19

 Added Erratum 20

 Edited Erratum 17

0.91 October 2008



Added Erratum 21

 Added Erratum 22

0.92 November 2008

 Added Erratum 23

1.0 February 2009



Added Erratum 24

 Added Erratum 25

 Added Erratum 26

1.1 March 2009



Added Erratum 27

 Added Erratum 28

PEX 8648 Errata v1.9

Revision Publication Date Description

1.2 April 2009



Added Erratum 29

 Added Erratum 30

 Edited Erratum 24 (Workaround #2)

 Edited Erratum 28 (Removed Workaround #3)

1.3 June 2009



Edited Erratum 22 (Added Workarounds, Affects BB

Silicon Revision as well)

1.4 September 2009



Added Erratum 31

 Added Erratum 32

 Edited Erratum 24 (Modified the Description)

1.5 December 2009



Added Erratum 33

 Added Caution 1

1.6 January 2010



Edited Erratum 33 (Corrected register bit reference)

 Edited Caution 1 (Updated Workaround and Impact)

1.7 March 2010

 Added Caution 2

1.8 July 2010

 Added Erratum 34

1.9 June 2011



Added Erratum 35

 Added Erratum 36

 Added Erratum 37

 Edited Erratum 28 (Added 3

rd

workaround)

D. Errata Summary

# Description

Risk

Category

Silicon Revisions Affected?

AA AB BB

1 Incorrect Header Log Register Value in NT Mode Low

Yes

2 Undependable Lane Reversal with Partial Lanes Low

Yes

No

3

Improper Data Rate & De-emphasis Level

Sequence

Low

Yes

No

4 Surprise Down Error Messages Not Generated Low

Yes

No

5 Exiting ASPM Causes Link Down Medium

Yes

No

6

Unsuccessful Dynamic Link Width/Speed

Change

Low

Yes

No

7

ARI Forwarding Supported & Forwarding Enable

Bits

Medium

Yes

No

8 Incorrect NT Port Vendor Specific Capability ID Medium

Yes

No

9 Incorrect Modified Compliance Pattern Disparity Medium

Yes

No

10

Flow Control Protocol Error Severity and

Surprise Down Severity in Upstream Port

Low

Yes

No

11 Completion Timeout Error Severity Low

Yes

No

PEX 8648 Errata v1.9

# Description

Risk

Category

Silicon Revisions Affected?

AA AB BB

12

EEPROM Load Cannot Override Strap Pin to

Enable NT

Low

Yes

No

13 Stuck in Recovery Low

Yes

No No

14 Scrambler Disable Training Control Bit Low Yes Yes No

15

Extended Synch Bit Non-functional in Gen 2

Mode

Low Yes Yes No

16

Idle_to_Rlock Transitioned Flag Broken in

Recovery State in Gen 2 Mode

Low

Yes

Yes No

17 EEPROM Loading of Port Configurations Low

Yes

Yes Yes

18 Bad DLLP/TLP Errors in ASPM L1 or L0s Medium Yes Yes No

19

Cannot Support 600ppm Offset in Asynchronous

Systems

Low

Yes

Yes Yes

20 Link Speed Change with L1 ASPM Enabled Medium

Yes

Yes No

21 Primary Bus Number 7 Low Yes Yes No

22 Rx Pins Do Not Work with AC-JTAG Instructions

Low Yes Yes

Yes

23

Unexpected DL_DOWN in the Middle of TLP

Can Cause FC Credit Loss

Low Yes Yes

No

24 Incorrect TCB Capture of Training Sets

Low Yes

Yes Yes

25

Receiver Error on Virtual Side of Non-

Transparent Port

Low Yes

Yes Yes

26 Correctable Error Status Bit Set Erroneously

Low Yes

Yes Yes

27

Unreliable Port Disable/Re-enable when using

0x234h[19:16]

Low Yes

Yes Yes

28

Legacy Interrupts Cannot be Generated in NT

Mode if Hot Reset Propagation is Disabled

Low Yes

Yes Yes

29

Inconsistent Default Value of Power Indicator

Control Register

Low Yes

Yes Yes

30

Inconsistent Default Value of Power Controller

Control Register if MRL is not locked

Low Yes

Yes Yes

31 Incorrect ACS P2P Completion Routing

Low Yes

Yes Yes

32 ACS Upstream Forwarding Issue Low Yes Yes Yes

PEX 8648 Errata v1.9

# Description

Risk

Category

Silicon Revisions Affected?

AA AB BB

33 Analog Loopback Slave Mode Support

Low Yes

Yes Yes

34

Port Arbitration Table can’t be Loaded using the

EEPROM

Low Yes Yes Yes

35 AC JTAG Functionality Does Not Work Low Yes No No

36

Upstream Port LTSSM Exits From Hot-Reset

State After it Receives TS1 With Hot-Reset TCB

Clear

Low Yes

Yes Yes

37

PCIe Links Dropped When JTAG Bypass is

Enabled

Low Yes

Yes Yes

E. Caution Summary

# Description

Risk

Category

Devices

Excepted

Silicon Revisions Affected?

AA AB BA BB

1

Receivers Detected on Lanes that

Do Not Exit Electrical Idle Polling

Low None Yes Yes Yes Yes

2

Speed Change Bit (TS1) Asserted

After L1 PM State Exit

Low None

No

No No

Yes

PEX 8648 Errata v1.9

F. Errata List

Note: Throughout this document, unless specified otherwise, “Switch” is used to indicate the

PEX 8648 switch.

1. Incorrect Header Log Register Value in NT Mode

Risk Category: Medium Silicon Revisions Affected: AA, AB, BB

Description

This erratum only affects designs using NT Mode.

When a TLP is received on the NT link-side (which is a 64-bit BAR) and the

translated TLP needs to be a 32-bit TLP, if this TLP hits a port that has its

memory enable (for downstream ports) or master enable (for upstream ports)

inactive, the error logging uses the virtual-side address space (the translated

address), but it is tagged with 64-bit flag. Hence, the header log will be a 64-bit

TLP with upper 32 bits 0 instead of its equivalent 32-bit version.

Solution/Workaround

None.

Impact

NT designs using 64 to 32 bit address translation may see an incorrect header

log register value due to this bug.

Back to Errata Summary Table

2. Undependable Lane Reversal with Partial Lanes

Risk Category: Low Silicon Revisions Affected: AA

Description

This erratum only affects designs using lane reversal with partial lanes (some of

the lanes being reversed are not connected to anything) and there is more than 1

port on that station. It does not affect x16 ports.

For example, if a 2-lane (x2) link is being used on a 4-lane (x4) slot and the lanes

are reversed so that Lane 1 is connected to Lane 0 of another device, the link

may not come up if another port on the same station is already linked up.

The same is true if a 2-lane (x2) or 4-lane (x4) device is connected to an 8-lane

(x8) slot and the lanes are reversed to make Lane 1 or Lane 3 to be connected to

the other device’s Lane 0.

Solution/Workaround

None.

PEX 8648 Errata v1.9

Impact

Lane reversal cannot be used for some port configurations if partial lanes are

being used.

Back to Errata Summary Table

3. Improper Data Rate & De-Emphasis Level Sequence

Risk Category: Low Silicon Revisions Affected: AA

Description

The PCI Express Gen2 specification states that data rate and de-emphasis level

settings should repeat the following sequence every time it enters polling

compliance state:

Data Rate = 2.5 GT/s, De-emphasis Level = -3.5 dB.

Data Rate = 5.0 GT/s, De-emphasis Level = -3.5 dB

Data Rate = 5.0 GT/s, De-emphasis Level = -6.0 dB

In the case of the Switch, the sequence is as follows:

Data Rate = 2.5 GT/s, De-emphasis Level = -3.5 dB.

Data Rate = 5.0 GT/s, De-emphasis Level = -6.0 dB

The “Data Rate = 5.0 GT/s, De emphasis Level = -3.5 dB” setting can be

achieved by writing to the Link Control2 register bit 4 and bit 12 and bits 3:0.

Solution/Workaround

None.

Impact

To achieve a data rate of 5.0GT/s and de-emphasis level of -3.5dB, the Link

Control2 register needs to be written to. One of the specification-defined ways to

achieve this (as described above) cannot be used.

Back to Errata Summary Table

PEX 8648 Errata v1.9

4. Surprise Down Error Messages Not Generated

Risk Category: Low Silicon Revisions Affected: AA

Description

The Uncorrectable Error Status register bit 5, Surprise Down Error Status, will not

be set when a link goes down, and the corresponding error message will not be

generated. Also, the data link layer state changed bit in the slot status register is

not reliable.

Solution/Workaround

None.

Impact

Rather than getting an error message in case of a Surprise Down, the system will

need to rely on completion timeouts or polling the link status register for the link-

width.

Back to Errata Summary Table

5. Exiting ASPM Causes Link Down

Risk Category: Medium Silicon Revisions Affected: AA

Description

Going in and out of Active State Power Management States sometimes results in

link retrain or negotiating down the link width.

Solution/Workaround

None (user needs to turn off ASPM).

Impact

If a system BIOS or software is not able to handle link down or link retrain, the

system will hang. Most systems allow ASPM to be turned off, but some systems

may require it.

Back to Errata Summary Table

6. Unsuccessful Dynamic Link Width/Speed Change

Risk Category: Low Silicon Revisions Affected: AA

Description

Dynamically changing link speed or link width from Gen 1 to Gen 2, or vice-

versa, could result in lower speed/width than expected (observed once or twice in

a million events).

PEX 8648 Errata v1.9

Solution/Workaround

Control link speed/width through software controllable registers for dynamic

changes during run time, confirm speed/width and re-program if not correct

value.

Impact

Systems that do not use hardware initiated dynamic speed/width changes should

not be affected by this. In systems where applicable, it may cause the link to

settle in Gen 1 or link up with the wrong width.

Back to Errata Summary Table

7. ARI Forwarding Supported & Forwarding Enable Bits

Risk Category: Medium Silicon Revisions Affected: AA

Description

ARI Forwarding supported bit in Device Capabilities2 Register for a switch

upstream port should be 1’b0 and ARI Forwarding Enable bit in the Device

Control2 Register for the upstream port of a switch should be hardwired to 1’b0.

In the Switch, however, ARI Forwarding supported bit is 1’b1 for the upstream

port and the ARI forwarding enable bit for the upstream port is Read/Writeable.

Solution/Workaround

User needs to disable the upstream port ARI forwarding supported bit using

EEPROM. This also disables the ARI forwarding enable bit Read/Writeable

privilege for the upstream port.

Impact

If customer system is planning to use ARI, EEPROM or I

2

C cycle will be needed

to write to ARI forwarding supported bit before BIOS scan.

Back to Errata Summary Table

8. Incorrect NT Port Vendor Specific Capability ID

Risk Category: Medium Silicon Revisions Affected: AA

Description

For customers using an NT port, the PLX vendor specific capability starts at

address 0xC8 on the type0 header for the Virtual Side and the Link Side uses an

incorrect capability ID of 0xb. It should use the correct ID for vendor specific

capability which is 0x9 (0xb is Compact PCI Central resource control capability).

Solution/Workaround

Standard software would not understand that this is a vendor specific capability

on the NT port.

PEX 8648 Errata v1.9

Impact

Customer software will need to be written in such a way that it understands that

this is a PLX vendor specific capability.

Back to Errata Summary Table

9. Incorrect Modified Compliance Pattern Disparity

Risk Category: Medium Silicon Revisions Affected: AA, AB

Description

The compliance patterns for Lanes 1 thru 7 in each octal of the Switch is

incorrect.

The delay sequence specified by the PCIe 2.0 spec is D D K28.5- D21.5 K28.5+

D10.2 D D where D symbols are K28.5 characters with appropriate disparity.

Lane 0 exhibits the following pattern: K28.5- K28.5+ K28.5- D21.5 K28.5+ D10.2

K28.5- K28.5+ followed by repeating sequences of K28.5- D21.5 K28.5+ D10.2

Lanes 1 thru 7 exhibit the following K28.5+ K28.5- K28.5+ D21.5 K28.5- D10.2

K28.5+ K28.5- followed by repeating sequences of K28.5+ D21.5 K28.5- D10.2.

Solution/Workaround

None.

Impact

The wrong sequence of K28.5+ D21.5 K28.5- D10.2 acts to degrade the high

frequency content of the Compliance Pattern.

Back to Errata Summary Table

10. Flow Control Protocol Error Severity and Surprise Down

Severity in Upstream Port

Risk Category: Low Silicon Revisions Affected: AA

Description

The Flow Control Protocol Error Severity in all ports and the Surprise Down

Severity in the upstream port is hardwired to 1’b0. However, per the PCIe

Specification, it should be hardwired to 1’b1.

Solution/Workaround

None.

Impact

None.

Back to Errata Summary Table

PEX 8648 Errata v1.9

11. Completion Timeout Error Severity

Risk Category: Low Silicon Revisions Affected: AA

Description

In the Switch, the Completion Timeout Error Severity bit is Read/Writeable.

However, per the PCIe Specification, switches do not generate non posted

transactions so all ports of a switch should hardwire this bit to 1’b0.

Solution/Workaround

None.

Impact

None.

Back to Errata Summary Table

12. EEPROM Load Cannot Override Strap Pin to Enable NT

Risk Category: Low Silicon Revisions Affected: AA

Description

The EEPROM load in the Switch is not able to override the strap pin to enable

NT mode.

Solution/Workaround

None.

Impact

Systems that strap the chip to not enable NT mode, and then use an EEPROM to

override the strapping pin to enable NT (0x1DC bit 18), will not be able to do so.

Back to Errata Summary Table

13. Stuck in Recovery

Risk Category: Low Silicon Revisions Affected: AA

Description

There is a state transition in the Recovery state where the Switch does not start

the timers that should cause a timeout if Recovery is not successful. This

transition is from Recovery Idle to Recovery.RcvrLock. This erratum is applicable

in Gen 1 mode as well as Gen 2 mode.

Solution/Workaround

None.

PEX 8648 Errata v1.9

Impact

In a very noisy system, the Switch could get stuck in Recovery when it should

timeout and go to Detect.

Back to Errata Summary Table

14. Scrambler Disable Training Control Bit

Risk Category: Low Silicon Revisions Affected: AA, AB

Description

The Scrambler Disable Training Control bit needs to be latched in the

Configuration Complete state and should not be latched in the Recovery state.

However, the Switch latches the Scrambling Disable Training Control bit in the

Recovery state.

Solution/Workaround

Program the corresponding station Port0 Offset 230h Bit[1] to disable scrambling

for Port0, Bit[5] to disable scrambling for Port1, Bit[9] to disable scrambling for

Port2, and Bit[13] to disable scrambling for Port3.

Impact

Customer will not be able to disable scrambling in the Configuration state. If the

customer tries to enable scramble again, the link will not come up.

Back to Errata Summary Table

15. Extended Synch Bit Non-functional in Gen 2 Mode

Risk Category: Low Silicon Revisions Affected: AA, AB

Description

The Extended Synch bit functionality is non-functional in Gen 2 mode. If the

Extended Synch bit is set in Recovery.RcvrLock state, the transmitter is

supposed to send a minimum of 1024 consecutive TS1 ordered sets before

transitioning to Recovery.RcvrCfg state. However, the Switch keeps on sending

TS1 ordered sets and does not move to Recovery.RcvrCfg state. After a 24ms

timeout, the Switch will attempt to reset the link speed back to Gen 1.

Solution/Workaround

None.

Impact

Customer cannot use the Extended Synch bit in the Switch.

Back to Errata Summary Table

PEX 8648 Errata v1.9

16. Idle_to_Rlock Transitioned Flag Broken in Recovery State in

Gen 2 Mode

Risk Category: Low Silicon Revisions Affected: AA, AB

Description

The idle_to_rlock_transitioned flag does not assert when the Recovery state

machine transitions from Recovery.Idle state to Recovery.RcvrLock state while in

Gen 2 mode. This causes the Recovery state machine to continuously cycle

between Recovery.RcvrLock->Recovery.RcvrCfg->Recovery.Idle states as long

as it is receiving TS2 training sets with valid link and lane numbers. This in turn

leads to a longer than necessary timeout and a delayed return to Detect state.

Solution/Workaround

None.

Impact

It will take a bad link a little longer to go down due to a longer timeout.

Back to Errata Summary Table

17. EEPROM Loading of Port Configurations

Risk Category: Low Silicon Revisions Affected: AA, AB, BB

Description

The EEPROM load of Station 1 and Station 2 port configurations (0x574h) does

not update unless the Station 0 port configuration is also changed during the

EERPOM load.

Solution/Workaround

The EEPROM load to change port configurations needs 1 extra write from the

EEPROM. The first write changes the Station 0 port configuration to a non-strap

value. The second write changes port configurations for all stations to the desired

value.

Impact

The customer may need to execute 1 extra write through the EEPROM if only the

Station 1 and/or Station 2 port configuration(s) need to be changed.

Back to Errata Summary Table

PEX 8648 Errata v1.9

18. Bad DLLP/TLP Errors in ASPM L1 or L0s

Risk Category: Medium Silicon Revisions Affected: AA, AB

Description

If ASPM L1 or L0s is enabled on the Switch, Bad DLLP/TLP errors are logged in

the Switch and spurious NAKs are sent out.

Solution/Workaround

None (user needs to turn off ASPM).

Impact

ASPM L1 and L0s cannot be used.

Back to Errata Summary Table

19. Cannot Support 600ppm Offset in Asynchronous Systems

Risk Category: Low Silicon Revisions Affected: AA, AB, BB

Description

The Switch supports up to a 500ppm offset from other devices in an

asynchronous system as opposed to the 600ppm that the PCIe Base

Specification, r2.0 requires.

Solution/Workaround

Reference clocks need to have tighter control.

Impact

Most clock sources compliant to PCI Express CEM specification exhibit less than

100ppm of frequency variation (including temperature and aging variance). There

should be no impact due to this erratum in CEM Express compliant systems.

Back to Errata Summary Table

20. Link Speed Change with L1 ASPM Enabled

Risk Category: Medium Silicon Revisions Affected: AA, AB

Description

If L1 ASPM is enabled and speed change is requested for a particular link of the

Switch, and the retrain link bit is set, the link will come out of low power state but

the speed change will not take place.

Solution/Workaround

If the link speed does not change on the first try, try again.

Impact

If ASPM is enabled, link speed change may not execute properly.

PEX 8648 Errata v1.9

Back to Errata Summary Table

21. Primary Bus Number for Port 7

Risk Category: Low Silicon Revisions Affected: AA, AB

Description

When software reads the primary bus number for Port 7 on the Switch, the

device returns the value from Port 6 primary bus number register. This issue

affects the read contents returned by the Switch for this register only; the

configuration contents captured, such as bus numbers, Base and Limit settings,

etc. occur normally and the routing of the packets through this port is not

affected.

Solution/Workaround

Do not read the primary bus number register on Port 7.

Impact

Customers using Port 6 or Port 7 as the upstream port will read incorrect values

from the Primary Bus register on Port 7. When the upstream port is neither Port 6

nor Port 7, there is no impact.

Back to Errata Summary Table

22. Rx Pins Do Not Work with AC-JTAG Instructions

Risk Category: Low Silicon Revisions Affected: AA, AB, BB

Description

The level output on the Switch RX pins used by the AC JTAG instructions is not

stable and consequently it is not latched in the Switch by the boundary scan

chain.

Solution/Workaround

There are two workarounds:

1. Bring up the links and check the widths using the PEX_PORT_GOOD# pins.

The link width and speed can also be checked using I

2

C.

2. The external device can put the Switch into loopback mode and then check

the integrity of the link. External devices connected to the Switch can also be

put in loopback mode using the Switch and the link integrity can be checked

using PRBS or other user-programmable test patterns.

Impact

The RX pins of the Switch cannot be used with AC-JTAG instructions. The TX

pins of the Switch are not affected and can be used with AC-JTAG instructions.

Back to Errata Summary Table

PEX 8648 Errata v1.9

23. Unexpected DL_DOWN in the Middle of TLP Can Cause FC

Credit Loss

Risk Category: Low Silicon Revisions Affected: AA, AB

Description

If a TLP starts on a port of the Switch and a device connected to the Switch is

disconnected either by removing its power supply or by physically disconnecting

it, it is possible that one TLP will not be de-allocated and will consume memory

space until the Switch is reset either by a Fundamental Reset or by a Hot Reset

from the upstream port. The same issue can occur if the noise on the link

manifests itself as an “STP” symbol.

A DL_DOWN due to noise where the device connected to the Switch is sending

at least a few training sets before the link goes down will not have this issue. If

DL_DOWN is caused by noise, the device connected to the Switch is supposed

to go into recovery and send training sets for at least 24ms before the link goes

down. If the Switch receives 2 consecutive good training sets, this erratum will

not occur.

Solution/Workaround

Set the “Link Disable” or “Secondary Bus Reset” bit before removing the link.

Impact

Surprise removal of a device connected to the Switch multiple times can lead to

reduced Switch performance.

Back to Errata Summary Table

24. Incorrect TCB Capture of Training Sets

Risk Category: Low Silicon Revisions Affected: AA, AB, BB

Description

In the case where excess noise exists on a link, the combination of a “COM”

symbol followed by noise can result in the incorrect misinterpretation of Ordered

Sets. The misinterpretation of said sequence might cause the LTSSM to remain

in Loopback State until an assertion of a Hot Reset or a Fundamental Reset is

detected. Due to what is required to create this condition, this problem has only

manifested itself in asynchronous clocked systems.

Solution/Workaround

There are 3 possible workarounds for this erratum:

1. Assert a Hot Rest or Fundamental Reset to the device.

2. Set register 0x228h[5] = 1 in order to mask Training Control Bits (TCB) in

the training sets. Note that setting this bit affects all ports in the station and

if the upstream port is part of the affected station, can cause the upstream

PEX 8648 Errata v1.9

port to ignore the Hot Reset TCB – preventing the switch to be reset from

such a training set.

3. Disable and then enable the failing port using register 0x234h to clear the

LTSSM.

Impact

The link might fail to achieve link-up status due to the noise on the link.

Back to Errata Summary Table

25. Receiver Error on Virtual Side of Non-Transparent Port

Risk Category: Low Silicon Revisions Affected: AA, AB, BB

Description

If a Correctable Error (FC4h), Uncorrectable Error (FB8h), Bad DLLP (1ECh), or

Bad TLP (1E8h) is detected on the Link side of the NT Port, the corresponding

status is reflected on both NT Link and NT Virtual registers on both the NT Link

and NT Virtual interfaces whereas it should only be reflected on the NT Link side.

Solution/Workaround

None.

Impact

The NT Virtual side does not have any link associated with it. Hence, the NT

Virtual Error Registers will reflect an incorrect error status. If the NT Virtual side

error registers have error status set for the one of the errors mentioned above (in

the Description), this error status actually reflects that of the NT Link side.

Back to Errata Summary Table

26. Correctable Error Status Bit Set Erroneously

Risk Category: Low Silicon Revisions Affected: AA, AB, BB

Description

When L0s ASPM is enabled, spurious receiver errors could get logged which

could result in ERR_CORR messages being received by the host.

Solution/Workaround

When L0s ASPM is enabled, set the Correctable Error Mask bit 0xFC8h[0]=1 to

prevent the ERR_CORR message from being sent out due to receiver errors.

Note that when this bit is set, other types of errors could still trigger ERR_CORR

messages if they occur.

Impact

Spurious ERR_CORR messages could be received and the switch might set the

Correctable Error Detected Bit (0x72h[0]) when L0s ASPM is enabled. Although

PEX 8648 Errata v1.9

this erratum occurs when ASPM is enabled, it does not affect the functionality of

ASPM.

Back to Errata Summary Table

27. Unreliable Port Disable/Re-enable when using 0x234h[19:16]

Risk Category: Low Silicon Revisions Affected: AA, AB, BB

Description

If a customer uses register 0x234h[19:16] to disable a particular port when the

link is at Gen 2 speed, the link may not come up when the customer re-enables

the port by clearing these bits back to the default value.

Solution/Workaround

1. To bring a link down, set link disable 0x78h[4] and then set 0x78h[5] to retrain

the link.

2. To disable a port, bring the target link speed to Gen 1 by writing to 0x98h[3:0],

waiting for 10 microseconds, and then using port disable to disable the port.

3. If enabling the port after disabling it does not bring the link up, disable it one

more time and enable it again. This will bring the link up.

Impact

At Gen 2 speed, customer cannot reliably use the port disable/re-enable

functionality of register 0x234h[12:16].

Back to Errata Summary Table

28. Legacy Interrupts Cannot be Generated in NT Mode if Hot Reset

Propagation is Disabled

Risk Category: Low Silicon Revisions Affected: AA, AB, BB

Description

In NT mode, if Hot Reset propagation is disabled by setting 0x1DCh[20] and a

Hot Reset occurs on the upstream port, subsequent doorbell interrupts to the

Root Complex cannot be generated using the doorbell registers. Furthermore,

interrupts from the downstream ports will not be forwarded upstream. Systems

without Hot Reset will not see this erratum.

Solution/Workaround

There are three workaround options:

1. Let the Hot Reset reset the whole device. Do not set 0x1DCh[20].

2. Use MSI in the system if Hot Reset propagation needs to be disabled in the

Switch.

3.

Use the Training Control Bit (TCB) Capture Disable bit (0x228[5]) to disable the

Hot Reset rather than the 0x1DC[20] bit.

PEX 8648 Errata v1.9

Impact

If legacy interrupts are needed in a system, a Hot Reset propagation cannot be

disabled on the upstream port of the Switch using 0x1DCh[20]. A Hot Reset is

required to reset the whole device or disabled using 0x228[5].

Back to Errata Summary Table

29. Inconsistent Default Value of Power Indicator Control Register

Risk Category: Low Silicon Revisions Affected: AA, AB, BB

Description

The default values of power indicator control bits [9:8] and attention indicator

control bits [7:6] in the Slot Control register (offset 80h) in the hot plug capable

downstream ports of the Switch are invalid. The legal values should be non-zero,

but these two fields show up as 2‘b00.

Solution/Workaround

Have the software ignore the initial value of the power indicator control and

attention indicator control bits.

Impact

Slight modifications to the software may be needed to ignore the initial default

values of the power indicator control and attention indicator control bits. The

functionality associated with these registers is not affected. Power to the hot plug

capable downstream ports can still be turned on and off normally.

Back to Errata Summary Table

30. Inconsistent Default Value of Power Controller Control Register

if MRL is Not Locked

Risk Category: Low Silicon Revisions Affected: AA, AB, BB

Description

For serial hot plug capable ports, if the MRL is not locked, the value (0 – Power

ON) shown in the power controller control bit [10] of the Slot Control register

(offset 80h) is incorrect. The port(s) is/are actually not powered on (HP_PWREN

is low) which is the correct behavior despite the incorrect default register value.

The port(s) can power ON and OFF normally.

Solution/Workaround

For serial hot plug capable ports, if the MRL is not locked, have the software

ignore the value of the power controller control bit.

Impact

If the MRL is not locked, slight modifications to the software may be needed to

ignore the value of the power controller control bit. The functionality associated

PEX 8648 Errata v1.9

with these registers is not affected. Power to the hot plug capable downstream

ports can still be turned on and off normally.

Back to Errata Summary Table

31. Incorrect ACS P2P Completion Routing

Risk Category: Low Silicon Revisions Affected: AA, AB, BB

Description

If the ACS P2P Completion Redirect bit in the ACS Control and Capability

register is set for a downstream port, completions directed to a peer port from a

peer port without the TLP Relaxed Ordering (RO) bit set should be routed to the

upstream port. However, when the following 2 conditions are met, the Switch

incorrectly routes such completions to the peer port instead:

a) The ACS P2P Egress Control bit is active in the ACS Control and

Capability Register.

b) The Egress Control Vector bit in the ACS Control and Capability register

for the associated egress peer is inactive.

Solution/Workaround

There are two possible workarounds:

1. Do not set the ACS P2P Egress control bit in the ACS Control and

Capability register if the ACS P2P Completion Redirect bit is being used in

the switch.

2. Ensure that the Egress Control Vector in the ACS Control and Capability

register of both the peer ports enable or disable the other port in a

symmetric manner. For example, if Peer Port 1 enables Peer Port 2

Egress Control and Peer Port 2 enables Peer Port 1 in the Egress Control

Vector, it is symmetric. Or, if Peer Port 1 disables Peer Port 2 Egress

Control and Peer Port 2 disables Peer Port 1 in the Egress Control Vector,

it is symmetric.

Impact

When the ACS P2P Completion Redirect bit is set, the ACS Egress Control

Vector may affect the ACS P2P Completion Redirect functionality by causing

completions (as described in the Description) to be routed to the incorrect port.

Back to Errata Summary Table

32. ACS Upstream Forwarding Issue

Risk Category: Low Silicon Revisions Affected: AA, AB, BB

Description

If the ACS Upstream Forwarding bit in the ACS Control and Capability register is

set in the downstream port of the Switch, and a completion is received at the

ingress of the downstream port intended for the egress of the same downstream

port, it should be routed upstream. However, with the Switch, if the above

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Broadcom PEX 8648 Silicon Errata List User guide

Broadcom PEX 8648 Silicon Errata List User guide

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