REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
Evaluation Board for AD9874
FUNCTIONAL BLOCK DIAGRAM
CLKIN
IFIN LO_IN
P1
AD9874
TB1
TB4
TB3
U12
U13
IDT
FIFO
XILINX
FPGA
J6
J3
J1
LO VCO
MODULE INTERFACE
VDIRECT
MIXER OUT
TB2
EPROM
HEADER
IF MATCHING
NETWORK
JP1–9
VREG
JP22
JP23
JP15
JP18
CRYSTAL
OSC.
JP24
JP25
SW2
SW1
LED
FREF
J2 J5
AD9874 REVC
ANALOG
DEVICES
EVAL-AD9874EB
Windows is a registered trademark of Microsoft Corp.
LabVIEW is a trademark of National Instruments.
GENERAL DESCRIPTION
The evaluation board for the AD9874 and its accompanying
software provide a simple means to evaluate this highly inte-
grated IC. The AD9874 is a general-purpose IF subsystem that
digitizes a low level 10 MHz–300 MHz IF input with signal
bandwidths ranging from 6.8 kHz to 270 kHz. The signal chain
within the IC consists of a low noise amplifier, a mixer, a vari-
able gain amplifier, a band-pass - analog-to-digital converter,
and a decimation filter with programmable decimation factor.
Auxiliary blocks include clock and LO synthesizers as well as a
serial peripheral interface (SPI) port.
The functional block diagram shows the major blocks of the evalua-
tion board. The evaluation board is designed to be flexible, allowing
the user to configure it for different potential applications. The
power supply distribution block provides filtered, adjustable volt-
ages to the various supply pins of the AD9874. In the IF input
signal path, component pads are available to implement different
IF impedance matching networks. The LO and CLK signals can
be externally applied or internally derived from a user-supplied
VCO module interface daughter board. The reference for the
on-chip LO and CLK synthesizers can be applied via the external
FREF input or an on-board crystal oscillator.
The evaluation board is designed to interface to a PC via a National
Instruments NI 6533 series digital IO card. A XILINX FPGA
formats the data between the AD9874 and digital I/O board.
Software, developed using National Instruments’ LabVIEW™
and provided as Windows
®
executable programs, is supplied for
the configuration of the SPI port registers and analysis of the
AD9874’s output data. This software provides a convenient
graphical user interface, allowing easy access to the various
SPI port configuration registers along with real-time frequency
and time domain analysis of its output data.
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EVAL-AD9874EB
–2–
SYSTEM REQUIREMENTS
A Pentium
®
90 or greater PC
National Instruments’ NI 6533 Series Digital I/O
(i.e., PCI-DIO-32HS). Note: NI6534 series works with NIDAQ
software version 6.9.2 or greater.
National Instruments’ 64-Lead Shielded (SH68-68-D1) Inter-
face Cable
High Quality RF Signal Generator(s) for the IF Input as well as LO
and CLK Inputs (If the AD9874 LO and CLK Synthesizers Are
Disabled)
VCO Module and Crystal Oscillator (or RF Signal Generator) if
the LO and CLK Synthesizers Are Enabled
Two 5 V Power Supplies (Note, Additional Supply Required to
Power VCO Module)
An AD9874 Evaluation Board with Software
HARDWARE DESCRIPTION
The following section describes the various sections pertaining to
the AD9874 evaluation board. The functional block diagram on the
previous page can be used to determine the location of the par-
ticular section being described. The relevant schematics are listed
next to each section and can be found at the end of this document.
The evaluation board’s schematic, layout documentation, bill of
materials, and software can be found at http://products.analog.com/
products/info.asp?product=AD9874.
SMA Connector Description
There are five SMA connectors on the evaluation board. The
functions of these connectors are outlined in Table I.
Table I. SMA Connector Description
No. Name Description
J1 FREF Reference Frequency Input for LO
and CLK Synthesizer
J2 IFIN IF Input Signal
J3 MIXER OUT Optional Mixer Output Signal
J5 LO_IN Optional LO Input for Mixer
J6 CLKIN Optional CLK Input for ADC
IF Matching Network (See Figure 6a)
The IF input signal path includes component pads such that a
matching network can be implemented to match the AD9874’s LNA
input impedance to a nominal 50 Ω RF signal source. A 0.1 µF
dc blocking capacitor, C83, is included in the signal path since the
AD9874’s LNA input is self-biasing. Table II lists the component
values for several IF frequencies.
Table II. Matching Component Values for Various IFs
IF (MHz) C30 (Ω) C31 (pF) C32 C34
73.35 0 18 220 nH 5 pF
109.65 0 19.5 120 nH 21.5 pF
240 0 5.7 4 pF 39 nH
The evaluation board is shipped with 0 Ω resistors inserted for C30
and C31 and a 57.6 Ω resistor inserted for R51. The addition of R51
(which is in parallel with the AD9874’s input impedance) results in
approximately a 50 Ω load for the external RF source and 8.1 dB
of power loss for frequencies below 100 MHz. Also, since the
IF signal path does not maintain a 50 Ω strip line impedance,
care must be taken when developing a matching network for
other IFs.
LO Input, Synthesizer, and VCO Module (See Figure 6b)
The LO input for the AD9874’s mixer can be supplied by
either an external RF generator via SMA connector J5, or a
user-suppled VCO module. In either case, the LO signal can
be passed on to the AD9874 as a single-ended signal (with
R59 = R60 = Open and R62 = 0 Ω) or a differential signal via
transformer T1 (with R59 = R60 = 0 Ω and R62 = Open).
The user can supply their own VCO module if the AD9874’s
LO synthesizer is to be enabled. The VCO module should be
connected to the AD9874 Evaluation Board via four single row
vertical 0.1 mil header and receptacle pairs (available from
3M, AMPS, Samtec). Use of the receptacle provides a solder-
free connection that simplifies the evaluation of multiple VCO
modules optimized for different LO frequencies. The user
should populate the AD9874 evaluation board’s VCO module
interface with the receptacle and lay out their custom VCO
module with the headers. Note, a solid ground connection is
formed between the user-supplied VCO module and the
AD9874 evaluation board’s ground plane, since almost all of
the receptacle/header pins (excluding the VCO module input
and output) are dedicated ground pins.
The charge pump output current of the AD9874 can be directed
to a resistor network consisting of R34 and R35 or to the
synthesizer’s loop filter via JP15. The former connection can be
used to monitor the charge pump’s performance independently,
while the latter connection is used for normal synthesizer
operation and closed-loop evaluation. Component pads consist-
ing of C44, C66, C67, R36, and R37 are available to implement
the application-specific loop filter.
CLK Input and Synthesizer (See Figure 6b)
The CLK signal for the AD9874 can be supplied via an external
RF generator or derived from a VCO. In the former case, the
external CLK signal is supplied via SMA connector J6 and
ac-coupled (via C41, C42) as a single-ended or differential signal
with R25 serving as a termination resistor. Note, the default
configuration is for an external RF generator that is capacitively
coupled to the AD9874’s CLK input as a single-ended signal.
The AD9874 evaluation board also provides a means to evaluate
the AD9874’s on-chip CLK synthesizer and negative resistance
oscillator. Component pads consisting of C62, C63, R30, and
R31 are used to implement the application specific loop filter
for the synthesizer. Varactor D5 (Toshiba 1SV2228, not included)
in combination with C29, L12, and the AD9874’s internal nega-
tive resistance core form a VCO that can be connected to the
AD9874’s CLK input via R3 and R4. Note, the component pads
for varactor D5 accept SOT 23 packages, allowing other vendor
varactors (i.e., Zetex) to be selected. R52 and C33 provide a
filtered dc biasing point for the VCO circuit. Lastly, the charge
pump output current from the AD9874 can be directed to a
resistor network consisting of R32 and R33 for independent
evaluation or to the CLK synthesizer’s loop filter via JP18.
FREF Input (See Figure 6e)
An external reference frequency for the LO and CLK synthesiz-
ers can be supplied via SMA connector J1 or a crystal oscillator
(“H” package, not included). The SMA input connector is
terminated with a 50 Ω resistor, R5. Selection of the frequency
Pentium is a registered trademark of the Intel Corporation.
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EVAL-AD9874EB
reference source can be made by installing R7 or R8. Note, the
crystal oscillator is locally decoupled and its supply tied to TB3
(VDIRECT).
FPGA, FIFO, and NIDAQ Interface (See Figures 6c and 6d)
The AD9874 evaluation board is designed to interface to a PC via
a National Instruments NI 6533 (or NI6534) series digital IO
(NIDAQ) card. The evaluation software that configures the
AD9874 and analyzes its output data supports this interface. A
XILINX FPGA (U3) and IDT FIFO (U11) are used to format
the AD9874’s serial output data and to control the interface
between the AD9874 and NIDAQ card as shown in Figure 1. The
interface supports normal data output modes of operation in
which decimated 16- or 24-bit I and Q data (along with optional
embedded AGC data) are provided within a frame. It also sup-
ports a mode that provides the undecimated digital output from
the AD9874’s - ADC.
For normal output data modes, the FPGA formats the AD9874’s
serial output (SSI) data within a frame into 16-bit parallel data
for the FIFO and controls the interface timing between the FIFO
and NIDAQ card. Line drivers (U12 and U13) are included to
drive the NIDAQ card via a shielded cable (not included) with
the 16-bit data. In the special interface mode, the FPGA provides
the buffered undecimated output data directly to the NIDAQ
card at the CLK rate.
The FPGA is also used to control the serial port interface (SPI)
between the AD9874 and NIDAQ card. In this case, the FPGA
buffers and conditions the 5 V logic input levels from the NIDAQ
card. It also contains a bidirectional buffer that is used to con-
trol the data flow for SPI WRITE and READ operations. The
FPGA is programmed via a serial EPROM (U4). A green LED
illuminates when the FPGA is configured.
The evaluation board comes installed with a 68-lead male SCS1-11
type cable connector. The user is required to purchase a
SH68-68-D1 shielded interface cable (National Instruments Part
No. 183432-01) and NI 6533 digital I/O card (www.ni.com/pdf/
products/us/2mhw332-333e.pdf).
Interfacing AD9874 Evaluation Board to a DSP (See Figure 6c)
The current AD9874 evaluation board unfortunately does not
provide a simple and clean interface to a DSP evaluation board.
However, only a minor board modification is required to enable
such an interface. The SSI digital output interface is simple
since the AD9874’s output signals are buffered by the FPGA
and made available from header J4. Note, the DGND test point
next to J4 should be used to provide a digital ground return path
between the two evaluation boards. The SPI interface is more
complicated since there is no header provided for the PE, PC,
and PD signals. The solution is to use the PE, PC, and PD test
points located next to the FPGA and lift the corresponding
FPGA pins (Pins 19, 20, and 21 of U3). These FPGA pins
provide buffered output signals and can be disconnected to
prevent bus contention.
Power Supply Interface (See Figure 6e and 6f)
The AD9874 evaluation board contains four power supply
terminal blocks (TB) for external power supply connections.
TB3 allows the user to directly apply power to any individual
6-LEAD HEADER
AD9874
SYNCB
DOUTA
DOUTB
CLKOUT
FS
DOUTB
DOUTA
FROM SW1 ON BOARD
RESET_
FIFO CONTROLLER
(FIFOCNT.V)
NATIONAL INSTRUMENTS' NIDAQ CARD
DOUTA_BUFF
DOUTA
DOUTB_BUFF
DOUTB
DOUT_BUFF
DOUT
CLKOUT_BUFF
FS_BUFF
FIFO WRITE CLK GENERATOR
(WR_CLK.V)
DW
DR48
SPI
CONFIGURATION
DECODER
(MODE.V)
SSI
SERIAL-TO-PARALLEL
CONVERTER
(DOUTS 2P.V)
TEST_MODE
SCAN_MODE
DC
LEVEL
SHIFTER
R_W_BIT
SPT
SERIAL-TO-PARALLEL
CONVERTER
(SPI.V)
PE
PC
PD
SPI_ADDR
6
SPI_DATA
8
R_W_BIT
J4
MRSCTR_
PD_OUT_3V
PD_IN_5V
PE_5V
FIFO
LINE
DRIVERS
16
FIFO_DATA
FIFO_DATA
16
WR_CLK
FF_
REN_
WEN_
16
FIFO_DATA_BUFF
DOUT
TEST
FIFO_WR_EN
PC_5V
XILINX FPGA
Figure 1. Block Diagram of XILINX FPGA and FIFO Used to Control Interface between AD9874 and NIDAQ Card
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EVAL-AD9874EB
–4–
GND
+5.0
POWER SUPPLY
CLKIN
IFIN LO_IN
P1
AD9874
TB1
TB4
TB3
U12
U13
IDT
FIFO
XILINX
FPGA
J6
J3
J1
LO VCO
MODULE INTERFACE
VDIRECT
MIXER OUT
TB2
EPROM
HEADER
IF MATCHING
NETWORK
JP1-9
VREG
JP22
JP23
JP15
JP18
CRYSTAL
OSC.
JP24
JP25
SW2
SW1
LED
FREF
J2 J5
71.10MHz –5dBm
OUTPUT
73.35MHz –40dBm
OUTPUT
18.00MHz –5dBm
OUTPUT
PHASE-LOCK GENERATORS
GETTING STARTED PRINTED CIRCUIT BOARD SETUP GUIDE
1) PHASE LOCK THREE SIGNAL GENERATORS AS FOLLOWS:
GEN 1: 71.1MHz @ –5dBm
GEN 2: 73.3MHz @ –40dBm
GEN 3: 18.0MHz @ –5dBm
2) CONNECT GENERATORS TO PCB AS SHOWN.
3) CONNECT ONE POWER SUPPLY TO TB4 AND ONE SUPPLY TO TB1.
BOTH POWER SUPPLIES SHOULD BE SET AT 5.00 VDC.
NOTE: THE GNDs OF THE TWO POWER SUPPLIES
CAN BE TIED TOGETHER AT THE SUPPLIES
OR ON THE BOARD AT JP24 OR JP25.
TO NATIONAL INSTRUMENTS’
6533 CARD
GND
+5.0
POWER
SUPPLY
AD9874 REVC
ANALOG
DEVICES
Figure 2. Typical AD9874 Evaluation Board Setup with the LO and CLK Synthesizers Disabled
or group of AD9874 supply pins by proper configuration of
jumpers JP1–JP9. This is useful for automated testing in which
various supply voltages may be swept. Also, the individual supply
currents can be monitored at these jumpers.
TB4 allows the user to apply an unregulated 5 V supply to five
voltage regulators that provide regulated supplies to the AD9874
by proper configuration of JP1–JP9. The voltage of these regulators
can be controlled over a 2.2 V to 3.8 V range via a potentiometer.
TB1 provides an unregulated 5 V supply for the digital ICs,
while TB2 provides a user-defined supply level for the LO VCO
module (if installed).
Evaluation Board Setup Example
Figure 2 shows an example of a lab setup used to evaluate the
AD9874. In this example, three RF generators are used to drive
the IFIN, LO_IN, and CLKIN SMA connectors, since both the
LO and CLK synthesizers of the AD9874 are disabled. All of
the RF generators are phase locked to minimize the phase noise
contribution and enable coherent sampling. Note, only a single
RF generator would be required to supply the IFIN signal if the
LO and CLK synthesizers were enabled with the necessary
external components installed (i.e., crystal oscillator, PLL loop
filter, VCO module, and so on).
Two 5 V supplies are connected to TB4 and TB1 with JP24 (or
J25) installed to connect the grounds of the supplies together.
Individual supplies to the AD9874 can be varied via the potenti-
ometers. A shielded interface cable (National Instruments Part
No. 183432-01) is used to connect the evaluation board to the
NI 6533 digital I/O card.
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EVAL-AD9874EB
SOFTWARE DESCRIPTION
Software Installation
The AD9874’s evaluation board software and PCB board docu-
mentation comes on a CD-ROM titled, AD9874 Evaluation Board
Software/Documentation. The contents of the CD are as follows
and are placed in their associated folders:
•
Readme File (Readme.txt)
•
Eval Board Connectivity PDF File (interconnect_pcb.pdf)
•
Layout PDF File (ad9874cpcb.pdf)
•
Schematic PDF File (ad9874csch.pdf)
•
LabVIEW Eval_ File (ad9874_eval.exe ver. 5.1.1)
•
LabVIEW Eval_ Library File (ad9874_eval.llb ver. 5.1.1)
•
Installer Setup File for LabVIEW Run-Time Engine
(Setup.exe ver. 5.1.1)
The user has two options available in the installation and opera-
tion of the software. Before loading the software, the user should
verify that the NI 6533 DIO card and associated software has been
installed on to their PC. Option 1 is for users who currently
have LabVIEW version 5.1.1 loaded on their computer, while
Option 2 is for those who do not. Please select the appropriate
option and follow the recommended guidelines below.
Option1: Running the VIs from the library files (.llb) in LabVIEW:
a. Launch the LabVIEW application
b. Choose File, Open, and select the ad9874_eval.llb file in
the Option1 subdirectory
c. From the File dialog box, choose the
ad9874_Eval_SW_090402. vi and click OK
Note, Analog Devices does not support modifications to any of
the VIs contained in the ad9874_eval library.
Option 2: Loading the run-time engine and running executable
files (.exe)
a. From Windows desktop environment, select START, run,
then browse to your cd drive, and execute the Setup.exe file
found in <cd drive letter>:Option2\Installer\disks directory.
Follow the instructions to load the run-time engine on
your computer.
b. From Windows desktop environment, select Start, run, then
browse to your cd drive and look for the ad9874_eval.exe files.
c. Hit Open to launch program.
Control Panel Description
Upon launching the AD9874_eval application, the control panel
shown in Figure 3 should appear. This panel is used to:
•
Configure and read back the various AD9874 SPI registers
•
Initiate a self-tuning macro for the AD9874’s ADC
•
Set the National Instruments data acquisition device’s
number
•
Access the demodulated complex I/Q signal or the ADC’s
undecimated data display windows.
The SPI registers are listed by their address and grouped accord-
ing to their function within the AD9874. When applicable, the
various control bits associated with some SPI register addresses
are expanded to further simplify programming of the IC. Lastly,
a Help button is available for each SPI register, providing a
more detailed description of its function.
Figure 3. Control Panel for Programming and Tuning the AD9874 Prior to Observing Output Data
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The bottom right corner of the control panel (next to the ADI
logo) contains several buttons that are used to invoke various
actions as described below in descending order. Positioning the
pointer over the particular button followed by a left mouse click
invokes a particular action.
Run Self-Tuning Macro—Clicking this button initiates a series
of commands detailed in the HELP menu that automatically
tunes the AD9874’s - ADC. Note, tuning is required upon
powering the AD9874 once the CLK frequency has stabilized.
Tuning is also required if the CLK frequency is varied.
National Instruments Data Acquisition Device Number—
One should ensure that the number entered in the box corre-
sponds to the number used when installing the NIDAQ NI 6533
card software.
Observe Digitized, Complex Output Signal—Once the
AD9874’s SPI registers have been properly configured (and its
- ADC tuned), clicking this button will open another display
showing the complex I/Q output data in both the time and fre-
quency domain.
Observe Undecimated Modulator Output—Once the
AD9874’s SPI registers have been properly configured (and its
- ADC tuned), clicking this button opens another display in
which the spectrum of the undecimated - ADC can be observed.
Write—Clicking this button causes all of the AD9874 SPI
registers to be updated with the values programmed on the screen.
Note, an automatic readback of the SPI registers occurs after
the write command and the results are shown on the bottom of
the control panel display.
Reset—Clicking this button “resets” the AD9874 to its default
values as described in Table I of the AD9874 data sheet. Note,
the default values will also appear on the bottom of the control
panel display.
Done—Clicking this button closes the AD9874_eval application.
Read—Clicking this button reads back the contents of the
AD9874’s SPI registers and displays the values to the left of the
button.
Digitized, Complex Output Signal Display Description
Figure 4 shows the display that will appear after clicking on the
Observe Digitized, Complex Output Signal button. The displays
show the Complex FFT of the I and Q data (normalized to its
output data rate) as well as a time domain representation of the
I/Q waveform and its constellation. The AD9874’s attenuation
setting, signal strength, and reset fields can also be observed
graphically by changing the Embedded AGC Data_I/Q Constel-
lation switch to the appropriate position (assuming the AD9874’s
SSI is configured properly). Note, upon entering this display,
the control panel is rendered inactive while the display window
remains active.
The horizontal and vertical axes of the displays can be modified
by the following procedure: position cursor over the min (or max)
axis setting, left click mouse, and type in new axis setting. Indi-
vidual SPI registers can be updated by entering the designated
register number and value in the boxes located in the display’s
bottom left corner followed by a left click on the WRITE button.
The current status of the SPI registers can be observed in the
lower portion of the display window.
FFT WINDOW, BW AND # OF AVERAGESPRINT PANEL RETURN TO CONTROL DISPLAY
I/Q DATA DISPLAY
CONSTELLATION
DISPLAY
SELECT AGC DATA
OR AGC CONSTELLATION
SIGNAL
POWER
IN-BAND
NOISE POWER
SINGLE REGISTER SPI WRITE SPI REGISTER CONTENT
COMPLEX FFT
Figure 4. Complex Output Signal Display with I/Q Constellation
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EVAL-AD9874EB
Parameters associated with the Complex FFT display can be
modified by the user. They are highlighted in yellow across the
top portion of the display window and include CLK rate, FFT
Window type, BW, and FFT averages. BW sets the measurement
bandwidth for which the following parameters are calculated:
signal power, in-band noise power, SNR, SFDR, and NBW.
The Complex FFT display highlights the signal power in red,
the in-band noise power in blue, and the out-of-band region in
black. Note, the signal power, SNR, and SFDR results are only
applicable for unmodulated carriers located in FFT bins. The
power of modulated carriers can be measured using the in-band
noise power (blue) with the BW parameter set appropriately.
The display window also has the ability to data log the SPI register
settings, the raw I/Q data, and the performance parameters. A
left click over the appropriate Save button will prompt the user
to specify a file name and location for the new data file. The data
is saved into this file with a time stamp for further evaluation.
Lastly, the display window can be printed to a file (or printer) using
the PRINT PANEL button located in the upper left-hand corner.
Figure 5. Complex Output Signal Display with I/Q Constellation
Undecimated Modular Display Description
Figure 5 shows the display that will appear after clicking on the
Observe Undecimated Modulator Output Signal button of the
control panel. The displays show the FFT of the AD9874’s
- ADC’s undecimated output data. The clock rate and FFT
window type can be specified in the top right corner of the window.
Note, the FFT display provides a clear demonstration of the
noise-shaping inherent in the band-pass - ADC’s output
spectrum. Also, the peak signal level reported in the top right
corner of the FFT display is useful in observing the amount of
out-of-band rejection to signals falling outside its pass band
prior to any digital filtering.
This display also provides the quantized output levels with the
ability to write the data to a file. Single SPI register write capa-
bilities are also included with the most current SPI register
settings displayed on the lower portion of the window. A
PRINT PANEL button is also provided on the display.
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EVAL-AD9874EB
–8–
R21
50⍀
AB
1
2
3
JP23
VDDA
VDDF
TP21
PC
PD
TP22
C98
VA L
C32
VA L
C34
VA L
R51
VA L
C83
0.1F
CLKN
CLKP
VDDC
IOUTC
VDDQ
VDDD
VDDH
FREF
IOUTL
VDDP
VDDL
LON
LOP
VDDI
SYNCB
FS
DOUTB
DOUTA
11
12
14
6
17
9
13
24
23
1
2
15
5
4
21
16
3
22
18
10
7
8
19
20
39
40
48
27
26
33
25
43
42
38
47
34
37
36
45
32
31
35
30
29
41
44
46
28
CLKOUT
U1
DUT-AD9874
CLKN
CLKP
GCN
GCP
GNDA
GNDC
GNDD
GNDF
GNDQ
GNDS
IF2N
IF2P
IOUTC
MXON
MXOP
PC
PD
RREF
VDDA-ADC
VDDC_CK_SYNTH
VDDF
VDDQ_CK_PUMP
VREFN
VREFP
CLKOUT
CXIF
CXVL
CXVM
DOUTA
DOUTB
FREF
FS
GNDH
GNDI
GNDL
GNDP
GNDT
IFIN
IOUTL
LON
LOP
PE
SYNCB
VDDD_DIGITAL_1
VDDH-DIG.INTERFACE
VDDL-LO
VDDP-LO_PUMP_SUPPLY
VDDI-LNA/MIXER
TP18
VDDH
PE
R23
10k⍀
R43
DNP
VDDH
1
2
3
4
SW2
AGND; 5
TP15
TP16
TP17
TP19
C16
DNP
C26
100nF
C27
1nF
C28
100nF
J2
IF IN
C30
VA L
C31
VA L
C99
VA L
C36
DNP
L1
10UH
NOTE: THESE 5 DEVICES ARE NOT DEFINED (CAPS OR INDUCTORS)
C24
10nF
C60
DNP
+
TP23
TP24
C25
100pF
C23
100pF
R18
100k⍀
C21
DNP
VCM
TP25
R47
0⍀
C15
2.2nF
TP2 TP1
TP11
TP10
C78
100pF
C77
100pF
MXOP
MXON
C43
DNP
C22
180pF
L2
10UH
AB
1
2
3
JP22
R1
50⍀
VDDI
T2
6
S
5
4
P
1
2
3
ADT1-1WT
R2
50⍀
C38
0.1F
VDDI
J3
MIXER OUTPUT
ADC IN
C37
DNP
Figure 6a. AD9874 Interface
AGND ; 3, 4, 5
T3
6
S
J6
CLKIN
5
4
P
1
2
3
ADT1-6T
1
2
C62
VA L
C63
VA L
R30
VA L
R31
VA L
A
B
1
2
3
JP18
R33
549⍀
R32
549⍀
TP3
IOUTC
VREGPQ
3
2
3
D5
1SV228
1
D5
1SV228
C29
VA L
C33
VA L
L12
100UH
R3
0⍀
R4
0⍀
CLKP
CLKN
C41
0.01F
C42
0.01F
MATCH LENGTH
VOLTAG E CO NTROLLED OSCILLATOR
R58
0⍀
R25
100⍀
R26
0⍀
R57
0⍀
R27
0⍀
CLKIN
R52
0⍀
VDDC
CLOCK SYNTHESIZER INTERFACE
AGND ; 3, 4, 5
LOIN
T1
4
S
J5
5
6
P
3
2
1
ADT1-1WT
1
2
M1
VCOMODULE
35
36
37
38
39
40
41
42
43
44
1
2
3
4
5
6
7
8
9
10
11
12
22
21
20
19
18
17
16
15
14
13
34
33
32
31
30
29
28
27
26
25
24
23
VCOVDD
VIN
CLKOUT
VDD
R62
0⍀
R60
0⍀
R61
200⍀
MATCH LENGTH
R59
0⍀
C65
0.1F
C64
0.1F
R63
0⍀
R50
VA L
LON
R48
VA L
LOP
R49
VA L
VDDI
C44
VA L
C66
VA L
C67
VA L
R36
VA L
R37
VA L
HIGH IMPEDANCE
A
B
1
2
3
JP15
R35
549⍀
R34
549⍀
TP4
IOUTL
VREGPQ
LO SYNTHESIZER INTERFACE
Figure 6b. CLK and LO Ext. Input/Synthesizer Interface
REV. 0
–9–
EVAL-AD9874EB
INIT
3_3V
U4
XC17S100XL
4
36
5
7
8
2
1
D2
GRN
CLK
DATA
GND
VCC1
VCC2
CE
OE/RESET
DIN
CCLK
DONE
C54
0.1F
C24
330⍀
DAT6
DAT0
DAT1
DAT2
DAT3
DAT4
2_50V
DAT8
DAT10
DAT11
DAT13
DAT14
DAT15
_WEN
_MRS
108
88
107
73
81
86
96
106
104
74
80
89
97
105
87
90
102
93
100
103
91
92
94
95
98
99
101
77
84
75
76
78
79
82
83
85
M2
WR_CLK
DAT12
DAT9
DAT7
DAT5
B4IO-VREF1
B4IO-4
VCCINT4
B4IO-6
B4IO-7
B4IO-8
B4IO-9
B4IO-3
B4IO-VREF2
B5IO-2
B5IO-4
GND6
B5IO-6
B5IO-VREF2
VCCINT3
GCK1
B5IO-1
B5IO-3
B5IO-7
B5IO-VREF1
VCCO-B5B4
B4IO-1
PWDN
VCCINT2
GND7
B4IO-5
B4IO-10
STATUS
M2
B5IO-5
B4IO-2
GND8
GND9
VCCO-B5
GCK0
VCCO-B6
3_3V
_FF
_PAF
_HF
_PAE
_EF
_REN
127
144
125
142
111
109
110
119
128
135
143
132
139
129
130
131
133
134
136
137
138
140
141
115
122
126
113
114
116
117
118
120
121
123
112
124
3_3V
2_50V
M2
3_3V
R45
10k⍀
J4
6
5
4
3
2
1
TMS
B6IO-1
B6IO-10
B6IO-2
B6IO-3
B6IO-4
B6IO-5
B6IO-6
B6IO-7
B6IO-8
B6IO-9
B6IO-TRDY
B6IO-VREF1
B6IO-VREF2
B7IO-1
B7IO-2
B7IO-3
B7IO-4
B7IO-5
B7IO-6
B7IO-7
B7IO-8
B7IO-9
B7IO-IRDY
B7IO-VREF1
B7IO-VREF2
GND1
GND2
GND3
GND4
GND5
M0
M1
TMS
VCCINT1
VCCO-B7
VCCO-B7B6
TESTMON
SPARE
DOUTA_BUFF
DOUT_BUFF
CLKOUT_BUFF
FS_BUFF
DOUTB_BUFF
U3
XC2S100
R40
0⍀
PD_IN_5V
PE_5V
PD_OUT_3V
_REQ
_RESET
PC_5V
FS
SYNCB
TDO
TCK
DONE
DOUT
U3
XC2S100
55
72
53
70
39
37
38
47
56
63
71
60
67
57
58
59
61
62
64
65
66
68
69
43
50
54
41
42
44
45
46
48
49
51
40
52
36
16
35
1
9
14
24
34
32
2
8
17
25
33
15
18
30
21
28
31
19
20
22
23
26
27
29
5
12
3
4
6
7
10
11
13
PD
PE
3_3V
DOUTA
DOUTB
2_50V
2_50V
PC
3_3V
INIT
CLKOUT
TDI
CCLK
DIN
_MRSCTR
B0IO-1
B0IO-2
B0IO-3
B0IO-4
B0IO-5
B0IO-6
B0IO-7
B0IO-VREF1
B0IO-VREF2
B1IO-1
B1IO-2
B1IO-3
B1IO-4
B1IO-5
B1IO-6
B1IO-7
B1IO-CS
B1IO-VREF1
B1IO-VREF2
B1IO-WRITE
GCK2
GCK3
GND13
GND14
GND15
GND16
TCK
TDI
TDO
VCCINT6
VCCINT7
VCCINT8
VCCO-B0
VCCO-B1
VCCO-B1B0
VCCO-B2
GND11
B2IO-5
B2IO-IRDY
B2IO-D3
B2IO-VREF1
B2IO-D2
GND12
B2IO-D1
B2IO-4
B2IO-VREF2
B3IO-TRDY
B2IO-1
B2IO-3
PROGRAM
B3IO-INT
B3IO-1
B3IO-VREF1
B3IO-2
B3IO-D6
GND10
B3IO-4
B3IO-VREF2
B3IO-D4
B3IO-D7
B3IO-D5
VCCO-B4
B3IO-3
B3IO-5
B2IO-2
D2IO-DOUT-BUSY
CCLK
B2IO-DIN-D0
VCCO-B3
VCCO-B3B2
DONE
VCCINT5
3_3V
TCK
TDO
TDI
TMS
J7
6
5
4
3
2
1
VCC
GND
TCK
TDO
TDI
TMS
JTAGCONN
36
37 72
1
144 109
108
73
XILINX
XC2S100
SPARTAN II
TQFP144
1
2
3
4
SW1
DGND; 5
RESET
3_3V
R54
10k⍀
C97
0.1F
C55
0.1F
C85
0.1F
C84
0.1F
C68
0.1F
2_50V
U3 DECOUPLING
C61
0.1F
C59
0.1F
C58
0.1F
C56
0.1F
2_50V
U3 DECOUPLING
C50
0.1F
C51
0.1F
C52
0.1F
C53
0.1F
3_3V
U3 DECOUPLING
C45
0.1F
C47
0.1F
C48
0.1F
C49
0.1F
3_3
U3 DECOUPLING
Figure 6c. FPGA
REV. 0
EVAL-AD9874EB
–10–
C92
0.1F
C82
0.1F
C81
0.1F
C79
0.1F
5V
B8
B9
B10
B11
B12
B13
B14
B15
_MRSCTR
B14
B9
B8
B7
B4
B3
_FF
B15
B0
RCLK
PC_5V
_REQ
PD_OUT_3V
PE_5V
B12
B11
B10
B5
B2
B1
B6
B13
PD_IN_5V
P1
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
TP29
NIDAQ
68P CONNECTOR
TP5
TP28
TP14
TP26
B3DAT3
RP4
22
18
DAT2
DAT1
DAT0
B2
B1
B0
RP4
22
27
RP4
22
36
RP4
22
45
C96
0.1F
C95
0.1F
C94
0.1F
C93
0.1F
_REN
_WEN
_PAE
_HF
DAT15
DAT14
DAT13
DAT12
DAT11
DAT10
DAT9
DAT8
DAT7
DAT6
DAT5
DAT4
DAT3
DAT2
DAT1
DAT0
_PAF
B0
B1
B2
B3
B4
B5
B6
B7
U13
74F541
2
3
4
5
6
7
8
9
1
10 11
12
13
14
15
16
17
18
20
19
5V
A1
A2
A3
A4
A5
A6
A7
A8
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
VCC
G1
G2
VEE
5V
R53
1k⍀
5V
RCLK
WR_CLK
_FF
_EF
_MRS
U11
IDT72255LA
59
46
4
30
43
50
49
55
39
33
27
24
5
60
52
48
47
45
44
42
41
40
38
37
36
35
34
32
31
29
28
26
2557
56
54
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
53
58
1
51
64
62
3
63
61
2
SEN
LD
PRS
FS_DC
MRS
WCLK
REN
WEN
FF
EF
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PAE
HF
PAF
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17
RCLK
FWFT
GND1
GND2
GND3
GND4
GND5
VCC1
OE
RT
VCC2
VCC3
VCC4
GND6
GND7
B7DAT7
RP3
22
18
DAT6
DAT5
DAT4
B6
B5
B4
RP3
22
27
RP3
22
36
RP3
22
45
B11DAT11
RP2
22
18
DAT10
DAT9
DAT8
B10
B9
B8
RP2
22
27
RP2
22
36
RP2
22
45
B15DAT15
RP1
22
18
DAT14
DAT13
DAT12
B14
B13
B12
RP1
22
27
RP1
22
36
RP1
22
45
U12
74F541
2
3
4
5
6
7
8
9
1
10 11
12
13
14
15
16
17
18
20
19
5V
A1
A2
A3
A4
A5
A6
A7
A8
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
VCC
G1
G2
VEE
TP32
TP30 TP31
TP33
Figure 6d. FIFO, Line Drivers, and NIDAQ Connector
REV. 0
–11–
EVAL-AD9874EB
C90
10F
16V
2_50V
5V
TPS76325DBVT
VR1
34
51
2
GND
VIN
VOUT
NC
EN
C91
10F
16V
+
C87
0.1F
+
C89
10F
16V
3_3V
5V
TPS76333DBVT
VR2
34
51
2
GND
VIN
VOUT
NC
EN
C88
10F
16V
+
C86
0.1F
+
AGND
D6
5V
VCOVDD
DGND
C80
10F
16V
5V
TP34
EXTERNAL POWER SUPPLY INPUTS
TB1
1
TB1
2
TB2
1
TB2
2
TP12
+
C57
10F
16V
+
TP7
TP35 TP36
TB4
1
TB3
1
TB3
2
TB4
2
D3
5V
C75
10F
16V
+
F1
80MA
F2
80MA
D4
12V
C76
10F
16V
+
VDIRECT
VREGULATED
TP13
DOUTB
DOUTA
5V
DOUT
R22
DNP
U5
8
6
4
1
7
2
3
5
AD8561
LA
+V
–V
GND
NC
R40
DNP
R42
DNP
R41
DNP
R69
1k⍀
R39
5k⍀
C46
0.1F
FREF_IN
AGND; 3 , 4, 5
J1
FREF
VDIRECT
2
1
U10
NUMBER
NC = 2, 3, 6, 7
5
8
4
1
TP20
NC
GND
VCC
OUT
C35
0.1F
C39
0.1F
R6
0⍀
R5
0⍀
R7
0⍀
R8
0⍀
C40
DNP
JP25
JP24
Figure 6e. Power Supply and FREF Inputs
REV. 0
–12–
C03201–0–10/02(0)
PRINTED IN U.S.A.
EVAL-AD9874EB
VREGULATED
U2
ADP3303A
NC = 1, 2, 3, 14, 13, 12
9
6
5
4
8
7
11
10
IN1
IN2
GND
OUT1
OUT2
FB
SD
ERR
C1
1F
R14
91k⍀
C6
100pF
JP10
JP11
R9
50k⍀
CW
R15
65k⍀
VREGI
C3
1F
U6
ADP3303A
NC = 1, 2, 3, 14, 13, 12
9
6
5
4
8
7
11
10
IN1
IN2
GND
OUT1
OUT2
FB
SD
ERR
C12
1F
R17
91k⍀
C7
100pF
JP12
JP13
R10
50k⍀
CW
R16
65k⍀
VREGPQ
C10
1F
U7
ADP3303A
NC = 1, 2, 3, 14, 13, 12
9
6
5
4
8
7
11
10
IN1
IN2
GND
OUT1
OUT2
FB
SD
ERR
C20
1F
R20
91k⍀
C13
100pF
JP14
JP16
R11
50k⍀
CW
R19
65k⍀
VREGFA
C17
1F
U8
ADP3303A
NC = 1, 2, 3, 14, 13, 12
9
6
5
4
8
7
11
10
IN1
IN2
GND
OUT1
OUT2
FB
SD
ERR
C71
1F
R29
91k⍀
C69
100pF
JP17
JP19
R12
50k⍀
CW
R28
65k⍀
VREGHD
C70
1F
U9
ADP3303A
NC = 1, 2, 3, 14, 13, 12
9
6
5
4
8
7
11
10
IN1
IN2
GND
OUT1
OUT2
FB
SD
ERR
C74
1F
R44
91k⍀
C72
100pF
JP20
JP21
R13
50k⍀
CW
R38
65k⍀
VREGCL
C73
1F
VDDL
VDDC
L6
VA L
C11
0.1F
C5
0.1F
L5
VA L
AB
1
2
3
JP6
AB
1
2
3
JP8
AB
1
2
3
JP3
L8
VA L
VDDH
C18
0.1F
AB
1
2
3
JP4
L7
VA L
VDDD
C9
0.1F
DUT BYPASS FILTERS
VDDA
VDDF
L3
VA L
C2
0.1F
C4
0.1F
L4
VA L
AB
1
2
3
JP5
AB
1
2
3
JP7
AB
1
2
3
JP1
L10
VA L
VDDP
C19
0.1F
AB
1
2
3
JP2
L9
VA L
VDDQ
C14
0.1F
VDIRECT
AB
1
2
3
JP9
L11
VA L
VDDI
C8
0.1F
Figure 6f. AD9874 Power Supply Interface/Filtering
/
