PCI 9054 Rev. AB
PCI 9054AB
Errata Rev. 2.2
May 2005
Errata Documentation
A. Affected Silicon Revision
This document details errata in the following silicon:
Product Part Number Description Production
PCI 9054AB PCI 9054-AB50PI Released 176-pin PQFP Product August 1999
PCI 9054AB PCI 9054-AB50BI Released 225-pin PBGA Product August 1999
B. Documentation Revision
The following documentation is the baseline functional description of the silicon.
Errata are defined as behaviors in the affected silicon that do not match
behaviors detailed in this documentation.
Document Revision Description Date
PCI 9054 Data Book 2.1 Data Book January 2000
PCI 9054 Design
Notes Documentation
See www.plxtech.com
for latest revision
Design Notes
Documentation
C. Errata Documentation Revision History
Revision Date Description
1.3 Sept. 1999 Errata #1 to #8.
1.5 Sept. 2000 Errata #1 to #14.
1.6 April 2001 Added Errata #15 to #20.
1.7 July 2001 Added Errata #21.
1.8 March 2002 Added Errata #22 to #23.
1.9 May 2002 Added Errata #24.
2.0 July 2003 Added Errata #25.
2.1 August 2003 Added Errata #26.
2.2 May 2005 Added Errata #27 to #29.
D. Errata Summary:
Document number: 9054AB-SIL-ER-P0-2.2
-1-
# Description
1 LOCK# Negation During an Idle Phase (Retracted)
2 Unaligned DMA Transfers with EOT# Asserted on the Last Data
3
DMA Channel 0 Almost Full Threshold Value of Zero on Local-to-PCI
Transfers
4 PCI Target Abort During DMA Transfer
5
M-Mode Direct Master Burst Read May Cause Improper RETRY#
Assertion if Burst is Preempted
6 Vital Product Data (VPD) Transfer Status Flag Update
7 Simultaneous Write to Queue Register in Messaging Unit
8 M-Mode DMA Local-to-PCI Burst Transaction with DMA FIFO Full
9 Power Management State Change From D3hot To D0
10 DMA PCI-to-Local Transfer with MWI Feature Enabled
11
Backoff (BREQo) or RETRY# Assertion for PCI Initiator Read
Transactions
12 Direct Master Read with PCI Initiator Cache Enabled
13 PCI Device ID Value
14 M-Mode Burst Inhibit (BI#) Input Qualification
15
DMA Fails when the DMA Channel Abort Bit (DMACSRx[2]) is Set from
the PCI Bus
16
BREQo Asserts Without LHOLD after a Direct Master Read is Backed-
Off, if WAIT# Input and READY# Output are Asserted Together
17
Cannot Perform a New Read or Write After Backoff – Must Resume with
Last Address
18 M-Mode TEA# Pin/Signal Can Be Asserted Improperly
19 Local Bus Upper Byte Lane Parity Checking
20
PCI 9054AB Asserts ENUM# Twice During Hot Swap Insertion, Causing
Driver to be Loaded Twice
21 Local Parity Error Status Bit and Interrupt Assertion
22 C/J-Mode DMA Burst-4 Mode with Constant Address
23 J-Mode DMA with Constant Address for 8- or 16-bit Local Buses
24 DMA Scatter-Gather Descriptor IRDY# PCI Protocol Violation
25
PQFP Package M-Mode LA[0:5], C-Mode LA[31:26], and J-mode
LA[28:26], ALE, DEN# and DT/R# Signal Noise
26
C/J-mode Local Bus is not released if BREQi (Bus Request) input is
asserted during a DMA transfer
27 PME# Pin Isolation
28
USERi/DACK0#/LLOCKi# pin is incorrectly driven high during TEST
input assertion (i.e., NANDTREE testing)
29 Direct Slave Disconnect Without Data
E. Errata Details:
Document number: 9054AB-SIL-ER-P0-2.2
-2-
1. LOCK# Negation During an Idle Phase (Retracted)
The previously published erratum has been determined to not be an issue in the
PCI 9054AB, and therefore this erratum is retracted.
2. Unaligned DMA Transfers with EOT# Asserted on the Last
Data
Erratum Issue: During a Local-to-PCI DMA transfer with unaligned addresses, if
EOT# is asserted either on the last data phase in Fast Terminate mode
(DMAMODEx[15] = 1), or on the next-to-last data phase in Slow Terminate mode
(DMAMODEx[15] = 0), a partial transfer of the last data into the DMA Channel
FIFO will occur. That partial transfer data will remain in the FIFO and will not be
transferred to the PCI bus. On the following Local-to-PCI DMA transfer, the
remaining data that should have been flushed from the internal FIFO will be the
first data transferred on the PCI Bus.
Solutions/Workarounds (use any):
1. If a local bus processor is available:
a. If Demand mode DMA is used (DMAMODE0[12] = 1), instead of
aborting DMA with EOT#, first pause the DMA operation by de-
asserting DREQ0# and then abort the DMA by having the local
processor set the DMA Abort bit (DMACSR0[2] = 1) with the DMA
Start bit (DMACSR0[1]) remaining set (DMACSR0[2:0] = 6). Note
that after DREQ# is de-asserted, one or two Local Bus data transfers
will move data into the DMA Channel 0 FIFO. This is not an issue
because asserting Channel Abort throws away all data in the FIFO.
b. Instead of aborting the DMA with EOT#, the local processor can first
pause the DMA operation by clearing the Channel Enable bit
(DMACSRx[0] = 0), and then abort the DMA operation by setting the
DMA Abort bit (DMACSRx[2] = 1) with the DMA Start bit
(DMACSR0[1]) remaining set (DMACSR0[2:0] = 6).
2. In the case where infinite transfers are not being used, since the user
knows the transfer count, EOT# should not be asserted on the last data
phase of the DMA transfer in Fast Terminate mode, nor on the next-to-last
data phase in Slow Terminate mode.
3. Use only aligned DMA addresses.
Document number: 9054AB-SIL-ER-P0-2.2
-3-
3. DMA Channel 0 Almost Full Threshold Value of Zero on
Local-to-PCI Transfers
Erratum Issue: During a DMA channel 0 Local-to-PCI transfer, the PCI 9054
uses the Almost Full Threshold register (DMATHR[11:8]) to determine when the
PCI 9054 should request the PCI bus to send out the data in its FIFO. If the
threshold is set to 0 and if only 1 word (or less) of data is in the FIFO, it will be
left there and not be sent out to the PCI bus. This can only happen when
Demand mode is used to transfer only 1 word to the PCI side at a time. If this 1
word is the last word of a DMA transfer, the thresholds will be ignored and the
data will still go through. This problem does not apply to DMA Channel 1.
Solutions / Workarounds:
1. Do not use Demand mode DMA channel 0 to transfer a single word at a
time. Use standard block mode or chaining DMA with a byte count of four
to effect the transfers instead.
2. Set the Almost Full Threshold to a non-zero value.
3. Assert EOT# to force out to the PCI side any data stuck in the FIFO. Note
that this will effectively abort the current DMA channel 0 cycle.
4. PCI Target Abort During DMA Transfer
This issue was previously published as an erratum. However, it has since been
determined to be compliant with the PCI Specification, and therefore this erratum
is retracted. The text for this issue is now re-published as PCI 9054 Design Notes
#13.
Document number: 9054AB-SIL-ER-P0-2.2
-4-
5. M-Mode Direct Master Burst Read May Cause Improper
RETRY# Assertion if Burst is Preempted
Erratum Issue: If the Backoff Timer is enabled (EROMBA[4] =1), and Deferred
Reads is disabled (LMISC[4]) = 0), and the PCI 9054 PCI Latency Timer expires
which allows the Direct Slave transfer to be started (Direct Slave is now
pending), and the Direct Master Read FIFO goes empty (because Direct Master
can’t get the PCI bus due to the Direct Slave transfer), the Local Bus RETRY#
output signal will be incorrectly asserted on a non-quadword aligned address
when the Backoff Timer expires.
Solutions/Workarounds (use any):
1. Enable Deferred Reads (LMISC[4]) = 1).
2. Set the PCI Latency Timer (PCILTR) to its maximum value (FFh); this will
allow the MPC 860 to complete its burst before the PCI 9054 needs to
release the PCI bus.
3. Set the PCI Target Retry Delay Clocks (LBRD0[31:28]) (which applies to
all Direct Slave accesses) to a value less than the Backoff Timer
(EROMBA[5,3:0]). This gives Direct Master higher priority over Direct
Slave accesses.
6. Vital Product Data (VPD) Transfer Status Flag Update
Erratum Issue: To perform a VPD write, data is written to the PVPDATA
register, followed by a write of the VPD address with bit 31, the VPD Flag
(PVPDAD[15]) set, after which the bit clears when the write completes. For a
VPD read, the address is written with bit 31, the VPD Flag (PVPDAD[15]) clear,
after which the Flag is set when the read completes. However, during VPD
Write/Read transfers the status completion Flag (PVPDAD [15]) intermittently
fails to update. The system may hang waiting for transaction completion if the
Flag is not set to the appropriate value after the transaction. This problem does
not affect reads of the EEPROM during PCI 9054 initialization.
Solutions/Workarounds (use any):
1. If the Flag bit is not set within 500 µsec after the VPD transaction is
started, the executed transaction needs to be restarted, to guarantee
successful completion of the VPD transaction.
2. Use CNTRL[27:24] bits rather than VPD to access the Serial EEPROM.
Document number: 9054AB-SIL-ER-P0-2.2
-5-
7. Simultaneous Write to Queue Register in Messaging Unit
Erratum Issue: The PCI 9054 updates one of four queue pointers automatically
each time there is a Read or Write to the messaging unit Inbound (Port 40h) or
Outbound (Port 44h) ports. The four registers are the inbound free tail pointer
(IFTPR), the inbound post head pointer (IPHPR), the outbound free head pointer
(OFHPR), and outbound post tail pointer (OPTPR). If a local master initiates a
write to the PCI 9054 messaging unit queue registers simultaneous to a PCI
access to the Inbound or Outbound ports, the PCI 9054 will fail to automatically
increment the appropriate pointers to reflect this. This can result in overwriting a
previous message or retrieving a previously read message from the queue.
These pointers cannot be ‘corrected’ due to the fact that the PCI 9054 cannot
determine if an increment failure has occurred. The failure only occurs when the
PCI 9054 returns READY# to the local master simultaneous with the PCI 9054
returning TRDY# to the PCI master on an Inbound or Outbound port access that
has been retried.
This erratum does not affect the I
2
O protocol. It only affects custom messaging
unit implementations.
Solutions/Workarounds (use any):
1. Disable the PCI r2.1 Features Enable bit by clearing MARBR[24]. With this
bit clear, the PCI Target Retry Delay Clocks register bits (LBRD0[31:28])
should be set to a value of 3h or greater.
2. For Multiple Initiator Implementations:
a. Implement a semaphore in an on-chip mailbox or any shared memory
region, so that the local master can access the messaging unit queue
registers only when the PCI master is not accessing them.
b. Update the interfering queue registers only from the PCI side, via
messages passed through the PCI 9054 internal mailbox registers.
For Single Initiator Implementations:
Implement a single request/reply message protocol for custom message
passing. This is recommended for applications where there is a single
host and the host waits for a reply before initiating a new request.
Document number: 9054AB-SIL-ER-P0-2.2
-6-
8. M-Mode DMA Local-to-PCI Burst Transaction with DMA FIFO
Full
Erratum Issue: The PCI 9054 may issue corrupted data on a Local-to-PCI DMA
data transfer when the rate of exchange between local writes and PCI reads
within the FIFO are such that they cause the FIFO to fill completely. This will only
happen when the Bterm bit is disabled and the Burst bit is enabled. The PCI
9054 will occasionally miss the DMA FIFO almost full flag, and consequently it
will overwrite current data in the DMA FIFO, thereby causing corrupted data.
Solutions/Workarounds:
1. Set the Local Latency Timer register (MARBR[7:0]) to a value that ensures
that the local side never bursts more than 26 Long Words, to keep the
DMA FIFO not full. Additionally, in the DMA Threshold register
(DMATHR), the Local-to-PCI Almost Empty field (CxLPAE) needs to be
set to Fh. This will force the DMA FIFO to go empty before the DMA
controller requests more reads from the local target. To increase data
throughput, the Local-to-PCI Almost Empty field (CxLPAE) could be set to
a smaller value, Eh or Dh, and the Local Latency Timer value
(MARBR[7:0]) would need to be lowered accordingly. The formula to
calculate values for the DMA Channel 0 Local-to-PCI Almost Empty
(C0LPAE) field (DMATHR[7:4]), and for the Local Latency Timer
(MARBR[7:0]), is C0LPAE / 2 – 1 + LLT = 24 Lwords (or C0LPAE / 2 +
LLT = 25 Lwords). The formula to calculate values for the DMA Channel 1
Local-to-PCI Almost Empty (C1LPAE) field (DMA[23:20]), and for the
Local Latency Timer (MARBR[7:0]), is: C1LPAE / 2 – 1 + LLT = 8 Lwords
(or C1LPAE / 2 + LLT = 9 Lwords). The Local Latency Timer has a 6-
LCLK latency before it kicks in.
2. Enable the Bterm bit (LBRDx[7]) to enable continuous bursting. Requires
an external memory controller.
3. Disable DMA burst capability.
9. Power Management State Change From D
3hot
To D
0
Erratum Issue: The PCI 9054 will fail to re-load EEPROM values into the Local
Configuration registers when the Power Management state changes from D
3hot
to
the D
0
state, causing all Local Configuration registers to be reset to default
values.
Solution/Workaround:
Anytime the PCI 9054 completes a Power Management state change from
D
3hot
to the D
0
state, the Reload Configuration Registers bit (CNTRL[29])
needs to be set prior to BIOS accessing the PCI 9054.
Document number: 9054AB-SIL-ER-P0-2.2
-7-
10. DMA PCI-to-Local Transfer with MWI Feature Enabled
Erratum Issue: The PCI 9054 will perform an illegal PCI Read transaction with a
PCI Command of ‘F’ on a PCI-to-Local DMA transaction when the MWI feature is
enabled (DMAMODEx[13] = 1).
Solutions/Workarounds (use any):
1. Disable the MWI bit (DMAMODEx[13]) for all PCI-to-Local DMA transfers.
2. For all PCI-to-Local DMA transfers, set the transfer count to be 1 Lword
less than the PCI Cache Line Size.
3. Set the PCI Cache Line Size register to a value larger than the data
packet size (in Lwords), prior to starting the PCI-to-Local DMA transfer.
11. Backoff (BREQo) or RETRY# Assertion for PCI Initiator
Read Transactions
Erratum Issue: The PCI 9054 will fail to issue the BREQo/RETRY# signal in a
busy PCI environment for the following condition:
C/J mode: If a PCI Initiator Write Data (DMW) is posted in the Direct Master
Write FIFO, and a PCI Initiator Read (DMR) transaction is executed to the PCI
9054 while a PCI Target Read (DSR) transaction is pending in the PCI 9054, with
Backoff Request enabled (EROMBA[4]=1). The PCI 9054 will issue wait states
by not asserting the READY# signal, and will not assert the BREQo signal to a
local bus processor for a deadlock solution, until the PCI 9054 gets a TRDY#
signal to complete the posted Direct Master Write transaction.
M mode: If a PCI Initiator Write Data (DMW) is posted in the DM Write FIFO, and
a PCI Initiator Read (DMR) transaction is executed to the PCI 9054 with the PCI
Initiator Deferred Read bit enabled (LMISC[4] = 1). The PCI 9054 will not issue a
RETRY# signal to a local bus processor to terminate the PCI Initiator Deferred
Read transaction until the PCI 9054 gets a TRDY# signal to complete the posted
Direct Master Write transaction.
Solution/Workaround 1:
This workaround applies to all of modes of the PCI 9054 and can be used
when the Target will always accept the last data in the transfer (doesn’t leave
the last data word of the transfer in the output holding register). The DMPAF
signal or DMPAF bit (MARBR [30]) can be used to monitor the Direct Master
Write FIFO status. The DMPAF status is programmable (DMPBAM [10, 8:5])
for the amount of Lwords to be in the FIFO before declaring it full. If DMPBAM
[10, 8:5] = 00000b then whenever the Direct Master Write FIFO has at least 1
Lword in it, the FIFO will be considered full (DMPAF =1) and no PCI Initiator
Read transaction should be performed.
Document number: 9054AB-SIL-ER-P0-2.2
-8-
Solution/Workaround 2:
This workaround applies to all of modes of the PCI 9054 and needs to be
used because a Target on the PCI bus will not always accept the last data in
a Direct Master write transfer. This workaround can be used if another PCI
Target on the bus can always accept at least one data transfer (which means
it won't leave the last data word of the transfer in the output holding register)
from a Direct Master Write before disconnecting.
The DMPAF signal or DMPAF bit (MARBR [30]) can be used to monitor the
Direct Master Write FIFO status. The DMPAF status is programmable
(DMPBAM [10, 8:5]) for the amount of Lwords to be in the FIFO before
declaring it full. If DMPBAM [10, 8:5] = 00000b, then whenever the Direct
Master Write FIFO has at least 1 Lword in it, the FIFO will be considered full
(DMPAF =1) and no PCI Initiator Read transaction should be performed. In
order to ensure that all Direct Master Write transfers are completed before
starting a Direct Master read, the last Direct Master Write transfer needs to be
directed to a PCI device that will always accept at least one data transfer. For
example: if another PCI 9054 is on the PCI bus, the Local Master could do a
"dummy" write (Direct Master Write) to its Mailbox register (or another
acceptable register). Because this is a register write, it won't be retried, and
will be completed once PCI bus ownership has been granted. You will know
that the write has been completed and that it is acceptable to start a Direct
Master Read if the DMPAF signal is false (=0).
Solution/Workaround 3:
This workaround applies to all of modes of the PCI 9054 and can be used if
access to the PCI arbiter is available. The DMPAF signal or DMPAF bit
(MARBR [30]) is used to monitor the Direct Master Write FIFO status. The
DMPAF status is programmable (DMPBAM [10, 8:5]) for the amount of
Lwords to be in the FIFO before declaring it full. If DMPBAM [10, 8:5] =
00000b then whenever the Direct Master Write FIFO has at least 1 Lword in
it, the FIFO will be considered full (DMPAF =1). Additionally the transfer
status needs to be ORed with DMPAF to create a signal that will inform the
system that the PCI 9054 hasn't completed its Direct Master task yet - let's
call it DMIP (Direct Master In Process). Since DMIP is in the Local clock
domain, the PCI REQ# signal needs to be synchronized to the Local clock,
before ORing it with DMPAF to create a signal that holds off other Direct
Master transfers until the pending transfer completes. Because REQ# will go
away for two clocks if MARBR[23] = 0 when a PCI transfer is retried, logic
needs detect it being gone for at least 3 clocks and the DMPAF signal being
false before allowing other Direct Master transfers to execute.
Document number: 9054AB-SIL-ER-P0-2.2
-9-
12. Direct Master Read with PCI Initiator Cache Enabled
Erratum Issue: PCI 9054 PCI Initiator (Direct Master) reads with PCI Initiator
Cache enabled (DMPBAM[2] = 1) will result in 32-bit data reads intermittently
returning incorrect data. The incorrect data returned will be the Lword value at
the 32-bit aligned address that immediately precedes the correct value. In other
words, data that has been previously cached and read out of the PCI Initiator
Read FIFO will be repeated on a subsequent read. This erratum occurs in all
three local bus modes (C, J, and M).
Solution/Workaround:
Disable PCI Initiator Cache by clearing the PCI Initiator Cache Enable bit
(DMPBAM[2] = 0).
13. PCI Device ID Value
Erratum Issue: If the PCI 9054 registers are initialized from EEPROM and the
PCI Device ID value is less than 0010h, the Initialization Done bit (LMISC[2]) will
be set before EEPROM initialization is complete. Consequently PCI BIOS will be
allowed access to the PCI 9054 before the chip is ready.
Solutions/Workarounds (use either):
1. Use a Device ID value that is not less than 0010h, for EEPROM loading.
2. Use a local bus processor to initialize the PCI 9054 registers. In such case
the local processor must set the Initialization Done bit (LMISC[2]) when
initialization is complete.
14. M-Mode Burst Inhibit (BI#) Input Qualification
Erratum Issue: When the PCI 9054 in M-mode, a local bus master such as the
MPC 860, and another local bus device all share the local bus BI# signal, if a
burst to any local bus device other than the PCI 9054 is inhibited by the local bus
master asserting the Burst Inhibit (BI#) signal, and then a local bus master
attempts a Direct Master burst to the PCI 9054, the PCI 9054 will hang the local
bus.
Solution/Workaround:
Connect a three-state buffer as follows:
Document number: 9054AB-SIL-ER-P0-2.2
-10-
1. Connect the local bus master’s (MPC 860) BI# I/O signal to the buffer
input.
2. Connect the buffer output to the PCI 9054 BI# input pin.
3. Connect one of the MPC 860’s programmable chip selects to the buffer
control pin.
4. Program the MPC 860’s corresponding chip select register such that it will
enable the three-state buffer only when accessing the PCI 9054.
If the local bus master does not have an available chip select, an equivalent
solution should be implemented.
15. DMA Fails when the DMA Channel Abort Bit (DMACSRx[2])
is Set from the PCI Bus
Erratum Issue: Writing to either DMA abort bit (DMACSRx[2]) from the PCI bus
can intermittently put that DMA channel into an undefined state. When in an
undefined state, the DMA channel does not respond, and DMA transactions on
that channel are no longer possible without resetting the PCI 9054. The
remaining DMA channel, as well as Direct Slave and Direct Master operations,
are not affected by a hung DMA channel.
Solutions/Workarounds (use either):
1. If a Local Bus processor is present, that processor can write to the Abort
bit in the DMACSRx register to abort the current DMA transfer. When the
PCI side needs to abort the DMA transfer, it may signal a local interrupt to
the local processor by writing to the PCI-to-Local Doorbell register
(P2LDBELL). The local processor must be programmed to respond to the
interrupt, abort the current DMA transfer by setting the Abort bit, and clear
the Doorbell interrupt.
2. The DMA transfer can be terminated by using the EOT# input. EOT# is
enabled by setting DMAMODEx[14]. EOT# will terminate an active DMA
transfer, but not a DMA that has been paused. If the DMA transfer is to be
aborted but the channel is currently paused, perform a dummy DMA
transfer of at least two data so that a DMA transfer will be in progress. The
PCI 9054 will abort the current DMA transfer when EOT# is asserted. Use
aligned addresses for the DMA transfer to avoid Errata #2.
Document number: 9054AB-SIL-ER-P0-2.2
-11-
16. BREQo Asserts Without LHOLD after a Direct Master Read
is Backed-Off, if WAIT# Input and READY# Output are
Asserted Together
Erratum Issue: If the PCI 9054 is configured for C or J mode, and the BREQo
signal is enabled (EROMBA[4] = 1) to back off a Direct Master transaction, the
PCI 9054 will incorrectly assert BREQo without LHOLD if the WAIT# input and
READY# output are asserted together while the Direct Master transfer is in
progress. WAIT# input and READY# output only need to be asserted together for
one rising local clock edge during the Direct Master transfer to cause the BREQo
without LHOLD. BREQo will be asserted without LHOLD two clocks after the
local master asserts ADS# to continue the backed-off transaction.
A workaround to this problem is only necessary if the WAIT# input is asserted
during a Direct Master transfer.
Solution/Workaround:
Stop the PCI 9054 Local Clock when WAIT# input is asserted. Disconnect the
PCI 9054 WAIT# pin and allow its pull-up to keep the signal in the inactive
state. When the WAIT# output from the local master is detected, freeze the
PCI 9054 local clock in the low state before the next rising edge, and hold the
clock in the low state until the local master negates WAIT#.
17. Cannot Perform a New Read or Write After Backoff – Must
Resume with Last Address
Erratum Issue: The PCI 9054 Data Book version 2.1 pages 3-16 and 5-14
states: “A new…read is performed if the resumed Local Bus cycle is not the
same as the Backed Off cycle”.
When the PCI 9054 BREQo/RETRY# signal is enabled (EROMBA[4] = 1) to back
off a Direct Master transaction (to resolve a potential deadlock), if the local
master does not resume a backed-off transfer with the originally backed-off
address, the PCI 9054 will incorrectly assert BREQo/RETRY# without asserting
LHOLD. If the local master does not apply the correct continuation address,
BREQo/RETRY# will be asserted without LHOLD two clocks after the local
master asserts ADS#.
Solution/Workaround:
Only resume a backed-off transfer with the continuation address, that is, the
Master must resume the backed-off transfer with the address that it was
backed-off from. Note: when using a TI DSP, make sure it is programmed to
correctly resume the read or write from the backed-off address.
Document number: 9054AB-SIL-ER-P0-2.2
-12-
18. M-Mode TEA# Pin/Signal Can Be Asserted Improperly
General functional description of proper TEA# assertion
TEA#, Transfer Error Acknowledge, is a wired-OR M-mode bus signal that is
asserted by a Slave device on the Local Bus. The MPC 860 can assert TEA# as
a Master or Slave if its Bus Monitor times out (if programmed to do so). TEA# is
only to be asserted by a local bus device during a transfer in which it is
participating. If the Bus Monitor does time out and the MPC 860 asserts TEA#,
the device it is communicating with needs to detect this regardless of its
configuration (Master or Slave) and get off the Local bus in one clock cycle.
Additionally the device should terminate any active PCI bus activity via an abort
and set its status bits/registers appropriately.
A. The following register bits directly affect the functionality of the TEA#
signal/pin:
INTCSR[0] Enables any PCI Abort condition or Local Parity error to assert
TEA#.
INTCSR[1] Enables internal PCI bus parity error signal to assert TEA#.
INTCSR[6] Enables the assertion of TEA# if a Local Bus parity error is
detected.
INTCSR[7] This bit is set upon detection of a Local Bus parity error. TEA#
asserts if enabled.
PCICR[6] Enables generation of a internal PCI bus parity error signal that can
assert TEA#.
PCISR[12] This bit is set upon the detection of a Target Abort. TEA# asserts if
enabled.
PCISR[13] This bit is set upon the detection of a Master Abort. TEA# asserts if
enabled.
PCISR[15] When set PCI bus parity error causes TEA# assertion if enabled.
QSR[6] Enables the assertion of TEA# when QSR[7] interrupt is set.
QSR[7] If Outbound Free Queue overflows this bit is set. TEA# asserts if
enabled.
Other register bits that are functionally affected by the TEA# signal/pin:
LMISC[5] Enables a TEA# assertion to generate a SERR# on the PCI bus.
Document number: 9054AB-SIL-ER-P0-2.2
-13-
B. Summary of conditions that correctly cause the PCI 9054AB to generate
a TEA#
• Received Target Abort (PCISR[12]) - As a Master the PCI 9054AB sets this
bit whenever its transaction is terminated with a Target Abort. The PCI
9054AB will assert TEA# after this bit is set. This condition can happen during
any Direct Master or DMA transfer or when 256 Retries have occurred in a
Direct Master or DMA transaction.
• Received Master Abort (PCISR[13]) - As a Master the PCI 9054AB sets this
bit whenever it terminates its transaction with a Master Abort. The PCI
9054AB will assert TEA# after this bit is set. This condition can happen during
any Direct Master or DMA transfer or when a Target fails to assert DEVSEL#.
• PCI Bus Parity Error (PCISR[15]) - If a PCI Parity error is detected,
PCISR[15] is set and TEA# is asserted.
• Local Bus Parity Error (INTCSR[6]) - Detection of a Local bus Data Parity
Error in a DMA, Direct Master Write or Direct Slave Read transfer will
generate an assertion of TEA# after the error is detected.
• Messaging Outbound Free queue overflows (QSR[7]) - When the
Outbound Free Queue overflows this bit is set and the PCI 9054AB will assert
TEA#.
C. Errata description - Improper TEA# assertion
The PCI 9054AB will improperly assert the TEA# signal/pin when it is not
currently participating in a transfer on the local bus under the following
circumstances:
• A posted Direct Master Write encounters one of the TEA# assertion
conditions once it obtains the PCI bus and starts the write transfer.
• A Direct Master Read encounters one of the TEA# assertion conditions after it
obtains the PCI bus and the cycle has been retried (if the Deferred Read
Enable bit (LMISC[4]) is set). Or if LMISC[4]) is clear and a PCI parity error is
encountered after the local transfer has completed (PCI data is still being pre-
fetched).
• A DMA encounters one of the TEA# assertion conditions after it obtains the
PCI bus.
In these cases TEA# may coincide with another Direct Master Write, Retried
Direct Master Read or DMA and therefore be seen as proper.
Document number: 9054AB-SIL-ER-P0-2.2
-14-
D. Local Bus conditions when TEA# may assert improperly, and the
results:
• If the Bus is idle - the MPC 860 will miss the assertion of TEA#.
• If the MPC 860 is communicating with another Target device – the other
Target will appear to have asserted TEA#.
• If the MPC 860 is asserting TS# when the PCI 9054AB is asserts TEA# - the
MPC 860 will generate a machine check. But it will corrupt the first instruction
fetch & hang.
• If the PCI 9054AB is processing a Direct Slave transaction on the Local Bus
when TEA# is improperly asserted by the PCI 9054AB - the Direct Slave
transactions will treat it as a TA#, which will confuse the MPC 860.
Solution/Workaround 1:
Turn deferred reads off (LMISC[4]) = 0) and allow a TEA# assertion to
generate a SERR# on the PCI bus (LMISC1[5] =1). Confirm functionality of
PCI addresses with Direct Master Read(s) before posting a Direct Master
Write or starting a DMA transfer to those addresses.
Solution/Workaround 2:
Do not connect the PCI 9054AB TEA# to the MPC 860, or disable all
sources of TEA# (see register bits above). Use LINT# with external logic
that monitors the bus to generate a TEA# at the appropriate time.
E. Critical Issue – PCI 9054AB behavior to a TEA# assertion
The MPC 860 can (if programmed to do so) assert TEA# as a Master or Slave if
its Bus Monitor times out.
• If TEA# is asserted by the MPC 860 while the PCI 9054AB is the local bus
master, TEA# will preempt TA# input and terminate the current cycle. If the
burst isn’t completed, the PCI 9054AB will generate a new TS# and continue.
This applies for Direct Slave and DMA transfers.
• If TEA# is asserted by the MPC 860 while the PCI 9054AB is the local bus
slave, the PCI 9054AB ignores TEA#.
Solution/Workaround 1:
Disable or program the MPC 860 Bus Monitor to a value high enough so
that it exceeds the amount of time necessary to get the bus and execute the
transfer.
Document number: 9054AB-SIL-ER-P0-2.2
-15-
Solution/Workaround 2:
Have the MPC 860 assert the LINT# pin instead of TEA# when the Bus
Monitor times out. That will cause the PCI INTA# interrupt pin to assert so
that the system can issue a software reset to the local section, by setting
the PCI 9054AB CNTRL register bit [30] to 1, and then clearing it after the
reset is completed.
A. The PCI 9054 Data Book version 2.1 clarifications and corrections:
♦ Section 3.4.1.9 on page 3-7: PCISR bits [11] & [12] swapped. Replace
“Target Abort bit (PCISR[13, 11]=0” to Received Target Abort bit (PCISR[13,
12]=0.
♦ Section 3.4.1.9 on page 3-7: this section says “It can then clear the Target
Abort bit (PCISR[11]) to clear the TEA# interrupt and re-enable PCI initiator
transfers”. It should say, “It can then clear the Master or Received Target
Abort bit (PCISR[13:12]) to clear the TEA# interrupt and re-enable PCI
initiator transfers.”
♦ Section 6.1.4 on page 6-2: replace all “Target Abort” references with
“Received Target Abort”, and replace all “PCISR[13, 11]=1” references with
“PCISR[13, 12]=1”.
♦ Section 6.1.12 on page 6-4: the first says “PCI Bus Target Abort bit is set
(PCISR[11]=1)”; it should state “PCI Bus Received Target Abort bit is set
(PCISR[12]=1)”.
♦ Section 6.1.12 on page 6-4: the second from last says “TEA# is a level
output that remains asserted as long as the Abort or Parity Error Status bits
are set.” This statement is incorrect. When asserted, TEA# is always a one
clock pulse wide signal.
♦ Section 6.1.12 on page 6-4: the last paragraph says “The PCI 9054 tolerates
TEA# input assertion only during PCI Target or DMA transactions. The PCI
9054 does not sample TEA# assertion during PCI initiator transactions.” The
Data Book should say, “The PCI 9054 samples TEA# input assertion only
during a Direct Slave or DMA transaction. When the PCI 9054 sees a TEA# it
will produce a new TS# if the burst is not yet completed. The PCI 9054 does
not sample TEA# assertion during Direct Master transactions.”
Document number: 9054AB-SIL-ER-P0-2.2
-16-
19. Local Bus Upper Byte Lane Parity Checking
Erratum Issue: This erratum applies to Local Bus designs that require parity
checking. When Local Bus parity checking is enabled, the PCI 9054 only checks
for parity errors on the least significant byte lane (the PCI 9054 checks only DP0
in C/J mode, and only DP3 in M-mode). Bad parity on the other Local Bus byte
lanes will not be detected. This is an issue during Local Bus writes to the PCI
9054 configuration registers, Direct Master writes, Direct Slave reads, and DMA
from the Local Bus to the PCI bus.
Solution/Workaround:
There is no recommended solution or workaround for this erratum in the PCI
9054AB.
20. PCI 9054AB Asserts ENUM# Twice During Hot Swap
Insertion, Causing Driver to be Loaded Twice
Erratum Issue: The PCI 9054AB can assert ENUM# twice during Hot Swap
insertion, if the switch gets latched after PCI RST# has been negated. This may
cause the driver to be loaded twice. This problem only occurs in the PCI 9054AB
version of the silicon.
Solutions/Workarounds (use either):
1. Prolong PCI RST# assertion so that the switch can be closed prior to
RST# negation.
2. Modify software to not load the driver if the same board is detected as
already inserted.
21. Local Parity Error Status Bit and Interrupt Assertion
Erratum Issue: Parity is checked for Direct Slave Reads, Direct Master Write
and DMA Local Bus Reads. If a parity error is detected, the PCI 9054 will set a
status bit, then assert an interrupt (LSERR# C/J-modes, TEA# M-mode) in the
clock cycle following that data being checked. However, the data Parity Error
status bit will never be set and the interrupt will not be asserted unless the
READY# signal for C/J-modes or TA# for M-mode is enabled and asserted low.
This will only apply when the READY#/TA# signal is disabled in the PCI 9054
register bit(s) for address spaces as indicated below:
• LBRDx[6] for Local Address Spaces 0 and 1
• LBRD0[22] for Expansion ROM space
• DMAMODEx[6] for DMA channels 0 and 1
Document number: 9054AB-SIL-ER-P0-2.2
-17-
Solution/Workaround:
If local parity is to be used for Direct Slave Reads or DMA Local Bus Reads,
and the READY# signal (C/J-modes) or TA# signal (M-mode) is not used for
these transfers, then the READY# enable bit (LBRDx[6], LBRD0[22], and/or
DMAMODEx[6]) should be enabled and the READY#/TA# line pulled low.
22. C/J-Mode DMA Burst-4 Mode with Constant Address
Erratum Issue: This erratum applies to PCI 9054 C/J-modes and not to M-mode.
When the PCI 9054 performs a DMA cycle in Burst-4 mode (Burst enabled and
BTERM# disabled, DMAMODEx[8:7] = 10b) with a Constant Address
(DMAMODEx[11] = 1), if the Local starting address is xCh, the PCI 9054
performs single cycles (ADS# & BLAST# are asserted for each data) rather than
a burst. However if the starting address is x0h (or x4h, x8h) the PCI 9054
performs a continuous burst cycle, even though BTERM# is disabled.
Solution/Workaround:
If Constant Address DMA is required use either continuous burst mode (both
Burst and Bterm mode bits enabled, DMAMODEx[8:7] = 11b) or non-burst
(DMAMODEx[8] = 0) modes, or M-mode, rather than C/J-mode Burst-4 mode.
If M-mode is to be used refer to Errata #8.
23. J-Mode DMA with Constant Address for 8- or 16-bit Local
Buses
Erratum Issue: This erratum applies to PCI 9054 J-mode and not to C- or M-
modes. For DMA the Local Addressing Mode register bit can be set to enable
Constant Address on the LA[28:2] and multiplexed LAD[31:0] address buses
(DMAMODEx[11] = 1), or this bit can be cleared (default) to cause the local
address to increment during DMA. In J-mode, during the address phase,
LAD[1:0]# are valid address bits and these bits toggle to match the LBE[1:0]#
state, regardless of whether Constant Address is enabled. Thus with an 8- or 16-
bit Local bus the LAD[1:0] address is not held constant.
Solution/Workaround:
For 8- or 16-bit data widths decode the address to an Lword boundary using
only the upper address lines (address phase LAD[31:2], or LA[28:2]) to select
the appropriate port.
Document number: 9054AB-SIL-ER-P0-2.2
-18-
24. DMA Scatter-Gather Descriptor IRDY# PCI Protocol
Violation
Erratum issue: If the PCI 9054 receives a PCI Target Abort when reading a
Scatter-Gather DMA descriptor from the PCI bus, the PCI 9054 will immediately
float the IRDY# signal, rather than drive the IRDY# signal from active (level 0) to
inactive (level 1) for 1 PCI clock period before floating, as is required by the PCI
Specification for STS I/O buffer protocol. As a result, it may take several PCI
clocks for the IRDY# signal to reach a TTL logic level high.
Solution/Workaround:
No fix is required, and no failures have been observed. The PCI Specification
also requires that IDRY# have a pull-up resistor on the motherboard. If the
above condition is encountered, adding an external pull-up (in parallel with
motherboard pull-up) will decrease the resistance to allow the signal to reach
a TTL logic high more quickly.
25. PQFP Package M-Mode LA[0:5], C-Mode LA[31:26], and
J-mode LA[28:26], ALE, DEN# and DT/R# Signal Noise
Note. This erratum only pertains to the PQFP packaged PCI 9054AB part
(PLX part number PCI 9054-AB50PI). It does not pertain to the PBGA
packaged part (PLX part number PCI 9054-AB50BI).
Erratum Issue: For the PCI 9054-AB50PI, noise may be injected on the Local
Bus causing incorrect values to be output on address bits LA[0:5] (M-mode), or
LA[31:26] (C-mode), or LA[28:26], ALE, DEN# and DT/R# (J-mode) if the
following occur simultaneously:
1. The PCI 9054-AB50PI is driving the PCI bus with patterns that maximize
the number of simultaneously switching outputs on AD[31:0], and
2. The PCI 9054-AB50PI is driving a Local Bus address during Direct Slave
or DMA data transfers.
The Local bus signals affected (LA[0:5] (M-mode), or LA[31:26] (C-mode), or
LA[28:26], ALE, DEN# and DT/R# (J-mode)) that should be logic 0’s might be
incorrectly driven to up to 0.8V for as long as 5 nsec. The amplitude of the noise
is proportional to the loading and signal amplitude/charge on the PCI AD[5:0]
signals when these are driven low by the PCI 9054. Additionally, only Local Bus
devices that detect a logic one near the bottom of the switching range are
affected.
Document number: 9054AB-SIL-ER-P0-2.2
-19-
Solutions/Workarounds (do one of the following):
1. Do not use the PCI 9054-AB50PI LA[0:5] (M-mode), or LA[31:26] (C-
mode), or LA[28:26], ALE, DEN# and DT/R# (J-mode) signals in designs
that perform Direct Slave or DMA data transfers. For M- or C-Mode this
will limit PCI 9054-AB50PI designs to the lower 64 Mbytes of Local Bus
address space. For J-Mode, the optional LA bus will also be limited to the
lower 64 Mbytes of address space. However, in J-Mode all 32-bits of the
Local address are available on the LAD[31:0] signal pins during the
address phase. For a J-Mode address strobe use ADS# instead of ALE or
use a device with a V
IH that is high enough to ignore these pulses.
Typically, DEN# and DT/R# are used with bus transceivers like the
74ACT16646, which will not experience this issue because its minimum
V
IH is 2.0V.
2. Use the PCI 9054-AB50BI, PCI 9054-AC50BI, or PCI 9056BA66BI parts
instead which do not have this issue.
26. C/J-mode Local Bus is not released if BREQi (Bus Request)
input is asserted during a DMA transfer
Erratum Issue: The PCI 9054 fails to release the Local Bus during an ongoing
DMA transfer (on either Channel) when BREQi input is asserted.
Solutions/Workarounds (use either):
1. If hardware control is needed to suspend a DMA transfer to allow another
Local Bus Master access or to allow the other DMA Channel a turn, use
Channel 0 in Demand Mode and de-assert the DREQ# pin to suspend the
DMA transfer and cause the PCI 9054 to release the local bus.
2. Program and Enable the Local Bus Latency timer MARBR[7:0,16] such
that the Local Bus will be released and another Local Bus Master or DMA
channel will be allowed to gain access to the Local Bus.
27. PME# Pin Isolation
Erratum issue: Add-in card components that support PCI Power Management
and implement PME# must ensure that, whenever power is removed, the non-
powered PME# output does not present a low impedance path to ground.
Otherwise, there could be an accidental system wake up event.
The silicon does not ensure such protection and does present a low impedance
path to ground when in the D3cold state, essentially causing an accidental wake
up event every time the add-in card is inserted.
Document number: 9054AB-SIL-ER-P0-2.2
-20-
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