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NXP i.MX 8M Plus – Arm® Cortex®-A53, Machine Learning, Vision, Multimedia and Industrial IoT Reference guide

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i.MX 8M Plus Applications Processor
Reference Manual
Document Number: IMX8MPRM
Rev. 0, 04/2021
i.MX 8M Plus Applications Processor Reference Manual, Rev. 0, 04/2021
2 NXP Semiconductors
Contents
Section number Title Page
Chapter 1
Introduction
1.1 Product Overview ........................................................................................................................................................ 13
1.2 Target Applications.......................................................................................................................................................13
1.3 Acronyms and Abbreviations....................................................................................................................................... 14
1.4 Architectural Overview.................................................................................................................................................16
Chapter 2
Memory Map
2.1 Memory system overview.............................................................................................................................................27
2.2 Cortex-A53 Memory Map ........................................................................................................................................... 28
2.3 Cortex-M7 Memory Map..............................................................................................................................................30
2.4 DMA memory maps..................................................................................................................................................... 33
2.5 AIPS Memory Maps..................................................................................................................................................... 34
2.6 DAP Memory Map....................................................................................................................................................... 40
2.7 Audio Processor Memory Map.....................................................................................................................................42
2.8 HDMI_TX Subsystem Memory Map........................................................................................................................... 42
Chapter 3
System Security
3.1 Overview.......................................................................................................................................................................45
3.2 Central Security Unit (CSU).........................................................................................................................................45
3.3 Cryptographic Acceleration and Assurance Module (CAAM).................................................................................... 45
3.4 Secure Non-Volatile Storage (SNVS).......................................................................................................................... 46
3.5 On-Chip OTP Controller (OCOTP_CTRL)..................................................................................................................46
3.6 Resource Domain Controller (RDC)............................................................................................................................ 46
3.7 TrustZone......................................................................................................................................................................47
Chapter 4
Resource Domain Controller (RDC)
4.1 Overview.......................................................................................................................................................................49
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Section number Title Page
4.2 Functional Description .................................................................................................................................................51
4.3 External Signals............................................................................................................................................................ 58
4.4 Programming Interface................................................................................................................................................. 58
4.5 RDC Memory Map/Register Definition....................................................................................................................... 64
4.6 RDC SEMA42 Memory Map/Register Definition....................................................................................................... 86
Chapter 5
Arm Cortex A53 Platform (A53) Placeholder
Chapter 6
Arm Cortex M7 Platform (CM7)
6.1 Overview.......................................................................................................................................................................97
6.2 Functional Description..................................................................................................................................................99
Chapter 7
Messaging Unit (MU) Placeholder
Chapter 8
Semaphore (SEMA4)
8.1 Overview.......................................................................................................................................................................103
8.2 Functional Description..................................................................................................................................................105
8.3 External Signal Description.......................................................................................................................................... 110
8.4 Initialization Information..............................................................................................................................................110
8.5 Application Information................................................................................................................................................110
8.6 Memory map and register definition.............................................................................................................................112
Chapter 9
On-Chip RAM Memory Controller (OCRAM)
9.1 Overview.......................................................................................................................................................................123
9.2 Functional Description..................................................................................................................................................124
9.3 Programmable Registers............................................................................................................................................... 125
Chapter 10
Network Interconnect Bus System (NIC) Placeholder
Chapter 11
AHB to IP Bridge (AIPSTZ)
11.1 Overview.......................................................................................................................................................................129
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Section number Title Page
11.2 Clocks........................................................................................................................................................................... 130
11.3 Functional Description..................................................................................................................................................130
11.4 Access Protections........................................................................................................................................................ 131
11.5 Access Support..............................................................................................................................................................131
11.6 Initialization Information..............................................................................................................................................132
11.7 Off-Platform Peripherals Index.....................................................................................................................................134
11.8 AIPSTZ Memory Map/Register Definition..................................................................................................................135
Chapter 12
Shared Peripheral Bus Arbiter (SPBA) Placeholder
Chapter 13
TrustZone Address Space Controller (TZASC) Placeholder
Chapter 14
System Debug
14.1 Debug............................................................................................................................................................................157
Chapter 15
System JTAG Controller (SJC) Placeholder
Chapter 16
System Counter (SYS_CTR) Placeholder
Chapter 17
Clock Control Module (CCM) Placeholder
Chapter 18
General Power Controller (GPC)
18.1 Overview.......................................................................................................................................................................169
18.2 Features.........................................................................................................................................................................169
18.3 Block Diagram..............................................................................................................................................................170
18.4 Functional Description..................................................................................................................................................171
18.5 Power Gating Controller (PGC) Overview...................................................................................................................175
18.6 Power control for A53 Platform................................................................................................................................... 180
18.7 Power control for the M7 Platform...............................................................................................................................184
18.8 Domain control for PGCs............................................................................................................................................. 184
18.9 Example Code...............................................................................................................................................................185
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Section number Title Page
18.10 GPC Memory Map/Register Definition........................................................................................................................191
18.11 GPC PGC Memory Map/Register Definition...............................................................................................................295
Chapter 19
Crystal Oscillator (XTALOSC) Placeholder
Chapter 20
Thermal Monitoring Unit (TMU) Placeholder
Chapter 21
System Boot
21.1 Overview.......................................................................................................................................................................325
21.2 Boot modes................................................................................................................................................................... 326
21.3 Device configuration.....................................................................................................................................................329
21.4 Device initialization......................................................................................................................................................331
21.5 Boot devices (internal boot)..........................................................................................................................................339
21.6 Boot image....................................................................................................................................................................385
21.7 USB boot.......................................................................................................................................................................388
21.8 Low-power boot............................................................................................................................................................388
21.9 SD/MMC manufacture mode........................................................................................................................................390
21.10 High-Assurance Boot (HAB)........................................................................................................................................390
21.11 Boot information for software...................................................................................................................................... 392
Chapter 22
Fusemap
22.1 Boot Fusemap............................................................................................................................................................... 395
22.2 Lock Fusemap...............................................................................................................................................................399
22.3 Fusemap Descriptions Table.........................................................................................................................................399
Chapter 23
On-Chip OTP Controller (OCOTP_CTRL) Placeholder
Chapter 24
Secure Non-Volatile Storage (SNVS)
24.1 Overview.......................................................................................................................................................................415
24.2 SNVS functional description........................................................................................................................................ 417
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Section number Title Page
24.3 External Signals............................................................................................................................................................ 421
24.4 Initialization of SNVS...................................................................................................................................................421
24.5 Memory Map and register definition............................................................................................................................ 422
Chapter 25
System Reset Controller (SRC) Placeholder
Chapter 26
Watchdog Timer (WDOG) Placeholder
Chapter 27
Interrupts and DMA Events
27.1 Overview.......................................................................................................................................................................449
27.2 A53 Interrupts............................................................................................................................................................... 449
27.3 CM7 Interrupts..............................................................................................................................................................457
27.4 Audio DSP Interrupts....................................................................................................................................................465
27.5 HDMI Interrupts........................................................................................................................................................... 466
27.6 SDMA event mapping.................................................................................................................................................. 466
Chapter 28
Smart Direct Memory Access Controller (SDMA)
28.1 Overview.......................................................................................................................................................................471
28.2 Functional Description..................................................................................................................................................475
28.3 Instruction Set...............................................................................................................................................................588
28.4 Software Restrictions....................................................................................................................................................644
28.5 Application Notes......................................................................................................................................................... 645
28.6 Arm Platform Memory Map and Control Register Definitions....................................................................................661
28.7 BP Memory Map and Control Register Definitions..................................................................................................... 697
28.8 SDMA Internal (Core) Memory Map and Internal Register Definitions..................................................................... 701
28.9 SDMA Peripheral Registers..........................................................................................................................................718
Chapter 29
Enhanced Direct Memory Access (eDMA)
29.1 Introduction...................................................................................................................................................................719
29.2 Modes of operation....................................................................................................................................................... 722
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Section number Title Page
29.3 Functional description...................................................................................................................................................723
29.4 Initialization/application information........................................................................................................................... 728
29.5 Memory map/register definition................................................................................................................................... 745
Chapter 30
Interrupt Request Steering (IRQ_STEER) Placeholder
Chapter 31
External Signals and Pin Multiplexing
31.1 Overview.......................................................................................................................................................................785
Chapter 32
IOMUX Controller (IOMUXC) Placeholder
Chapter 33
General Purpose Input/Output (GPIO)
33.1 Overview.......................................................................................................................................................................811
33.2 Functional Description..................................................................................................................................................812
33.3 External Signals............................................................................................................................................................ 815
33.4 Application Information................................................................................................................................................815
33.5 Memory Map/Register Definition.................................................................................................................................816
Chapter 34
External Memory Overview Placeholder
Chapter 35
DDR Controller (DDRC) Placeholder
Chapter 36
DDR BLK_CTRL Placeholder
Chapter 37
DDR PHY (DDR_PHY) Placeholder
Chapter 38
AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) Placeholder
Chapter 39
62BIT Correcting ECC Accelerator (BCH) Placeholder
Chapter 40
General Purpose Media Interface (GPMI) Placeholder
Chapter 41
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Section number Title Page
Enhanced Configurable SPI (ECSPI) Placeholder
Chapter 42
FlexSPI Controller (FlexSPI) Placeholder
Chapter 43
Ultra Secured Digital Host Controller (uSDHC)
43.1 Overview.......................................................................................................................................................................849
43.2 Functional description...................................................................................................................................................852
43.3 External signals.............................................................................................................................................................882
43.4 Application of uSDHC..................................................................................................................................................884
43.5 Software restrictions..................................................................................................................................................... 909
43.6 uSDHC memory map/register definition......................................................................................................................911
Chapter 44
HSIO BLK_CTRL Placeholder
Chapter 45
Universal Serial Bus Controller (USB) Placeholder
Chapter 46
Universal Serial Bus PHY (USB_PHY) Placeholder
Chapter 47
PCI Express (PCIe) Placeholder
Chapter 48
PCI Express PHY (PCIe_PHY) Placeholder
Chapter 49
Ethernet MAC (ENET) Placeholder
Chapter 50
Ethernet Quality Of Service (ENET_QOS) Placeholder
Chapter 51
FlexCAN
51.1 Overview.......................................................................................................................................................................1025
51.2 Functional description...................................................................................................................................................1028
51.3 FlexCAN signal descriptions........................................................................................................................................1086
51.4 Initialization/application information........................................................................................................................... 1087
51.5 Memory map/register definition................................................................................................................................... 1088
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Section number Title Page
51.6 Glossary........................................................................................................................................................................ 1166
Chapter 52
General Purpose Timer (GPT)
52.1 Overview.......................................................................................................................................................................1169
52.2 Functional Description..................................................................................................................................................1171
52.3 External Signals............................................................................................................................................................ 1177
52.4 Initialization/ Application Information ........................................................................................................................1178
52.5 Memory map and register definitions...........................................................................................................................1179
Chapter 53
Pulse Width Modulation (PWM)
53.1 Overview.......................................................................................................................................................................1191
53.2 External Signals............................................................................................................................................................ 1192
53.3 Functional Description..................................................................................................................................................1193
53.4 Enable Sequence for the PWM.....................................................................................................................................1195
53.5 Disable Sequence for the PWM....................................................................................................................................1195
53.6 PWM Memory Map/Register Definition......................................................................................................................1196
Chapter 54
Display, Imaging, and Camera Overview
54.1 Overview.......................................................................................................................................................................1205
54.2 Display Interface...........................................................................................................................................................1206
54.3 Graphics Processing Unit (GPU)..................................................................................................................................1208
54.4 Video Processing Unit (VPU).......................................................................................................................................1209
54.5 Image Signal Processor (ISP)....................................................................................................................................... 1209
54.6 Dewarp Engine..............................................................................................................................................................1212
54.7 Neural Processing Unit (NPU)......................................................................................................................................1213
Chapter 55
MEDIA BLK_CTRL Placeholder
Chapter 56
LCD Interface (LCDIF)
56.1 Overview.......................................................................................................................................................................1217
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Section number Title Page
56.2 Functional description...................................................................................................................................................1218
56.3 Memory Map and register definition............................................................................................................................ 1221
Chapter 57
Image Sensing Interface (ISI) Placeholder
Chapter 58
MIPI CSI Host Controller (MIPI_CSI) Placeholder
Chapter 59
MIPI DSI Host Controller (MIPI_DSI) Placeholder
Chapter 60
MIPI D-PHY (MIPI_DPHY) Placeholder
Chapter 61
LVDS Display Bridge (LDB) Placeholder
Chapter 62
HDMI TX Controller Placeholder
Chapter 63
HDMI TX PHY Placeholder
Chapter 64
HDMI TRNG Controller Placeholder
Chapter 65
HDMI TX BLK_CTRL Placeholder
Chapter 66
HDMI TX Parallel Audio Interface (HTX_PAI) Placeholder
Chapter 67
HDMI TX Parallel Video Interface (HTX_PVI) Placeholder
Chapter 68
Image Signal Processor (ISP) Placeholder
Chapter 69
DeWarp Placeholder
Chapter 70
Machine Learning Neural Processing Unit (NPU) Placeholder
Chapter 71
Audio Overview
71.1 Audio Interface............................................................................................................................................................. 1277
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Section number Title Page
71.2 Audio DSP (HiFi 4)...................................................................................................................................................... 1281
Chapter 72
AUDIO BLK_CTRL Placeholder
Chapter 73
PDM Microphone Interface (MICFIL) Placeholder
Chapter 74
Synchronous Audio Interface (SAI) Placeholder
Chapter 75
Asynchronous Sample Rate Converter (ASRC) Placeholder
Chapter 76
Enhanced Audio Return Channel (eARC) Placeholder
Chapter 77
Audio DSP (HiFi 4 DSP) Placeholder
Chapter 78
GPU Overview
78.1 Overview.......................................................................................................................................................................1295
78.2 Features.........................................................................................................................................................................1296
Chapter 79
2D Graphics Processing Unit (GPU2D) Placeholder
Chapter 80
3D Graphics Processing Unit (GPU3D) Placeholder
Chapter 81
VPU G1 Decoder Placeholder
Chapter 82
VPU G2 Decoder Placeholder
Chapter 83
VPU VC8000E Encoder Placeholder
Chapter 84
VPU BLK_CTRL Placeholder
Chapter 85
I2C Controller (I2C) Placeholder
Chapter 86
Universal Asynchronous Receiver/Transmitter (UART) Placeholder
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Chapter 1
Introduction
1.1 Product Overview
This chapter introduces the architecture of the i.MX 8M Plus Applications Processor.
The i.MX 8M Plus family is a set of NXP products focused on machine learning
applications, combining state-of-art multimedia features with high-performance
processing optimized for low-power consumption.
The i.MX 8M Plus Media Applications Processor is built to achieve both high
performance and low power consumption and relies on a powerful fully coherent core
complex based on a quad Cortex-A53 cluster, a Cortex-M7 low-power coprocessor,
audio digital signal processor, machine learning and graphics accelerators.
The i.MX 8M Family provides additional computing resources and peripherals:
• Advanced security modules for secure boot, cipher acceleration and DRM support
• A wide range of audio interfaces including I2S, AC97, and TDM
• Large set of peripherals that are commonly used in consumer/industrial markets
including USB , PCIe and Ethernet
1.2
Target Applications
The i.MX 8M Plus Media Applications Processor targets applications on:
• Smart Homes, Buildings and Cities
• Machine Learning and Industrial Automation
• Consumer and Pro Audio/Voice Systems
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1.3 Acronyms and Abbreviations
The table below contains acronyms and abbreviations used in this document.
Acronyms and Abbreviated Terms
Term Meaning
ADC Analog-to-Digital Converter
AHB Advanced High-performance Bus
AIPS Arm IP Bus
ALU Arithmetic Logic Unit
AMBA Advanced Microcontroller Bus Architecture
APB Advanced Peripheral Bus
ASRC Asynchronous Sample Rate Converter
AXI Advanced eXtensible Interface
CA/CM Arm Cortex-A/Cortex-M
CAAM Cryptographic Acceleration and Assurance Module
CA53 Arm Cortex A53 Core
CAN Controller Area Network
CM7 Arm Cortex M7 Core
CPU Central Processing Unit
CSI CMOS Sensor Interface
CSU Central Security Unit
CTI Cross Trigger Interface
D-cache Data cache
DAP Debug Access Port
DDR Double data rate
DMA Direct memory access
DPLL Digital phase-locked loop
DRAM Dynamic random access memory
ECC Error correcting codes
ECSPI Enhanced Configurable SPI
LPSPI Low-power SPI
EDMA Enhanced Direct Memory Access
EIM External Interface Module
ENET Ethernet
EPIT Enhanced Periodic Interrupt Timer
EPROM Erasable Programmable Read-Only Memory
ETF Embedded Trace FIFO
ETM Embedded Trace Macrocell
FIFO First-In-First-Out
Table continues on the next page...
Acronyms and Abbreviations
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Term Meaning
GIC General Interrupt Controller
GPC General Power Controller
GPIO General-Purpose I/O
GPR General-Purpose Register
GPS Global Positioning System
GPT General-Purpose Timer
GPU Graphics Processing Unit
GPV Global Programmers View
HAB High-Assurance Boot
I-cache Instruction cache
I2C or I
2
C Inter-Integrated Circuit
IC Integrated Circuit
IEEE Institute of Electrical and Electronics Engineers
IOMUX Input-Output Multiplexer
IP Intellectual Property
IrDA Infrared Data Association
ISP Image Signal Processor
JTAG Joint Test Action Group (a serial bus protocol usually used for test purposes)
ELCDIF Liquid Crystal Display Interface
LDO Low-Dropout
LIFO Last-In-First-Out
LRU Least-Recently Used
LSB Least-Significant Byte
LUT Look-Up Table
LVDS Low Voltage Differential Signaling
MAC Medium Access Control
MCM Miscellaneous Control Module
ML Machine Learning
MMC Multimedia Card
MSB Most-Significant Byte
MT/s Mega Transfers per second
NPU Neural Processing Unit
OCRAM On-Chip Random-Access Memory
OCOTP On-Chip One-Time Programmable Controller
PCI Peripheral Component Interconnect
PCIe PCI express
PCMCIA Personal Computer Memory Card International Association
PGC Power Gating Controller
PIC Programmable Interrupt Controller
PMU Power Management Unit
POR Power-On Reset
Table continues on the next page...
Chapter 1 Introduction
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Term Meaning
PSRAM Pseudo-Static Random Access Memory
PWM Pulse Width Modulation
PXP Pixel Pipeline
QoS Quality of Service
R2D Radians to Degrees
RISC Reduced Instruction Set Computing
ROM Read-Only Memory
RTOS Real-Time Operating System
Rx Receive
SAI Synchronous Audio Interface
SCU Snoop Control Unit
SD Secure Digital
SDIO Secure Digital Input/Output
SDLC Synchronous Data Link Control
SDMA Smart DMA
SIM Subscriber Identification Module
SNVS Secure Non-Volatile Storage
SoC System-on-Chip
SPBA Shared Peripheral Bus Arbiter
SPDIF Sony Phillips Digital Interface
SPI Serial Peripheral Interface
SRAM Static Random-Access Memory
SRC System Reset Controller
TFT Thin-Film Transistor
TPIU Trace Port Interface Unit
TSGEN Time Stamp Generator
Tx Transmit
TZASC TrustZone Address Space Controller
UART Universal Asynchronous Receiver/Transmitter
USB Universal Serial Bus
USDHC Ultra Secured Digital Host Controller
WDOG Watchdog
WLAN Wireless Local Area Network
WXGA Wide Extended Graphics Array
1.4 Architectural Overview
This section contains the i.MX 8M Plus architectural overview.
Architectural Overview
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1.4.1 Block Diagram
The high-level block diagram is shown in the figure below.
Debug
DAP
CTIs
SJC
Shared Peripherals
Internal Memory
OCRAM 576KB
ROM 256KB
External Memory
DDR Controller
SD/eMMC
SPBA(2)
PLLs
CCM
GPC
SRC
XTAL OSC
RC OSC
Timers
System Counter
Security
CSU
OCOTP (eFuse)
Power Management
AP Peripherals
PCIe Bus
Camera
WLAN
GPMI&BCH
QSPI
NAND FLASH
Display Interface
LCDIF(3)
LVDS
Smart DMA
SDMA(3)
Temp Monitor
IOMUX
LPDDR4/DDR4
Battery Ctrl
Device
JTAG
(IEEE1149.6)
Crystal&
Clock Source
CAAM
(32KB RAM)
SNVS(RTC)
Quad SPI
Flash
USB
(dev/host)
RDC
MU
SEMAPHORE
Multi-Core Unit
WDOG(3)
GPT(6)
eCSPI(3)
SAI(6)
UART(4)
GPIO(5)
UART(4)
PWM(4)
eCSPI(3)
I2C(6)
PCIe v3.0
AVB ENET
uSDHC(3)
Clock & Reset
10/100/1000M
Ethernet
AXI and AHB Switch Fabric
MMC/SD
eMMC/eSD
MMC/SD
SDXC
OCOTP
(2)
USB 3.0
eMMC 5.0
FLASH
OCRAM_S 36KB
MIPI DSI
CPU3
CPU2
L2 Cache 512 KB
SCU & Timer
I$ 32KB D$ 32KB
CPU0
CPU1
Arm Cortex A53
MPCore Platform
NEON CRYPTO
TCM 256KB
I$ 32KB
D$ 32KB
Cortex-M7 Core
Arm Cortex M7
Platform
NVIC
MPU
FPU
Graphics/Video
VPU
GPU
Machine Learning
NPU
PDM
I$ 32KB
D$ 48KB
DTCM 64KB
Audio DSP Core
OCRAM_A 256KB
ISP(2)
MIPI CSI2(2)
ISI
HDMI 2.0a
HDMI Display
LVDS Display
MIPI Display
with TSN
ENET Qos
1Gbit Ethernet
with TSN
CAN-FD(2)
Figure 1-1. Block Diagram
1.4.2
Features
Chapter 1 Introduction
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1.4.2.1 Arm Cortex-A53 MPCoreâ„¢ Platform
The i.MX 8M Family Applications Processors are based on the Arm Cortex-A53
MPCoreâ„¢ Platform, which has the following features:
• Quad symmetric Cortex-A53 processors, including:
• 32 KB L1 Instruction Cache
• 32 KB L1 Data Cache
• Media Processing Engine (MPE) with NEON technology supporting the
Advanced Single Instruction Multiple Data architecture
• Floating Point Unit (FPU) with support of the VFPv4-D16 architecture
• Support of 64-bit Armv8-A architecture
• 512 KB unified L2 cache
1.4.2.2 Arm Cortex-M7 Platform
The Cortex-M7 Core Platform includes the following:
• Low power microcontroller available for customer application:
• Low power standby mode
• IoT features including Weave
• Manage IR or wireless remote
• ML applications
• Arm Cortex-M7 CPU Processor, including:
• 32 KB L1 Instruction Cache
• 32 KB L1 Data Cache
• 256 KB TCM
1.4.2.3
System Bus and Interconnect
System bus and interconnect include the following:
• Network interconnect (NoC) AXI arbiter
• Quality of service controller (QoSC) to configure priorities and limits of AXI
transcations
• Performance monitor (PERFMON) to monitor AXI bus activity
• Debug monitor (DBGMON) to record AXI transactions preceding a system reset
Architectural Overview
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1.4.2.4 Clocking and Resets
Clocking and resets include:
• Clock control module (CCM) provides centralized clock generation and control
• Simplified clock tree structure
• Unified clock programming model for each clock root
• Multicore awareness for resource domains
• System reset controller (SRC) provides reset generation and distribution
1.4.2.5 Interrupts and DMA
Interrupts and DMA include:
• 160 shared peripheral interrupts routed to Cortex-A53 Global Interrupt Controller
(GIC) and Cortex-M7 nested vector interrupt controller (NVIC) for flexible interrupt
handling
• Three Smart direct memory access (SDMA) engines. Although these three engines
are identical to each other, they are integrated into the processor to serve different
peripherals.
• SDMA-1 is a general-purpose DMA engine which can be used by low speed
peripherals including UART, SPI and also others peripherals.
• SDMA-2 and SMDA-3 is used for audio interface, including SAI-1/2/3/5/6/7,
SPDIF and PDM audio input.
1.4.2.6
On-Chip Memory
The on-chip memory system consists of the following:
• Boot ROM (256KB)
• On-Chip RAM - OCRAM (576KB)
• Audio Processor System RAM - OCRAM_A (256KB)
• On-Chip RAM for State Retention - OCRAM_S (36KB)
1.4.2.7
External Memory Interface
The external memory interfaces supported on this chip include:
• 32-bit DRAM Interface:
Chapter 1 Introduction
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• LPDDR4-4000
• DDR4-3200
• 8-bit NAND FLASH, including support for Raw MLC/SLC devices, BCH ECC up to
62-bit, and ONFi3.2 compliance (clock rates up to 100 MHz and data rates up to 200
MB/sec)
• eMMC 5.1 FLASH (2 interfaces)
• SPI NOR FLASH (3 interfaces)
• FlexSPI FLASH with support for XIP (for Cortex-M7 in low-power mode) and
support for either one Octal SPI, or parallel read mode of two identical Quad SPI
FLASH devices
1.4.2.8 Timers
The timers on this chip include:
• One local generic timer integrated into each Cortex-A53 CPU
• Global system counter with timer bus interface to Cortex-A53 MPCore generic
timers
• One local system timer (SysTick) integrated into the Cortex-M7 CPU
• Six general purpose timer (GPT) modules
• Three watchdog timer (WDOG) modules
• Four pulse width modulation (PWM) modules
1.4.2.9
Graphics Processing Unit (GPU)
The chip incorporates the following Graphics Processing Unit (GPU) features:
• One GPU for 2D and composition acceleration
• Supports multi-source composition
• Supports one-pass filter
• Supports tile format
• One GPU for 3D processing
• Two Shader Execution Units
• Supports OpenGL ES 1.1, 2.0, 3.0, 3.1
• Supports OpenCL 3.0
• Supports OpenVG 1.1
• Supports OpenGL 4.0
• Supports EGL 1.5
• Supports Vulkan 1.1
• Supports tile format
Architectural Overview
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