e200z759n3 Core Reference Manual, Rev. 2
Freescale Semiconductor 1
e200z759n3 Core Reference Manual
Supports:
e200z759n3
e200z759n3CRM
Rev. 2
January 2015
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Freescale Semiconductor 3
Chapter 1
e200z759n3 Overview
1.1 Overview of the e200z759n3 ..........................................................................................................23
1.1.1 Features .............................................................................................................................23
1.1.2 Microarchitecture summary ..............................................................................................24
1.1.2.1 Instruction unit features ..................................................................................26
1.1.2.2 Integer unit features ........................................................................................27
1.1.2.3 Load/store unit features ..................................................................................27
1.1.2.4 Cache features .................................................................................................27
1.1.2.5 MMU Features ................................................................................................28
1.1.2.6 e200z759n3 system bus features .....................................................................28
Chapter 2
Register Model
2.1 PowerPC Book E registers ..............................................................................................................33
2.2 Zen-specific special purpose registers .............................................................................................35
2.3 Zen-specific device control registers ...............................................................................................37
2.4 Special-purpose register descriptions ..............................................................................................37
2.4.1 Machine State Register (MSR) .........................................................................................37
2.4.2 Processor ID Register (PIR) .............................................................................................39
2.4.3 Processor Version Register (PVR) ....................................................................................40
2.4.4 System Version Register (SVR) ........................................................................................41
2.4.5 Integer Exception Register (XER) ....................................................................................41
2.4.6 Exception Syndrome Register ..........................................................................................42
2.4.6.1 PowerPC VLE mode instruction syndrome ....................................................44
2.4.6.2 Misaligned instruction fetch syndrome ...........................................................44
2.4.7 Machine Check Syndrome Register (MCSR) ...................................................................45
2.4.8 Timer Control Register (TCR) ..........................................................................................47
2.4.9 Timer Status Register (TSR) .............................................................................................48
2.4.10 Debug registers .................................................................................................................49
2.4.11 Hardware Implementation Dependent Register 0 (HID0) ................................................50
2.4.12 Hardware Implementation Dependent Register 1 (HID1) ................................................52
2.4.13 Branch Unit Control and Status Register (BUCSR) .........................................................53
2.4.14 L1 Cache Control and Status Registers (L1CSR0, L1CSR1) ...........................................54
2.4.15 L1 Cache Configuration registers (L1CFG0, L1CFG1) ...................................................54
2.4.16 L1 Cache Flush and Invalidate registers (L1FINV0, L1FINV1) ......................................55
2.4.17 MMU Control and Status Register (MMUCSR0) ............................................................55
2.4.18 MMU Configuration register (MMUCFG) .......................................................................55
2.4.19 TLB Configuration registers (TLB0CFG, TLB1CFG) .....................................................55
2.5 SPR register access ..........................................................................................................................55
2.5.1 Invalid SPR references ......................................................................................................55
2.5.2 Synchronization requirements for SPRs ...........................................................................56
2.5.3 Special purpose register summary ....................................................................................57
2.6 Reset settings ...................................................................................................................................60
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Chapter 3
Instruction Model
3.1 Unsupported instructions and instruction forms .............................................................................65
3.2 Implementation-specific instructions ..............................................................................................65
3.3 Book E instruction extensions .........................................................................................................66
3.4 Memory access alignment support ..................................................................................................66
3.5 Memory synchronization and reservation instructions ...................................................................66
3.6 Branch prediction ............................................................................................................................68
3.7 Interruption of instructions by interrupt requests ............................................................................68
3.8 New Zen instructions and APUs .....................................................................................................68
3.9 ISEL APU .......................................................................................................................................69
3.10 Debug APU .....................................................................................................................................69
3.10.1 Debug notify halt instructions ...........................................................................................71
3.11 Machine Check APU .......................................................................................................................73
3.12 WAIT APU ......................................................................................................................................75
3.13 Enhanced reservations APU ............................................................................................................76
3.14 Volatile Context Save/Restore APU ................................................................................................79
3.15 Unimplemented SPRs and read-only SPRs .....................................................................................87
3.16 Invalid forms of instructions ...........................................................................................................87
3.16.1 Load and store with update instructions ...........................................................................87
3.16.2 Load multiple word (lmw, e_lmw) instruction .................................................................87
3.16.3 Branch conditional to count register instructions .............................................................87
3.16.4 Instructions with reserved fields non-zero ........................................................................88
3.17 Instruction summary ........................................................................................................................88
3.17.1 Instruction index sorted by mnemonic ..............................................................................89
3.17.2 Instruction index sorted by opcode .................................................................................102
Chapter 4
Instruction Pipeline and Execution Timing
4.1 Overview of operation ...................................................................................................................117
4.1.1 Control unit .....................................................................................................................119
4.1.2 Instruction unit ................................................................................................................119
4.1.3 Branch unit ......................................................................................................................119
4.1.4 Instruction decode unit ....................................................................................................119
4.1.5 Exception handling .........................................................................................................120
4.2 Execution units ..............................................................................................................................120
4.2.1 Integer execution units ....................................................................................................120
4.2.2 Load / store unit ..............................................................................................................120
4.2.3 Embedded floating-point execution units .......................................................................120
4.3 Instruction pipeline ........................................................................................................................120
4.3.1 Description of pipeline stages .........................................................................................122
4.3.2 Instruction prefetch buffers and branch target buffer .....................................................123
4.3.3 Single-cycle instruction pipeline operation ....................................................................125
4.3.4 Basic load and store instruction pipeline operation ........................................................125
4.3.5 Change-of-flow instruction pipeline operation ...............................................................126
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4.3.6 Basic multi-cycle instruction pipeline operation ............................................................128
4.3.7 Additional examples of instruction pipeline operation for load and store ......................129
4.3.8 Move to/from SPR instruction pipeline operation ..........................................................131
4.4 Control hazards .............................................................................................................................133
4.5 Instruction serialization .................................................................................................................133
4.5.1 Completion serialization .................................................................................................133
4.5.2 Dispatch serialization ......................................................................................................134
4.5.3 Refetch serialization .......................................................................................................134
4.6 Concurrent instruction execution ..................................................................................................135
4.7 Instruction Timings .......................................................................................................................136
4.8 Operand placement on performance .............................................................................................141
Chapter 5
Embedded Floating-Point APU (EFPU2)
5.1 Nomenclature and conventions .....................................................................................................143
5.2 EFPU programming model ...........................................................................................................143
5.2.1 Signal Processing Extension / Embedded Floating-point Status and Control Register
(SPEFSCR) 143
5.2.2 GPRs and PowerISA 2.06 instructions ...........................................................................147
5.2.3 SPE/EFPU available bit in MSR ....................................................................................147
5.2.4 Embedded floating-point exception bit in ESR ..............................................................147
5.2.5 EFPU exceptions .............................................................................................................147
5.2.5.1 EFPU unavailable exception .........................................................................148
5.2.5.2 Embedded floating-point data exception ......................................................148
5.2.5.3 Embedded floating-point round exception ...................................................148
5.2.6 Exception Priorities .........................................................................................................149
5.3 Embedded floating-point APU operations ....................................................................................149
5.3.1 Floating-point data formats .............................................................................................149
5.3.1.1 Single-precision floating-point format ..........................................................150
5.3.1.2 Half-precision floating-point format .............................................................151
5.3.2 IEEE 754 compliance .....................................................................................................152
5.3.3 Floating-point exceptions ...............................................................................................153
5.3.4 Embedded scalar single-precision floating-point instructions ........................................153
5.3.5 EFPU Vector Single-precision Embedded Floating-Point Instructions ..........................186
5.4 Embedded floating-point results summary ...................................................................................238
5.5 EFPU instruction timing ................................................................................................................253
5.5.1 EFPU single-precision vector floating-point instruction timing .....................................254
5.5.2 EFPU single-precision scalar floating-point instruction timing .....................................255
5.6 Instruction forms and opcodes ......................................................................................................256
5.6.1 Opcodes for EFPU vector floating-point instructions ....................................................257
5.6.2 Opcodes for EFPU scalar single-precision floating-point instructions ..........................259
Chapter 6
Signal Processing Extension APU (SPE APU)
6.1 Nomenclature and conventions .....................................................................................................261
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6.2 SPE programming model ..............................................................................................................261
6.2.1 SPE Status and Control Register (SPEFSCR) ................................................................261
6.2.2 Accumulator ....................................................................................................................263
6.2.2.1 Context switch ..............................................................................................264
6.2.3 GPRs and PowerPC Book E instructions .......................................................................264
6.2.4 SPE available bit in MSR ...............................................................................................264
6.2.5 SPE exception bit in ESR ...............................................................................................264
6.2.6 SPE exceptions ...............................................................................................................264
6.2.6.1 SPE APU Unavailable exception ..................................................................265
6.2.7 Exception priorities .........................................................................................................265
6.3 Integer SPE simple instructions ....................................................................................................265
6.4 Integer SPE multiply, multiply-accumulate, and operation to accumulator instructions (complex
integer instructions) 307
6.4.1 Multiply halfword instructions .......................................................................................308
6.4.2 Multiply words instructions ............................................................................................372
6.4.3 Add/subtract word to accumulator instructions ..............................................................412
6.4.4 Initializing and reading the accumulator ........................................................................420
6.5 SPE vector load/store instructions .................................................................................................422
6.6 SPE instruction timing ..................................................................................................................458
6.6.1 SPE integer simple instructions timing ...........................................................................458
6.6.2 SPE load and store instruction timing .............................................................................460
6.6.3 SPE complex integer instruction timing .........................................................................461
6.7 Instruction forms and opcodes ......................................................................................................465
6.7.1 SPE vector integer simple instructions ...........................................................................466
6.7.2 Opcodes for SPE load and store instructions ..................................................................468
6.7.3 Opcodes for SPE complex integer instructions ..............................................................469
Chapter 7
Interrupts and Exceptions
7.1 e200z759n3 interrupts ...................................................................................................................479
7.2 Exception Syndrome Register (ESR) ............................................................................................482
7.3 Machine State Register (MSR) ......................................................................................................484
7.3.1 Machine Check Syndrome Register (MCSR) .................................................................486
7.4 Interrupt Vector Prefix Registers (IVPR) ......................................................................................489
7.5 Interrupt Vector Offset Registers (IVORxx) .................................................................................490
7.6 Hardware Interrupt Vector Offset Values (p_voffset[0:15]) ..........................................................490
7.7 Interrupt definitions .......................................................................................................................491
7.7.1 Critical Input interrupt (IVOR0) .....................................................................................491
7.7.2 Machine Check interrupt (IVOR1) .................................................................................492
7.7.2.1 Machine check causes ...................................................................................492
7.7.2.1.1Error report machine check exceptions ........................................................492
7.7.2.1.2Non-maskable interrupt machine check exceptions .....................................497
7.7.2.1.3Asynchronous machine check exceptions ....................................................497
7.7.2.2 Machine check interrupt actions ...................................................................504
7.7.2.3 Checkstop state .............................................................................................505
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7.7.3 Data Storage interrupt (IVOR2) ......................................................................................505
7.7.4 Instruction Storage interrupt (IVOR3) ............................................................................506
7.7.5 External Input interrupt (IVOR4) ...................................................................................507
7.7.6 Alignment interrupt (IVOR5) .........................................................................................508
7.7.7 Program interrupt (IVOR6) ............................................................................................508
7.7.8 Floating-Point Unavailable interrupt (IVOR7) ...............................................................509
7.7.9 System Call interrupt (IVOR8) .......................................................................................510
7.7.10 Auxiliary Processor Unavailable interrupt (IVOR9) ......................................................510
7.7.11 Decrementer interrupt (IVOR10) ....................................................................................510
7.7.12 Fixed-Interval Timer interrupt (IVOR11) .......................................................................511
7.7.13 Watchdog Timer interrupt (IVOR12) ..............................................................................512
7.7.14 Data TLB Error interrupt (IVOR13) ...............................................................................512
7.7.15 Instruction TLB Error interrupt (IVOR14) .....................................................................513
7.7.16 Debug interrupt (IVOR15) ..............................................................................................514
7.7.17 System Reset interrupt ....................................................................................................516
7.7.18 SPE/EFPU APU Unavailable interrupt (IVOR32) .........................................................518
7.7.19 Embedded Floating-point Data interrupt (IVOR33) .......................................................518
7.7.20 Embedded Floating-point Round interrupt (IVOR34) ....................................................519
7.7.21 Performance monitor interrupt (IVOR35) ......................................................................519
7.8 Exception recognition and priorities .............................................................................................520
7.8.1 Exception priorities .........................................................................................................522
7.9 Interrupt processing .......................................................................................................................525
7.9.1 Enabling and disabling exceptions .................................................................................526
7.9.2 Returning from an interrupt handler ...............................................................................527
7.10 Process switching ..........................................................................................................................527
Chapter 8
Performance Monitor
8.1 Overview .......................................................................................................................................529
8.2 Performance Monitor APU instructions ........................................................................................530
8.3 Performance Monitor APU registers .............................................................................................531
8.3.1 Invalid PMR references ..................................................................................................532
8.3.2 References to read-only PMRs .......................................................................................532
8.3.3 Performance Monitor Global Control Register 0 (PMGC0) ..........................................532
8.3.4 User Performance Monitor Global Control Register 0 (UPMGC0) ...............................534
8.3.5 Performance Monitor Local Control A Registers (PMLCa0–PMLCa3) ........................534
8.3.6 User Performance Monitor Local Control A Registers (UPMLCa0–UPMLCa3) .........535
8.3.7 Performance Monitor Local Control B Registers (PMLCb0–PMLCb3) ........................535
8.3.8 User Performance Monitor Local Control B registers (UPMLCb0–UPMLCb3) ...........540
8.3.9 Performance Monitor Counter registers (PMC0–PMC3) ...............................................540
8.3.10 User Performance Monitor Counter registers (UPMC0–UPMC3) .................................541
8.4 Performance monitor interrupt ......................................................................................................541
8.5 Event counting ...............................................................................................................................542
8.5.1 MSR-based context filtering ...........................................................................................542
8.6 Examples .......................................................................................................................................543
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8.6.1 Chaining counters ...........................................................................................................543
8.6.2 Thresholding ...................................................................................................................543
8.7 Event selection ..............................................................................................................................544
Chapter 9
Power Management
9.1 Power management .......................................................................................................................555
9.1.1 Active state .....................................................................................................................555
9.1.2 Waiting state ....................................................................................................................555
9.1.3 Halted state .....................................................................................................................555
9.1.4 Stopped state ...................................................................................................................556
9.1.5 Power management pins .................................................................................................556
9.1.6 Power management control bits ......................................................................................557
9.1.7 Software considerations for power management using wait instructions .......................557
9.1.8 Software considerations for power management using Doze, Nap or Sleep ..................558
9.1.9 Debug considerations for power management ................................................................558
Chapter 10
Memory Management Unit
10.1 Overview .......................................................................................................................................559
10.2 Effective to real address translation ..............................................................................................559
10.2.1 Effective addresses ..........................................................................................................559
10.2.2 Address spaces ................................................................................................................559
10.2.3 Process ID .......................................................................................................................560
10.2.4 Translation flow ..............................................................................................................560
10.2.5 Permissions .....................................................................................................................562
10.2.6 Restrictions on 1 KB and 2 KB page size usage .............................................................563
10.3 Translation Lookaside Buffer (TLB) .............................................................................................563
10.4 Configuration information .............................................................................................................564
10.4.1 MMU Configuration Register (MMUCFG) ...................................................................564
10.4.2 TLB0 Configuration Register (TLB0CFG) ....................................................................565
10.4.3 TLB1 Configuration Register (TLB1CFG) ....................................................................566
10.5 Software interface and TLB instructions ......................................................................................567
10.5.1 TLB read entry instruction (tlbre) ...................................................................................568
10.5.2 TLB write entry instruction (tlbwe) ................................................................................568
10.5.3 TLB search instruction (tlbsx) ........................................................................................568
10.5.4 TLB Invalidate (tlbivax) Instruction ...............................................................................569
10.5.5 TLB synchronize instruction (tlbsync) ...........................................................................570
10.6 TLB operations ..............................................................................................................................571
10.6.1 Translation reload ...........................................................................................................571
10.6.2 Reading the TLB .............................................................................................................571
10.6.3 Writing the TLB ..............................................................................................................571
10.6.4 Searching the TLB ..........................................................................................................571
10.6.5 TLB miss exception update ............................................................................................572
10.6.6 IPROT invalidation protection ........................................................................................572
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10.6.7 TLB load on reset ...........................................................................................................572
10.6.8 The G bit .........................................................................................................................573
10.7 MMU control registers ..................................................................................................................573
10.7.1 Data Exception Address Register (DEAR) .....................................................................573
10.7.2 MMU Control and Status Register 0 (MMUCSR0) .......................................................573
10.7.3 MMU assist registers (MAS) ..........................................................................................574
10.7.3.1 MMU Read/Write and Replacement Control register (MAS0) ....................574
10.7.3.2 Descriptor Context and Configuration Control register (MAS1) .................575
10.7.3.3 EPN and Page Attributes register (MAS2) ...................................................576
10.7.3.4 RPN and Access Control register (MAS3) ...................................................577
10.7.3.5 Hardware Replacement Assist Configuration register (MAS4) ...................578
10.7.3.6 TLB Search Context Register 0 (MAS6) ......................................................579
10.7.4 MAS registers summary .................................................................................................580
10.7.5 MAS register updates ......................................................................................................580
10.8 TLB coherency control ..................................................................................................................581
10.9 Core interface operation for MMU control instructions ...............................................................581
10.9.1 Transfer type encodings for MMU control instructions .................................................581
10.10Effect of hardware debug on MMU operation ..............................................................................582
10.11External translation alterations for realtime systems ....................................................................583
Chapter 11
L1 Cache
11.1 Overview .......................................................................................................................................585
11.2 16 KB cache organization .............................................................................................................586
11.3 Cache lookup .................................................................................................................................587
11.4 Cache control .................................................................................................................................589
11.4.1 L1 Cache Control and Status Register 0 (L1CSR0) .......................................................589
11.4.2 L1 Cache Control and Status Register 1 (L1CSR1) .......................................................593
11.4.3 L1 Cache Configuration Register 0 (L1CFG0) ..............................................................595
11.4.4 L1 Cache Configuration Register 1 (L1CFG1) ..............................................................596
11.5 Data cache software coherency .....................................................................................................597
11.6 Address aliasing ............................................................................................................................597
11.7 Cache Operation ............................................................................................................................598
11.7.1 Cache enable/disable .......................................................................................................598
11.7.2 Cache fills .......................................................................................................................598
11.7.3 Cache line replacement ...................................................................................................599
11.7.4 Cache miss access ordering ............................................................................................599
11.7.5 Cache-inhibited accesses ................................................................................................599
11.7.6 Guarded accesses ............................................................................................................600
11.7.7 Cache-inhibited guarded accesses ..................................................................................600
11.7.8 Cache invalidation ..........................................................................................................600
11.7.9 Cache flush/invalidate by set and way ............................................................................601
11.7.9.1 L1 Flush and Invalidate Control Register 0 (L1FINV0) ..............................601
11.7.9.2 L1 Flush and Invalidate Control Register 1 (L1FINV1) ..............................602
11.8 Cache parity and EDC protection ..................................................................................................603
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11.8.1 Cache error action control ...............................................................................................604
11.8.1.1 L1CSR[0,1][I,D]CEA = 00, machine check generation on error .................604
11.8.1.2 L1CSR[0,1][I,D]CEA = 01, correction/auto-invalidation on error ..............605
11.8.1.2.1Instruction cache errors ..............................................................................605
11.8.1.2.2Data cache errors ........................................................................................606
11.8.1.2.3Data cache line flush or invalidation due to reservation instructions
(l[b,h,w]arx, st[b,h,w]cx.) .......................................................................607
11.8.2 Parity/EDC error handling for cache control operations and instructions ......................607
11.8.2.1 L1FINV[0,1] operations ...............................................................................607
11.8.2.2 Cache touch instructions (dcbt, dcbtst, icbt) .................................................608
11.8.2.3 icbi instructions .............................................................................................608
11.8.2.4 dcbi instructions ............................................................................................608
11.8.2.5 dcbst instructions ..........................................................................................609
11.8.2.6 dcbf instructions ............................................................................................609
11.8.2.7 dcbz instructions ...........................................................................................609
11.8.2.8 Cache locking instructions (dcbtls, dcbtstls, dcblc, icbtls, icblc) .................610
11.8.3 Cache inhibited accesses and parity/EDC errors ............................................................610
11.8.4 Snoop operations and parity/EDC errors ........................................................................611
11.8.5 EDC checkbit/syndrome coding scheme generation — ICache .....................................611
11.8.6 EDC checkbit/syndrome coding scheme generation — DCache ...................................612
11.8.7 Cache error injection .......................................................................................................612
11.9 Push and store buffers ...................................................................................................................613
11.10 Cache management instructions ....................................................................................................614
11.10.1Instruction cache block invalidate (icbi) instruction .......................................................614
11.10.2Instruction cache block touch (icbt) instruction .............................................................614
11.10.3Data cache block allocate (dcba) instruction ..................................................................614
11.10.4Data cache block flush (dcbf) instruction .......................................................................615
11.10.5Data cache block invalidate (dcbi) instruction ...............................................................615
11.10.6Data cache block store (dcbst) instruction ......................................................................615
11.10.7Data cache block touch (dcbt) instruction ......................................................................615
11.10.8Data cache block touch for store (dcbtst) instruction .....................................................615
11.10.9Data cache block set to zero (dcbz) instruction ..............................................................615
11.11 Touch instructions .........................................................................................................................616
11.12 Cache line locking/unlocking APU ...............................................................................................616
11.12.1Overview .........................................................................................................................616
11.12.2dcbtls — data cache block touch and lock set ................................................................618
11.12.3dcbtstls — data cache block touch for store and lock set ...............................................619
11.12.4dcblc — data cache block lock clear ..............................................................................619
11.12.5icbtls — instruction cache block touch and lock set .......................................................620
11.12.6icblc — instruction cache block lock clear .....................................................................621
11.12.7Effects of other cache instructions on locked lines .........................................................622
11.12.8Flash clearing of lock bits ...............................................................................................622
11.13 Cache instructions and exceptions ................................................................................................623
11.13.1Exception conditions for cache instructions ...................................................................623
11.13.2Transfer type encodings for cache management instructions .........................................624
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11.14Sequential consistency ..................................................................................................................625
11.15Self-modifying code requirements ................................................................................................625
11.16Page table control bits ...................................................................................................................625
11.16.1Writethrough stores .........................................................................................................626
11.16.2Cache-inhibited accesses ................................................................................................626
11.16.3Memory coherence required ...........................................................................................626
11.16.4Guarded storage ..............................................................................................................626
11.16.5Misaligned accesses and the endian (E) bit ....................................................................626
11.17Reservation instructions and cache interactions ............................................................................626
11.18Effect of hardware debug on cache operation ...............................................................................627
11.19Cache memory access for debug / error handling .........................................................................627
11.19.1Cache memory access via software ................................................................................627
11.19.2Cache memory access through JTAG/OnCE port ..........................................................628
11.19.3Cache Debug Access Control register (CDACNTL) ......................................................629
11.19.3.1 Cache Debug Access Data register (CDADATA) ........................................630
11.20 Hardware Debug (Cache) Control Register 0 ...............................................................................631
11.21Hardware cache coherency ............................................................................................................632
11.21.1Coherency protocol .........................................................................................................633
11.21.2Snoop command port ......................................................................................................633
11.21.3Snoop request queue .......................................................................................................635
11.21.4Snoop lookup operation ..................................................................................................635
11.21.5Snoop errors ....................................................................................................................636
11.21.6Snoop collisions ..............................................................................................................636
11.21.7Snoop synchronization ....................................................................................................636
11.21.7.1Synchronization port request ........................................................................636
11.21.7.2 Snoop command port request .......................................................................637
11.21.8Starvation control ............................................................................................................637
11.21.9Queue flow control .........................................................................................................637
11.21.10Snooping in low power states .......................................................................................638
Chapter 12
Debug Support
12.1 Overview .......................................................................................................................................639
12.1.1 Software debug facilities ................................................................................................639
12.1.1.1 PowerISA 2.06 compatibility ........................................................................640
12.1.2 Additional debug facilities ..............................................................................................640
12.1.3 Hardware debug facilities ...............................................................................................640
12.1.4 Sharing debug resources by software/hardware .............................................................641
12.1.4.1 Simultaneous hardware and software debug event handing .........................641
12.2 Software debug events and exceptions ..........................................................................................642
12.2.1 Instruction Address Compare event ................................................................................643
12.2.2 Data Address Compare event .........................................................................................644
12.2.2.1 Data Address Compare event status updates ................................................645
12.2.3 Linked Instruction Address and Data Address Compare event ......................................655
12.2.4 Trap debug event .............................................................................................................656
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12.2.5 Branch Taken debug event ..............................................................................................656
12.2.6 Instruction Complete debug event ..................................................................................656
12.2.7 Interrupt Taken debug event ...........................................................................................657
12.2.8 Critical Interrupt Taken debug event ..............................................................................657
12.2.9 Return debug event .........................................................................................................657
12.2.10Critical Return debug event ............................................................................................658
12.2.11Debug Counter debug event ...........................................................................................658
12.2.12External debug event ......................................................................................................658
12.2.13Unconditional debug event .............................................................................................658
12.3 Debug registers ..............................................................................................................................659
12.3.1 Debug address and value registers ..................................................................................659
12.3.2 Debug Counter register (DBCNT) ..................................................................................660
12.3.3 Debug Control and Status registers .................................................................................660
12.3.3.1 Debug Control Register 0 (DBCR0) .............................................................661
12.3.3.2 Debug Control Register 1 (DBCR1) .............................................................663
12.3.3.3 Debug Control Register 2 (DBCR2) .............................................................665
12.3.3.4 Debug Control Register 3 (DBCR3) .............................................................669
12.3.3.5 Debug Control Register 4 (DBCR4) .............................................................674
12.3.3.6 Debug Control Register 5 (DBCR5) .............................................................675
12.3.3.7 Debug Control Register 6 (DBCR6) .............................................................677
12.3.3.8 Debug Status register (DBSR) ......................................................................679
12.3.4 Debug External Resource Control register (DBERC0) ..................................................681
12.3.5 Debug Event Select register (DEVENT) ........................................................................688
12.3.6 Debug Data Acquisition Message register (DDAM) ......................................................689
12.4 External debug support ..................................................................................................................689
12.4.1 External debug registers ..................................................................................................690
12.4.1.1 External Debug Control Register 0 (EDBCR0) ............................................691
12.4.1.2 External Debug Status Register 0 (EDBSR0) ...............................................692
12.4.1.3 External Debug Status Register Mask 0 (EDBSRMSK0) ............................694
12.4.2 OnCE introduction ..........................................................................................................696
12.4.3 JTAG/OnCE pins ............................................................................................................698
12.4.4 OnCE internal interface signals ......................................................................................698
12.4.4.1 CPU debug request (dbg_dbgrq) ..................................................................699
12.4.4.2 CPU debug acknowledge (cpu_dbgack) .......................................................699
12.4.4.3 CPU address, attributes .................................................................................699
12.4.4.4 CPU data .......................................................................................................699
12.4.5 OnCE interface signals ...................................................................................................699
12.4.5.1 OnCE enable (jd_en_once) ...........................................................................699
12.4.5.2 OnCE debug request/event (jd_de_b, jd_de_en) ..........................................700
12.4.5.3 e200z759n3 OnCE debug output (jd_debug_b) ...........................................700
12.4.5.4 e200z759n3 CPU clock on input (jd_mclk_on) ...........................................700
12.4.5.5 Watchpoint events (jd_watchpt[0:29]) ..........................................................700
12.4.6 e200z759n3 OnCE controller and serial interface ..........................................................701
12.4.6.1 e200z759n3 OnCE Status Register (OSR) ...................................................701
12.4.6.2 e200z759n3 OnCE Command register (OCMD) ..........................................702
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12.4.6.3 e200z759n3 OnCE Control Register (OCR) ................................................706
12.4.7 Access to debug resources ..............................................................................................708
12.4.8 Methods of entering debug mode ...................................................................................710
12.4.8.1 External debug request during RESET .........................................................710
12.4.8.2 Debug request during RESET .......................................................................710
12.4.8.3 Debug request during normal activity ..........................................................711
12.4.8.4 Debug request during Waiting, Halted, or Stopped state ..............................711
12.4.8.5 Software request during normal activity .......................................................711
12.4.8.6 Debug notify halt instructions .......................................................................711
12.4.9 CPU Status and Control Scan Chain Register (CPUSCR) .............................................712
12.4.9.1 Instruction Register (IR) ...............................................................................712
12.4.9.2 Control State register (CTL) .........................................................................713
12.4.9.3 Program Counter register (PC) .....................................................................716
12.4.9.4 Write-Back Bus Register (WBBRlow, WBBRhigh) ....................................716
12.4.9.5 Machine State Register (MSR) .....................................................................717
12.4.9.6 Exiting debug mode and interrupt blocking .................................................717
12.4.10Instruction Address FIFO buffer (PC FIFO) ..................................................................717
12.4.10.1PC FIFO ........................................................................................................717
12.4.11Reserved registers (reserved) ..........................................................................................719
12.5 Watchpoint support ........................................................................................................................719
12.6 MMU and cache operation during debug ......................................................................................721
12.7 Cache array access during debug ..................................................................................................722
12.8 Basic steps for enabling, using, and exiting external debug mode ...............................................722
12.9 Parallel Signature unit ...................................................................................................................723
12.9.1 Parallel Signature Control Register (PSCR) ...................................................................725
12.9.2 Parallel Signature Status Register (PSSR) ......................................................................725
12.9.3 Parallel Signature High Register (PSHR) .......................................................................726
12.9.4 Parallel Signature Low Register (PSLR) ........................................................................726
12.9.5 Parallel Signature Counter Register (PSCTR) ................................................................727
12.9.6 Parallel Signature Update High Register (PSUHR) .......................................................727
12.9.7 Parallel Signature Update Low Register (PSULR) .........................................................727
Chapter 13
Nexus 3 Module
13.1 Introduction ...................................................................................................................................729
13.1.1 General description .........................................................................................................729
13.1.2 Terms and definitions ......................................................................................................729
13.1.3 Feature list .......................................................................................................................730
13.1.4 Functional block diagram ...............................................................................................732
13.2 Enabling Nexus 3 operation ..........................................................................................................732
13.3 TCODEs supported .......................................................................................................................733
13.4 Nexus 3 programmer’s model .......................................................................................................739
13.4.1 Client Select Control register (CSC) ..............................................................................741
13.4.2 Port Configuration Register (PCR) — reference only ....................................................741
13.4.3 Nexus Development Control Register 1 (DC1) ..............................................................742
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13.4.4 Nexus Development Control Registers 2 and 3 (DC2, DC3) .........................................744
13.4.5 Nexus Development Control Register 4 (DC4) ..............................................................748
13.4.6 Development Status register (DS) ..................................................................................749
13.4.7 Watchpoint Trigger registers (WT, PTSTC, PTETC, DTSTC, DTETC) ........................749
13.4.8 Nexus Watchpoint Mask register (WMSK) ....................................................................754
13.4.9 Nexus Overrun Control Register (OVCR) ......................................................................755
13.4.10Data Trace Control Register (DTC) ................................................................................756
13.4.11Data Trace Start Address Registers (DTSA1–4) ............................................................758
13.4.12Data Trace End Address registers (DTEA1–4) ...............................................................758
13.4.13Read/Write Access Control/Status register (RWCS) ......................................................760
13.4.14Read/Write Access Data (RWD) .....................................................................................761
13.4.15Read/Write Access Address register (RWA) ..................................................................763
13.5 Nexus 3 register access via JTAG/OnCE ......................................................................................763
13.6 Nexus message fields ....................................................................................................................764
13.6.1 TCODE field ...................................................................................................................764
13.6.2 Source ID field (SRC) .....................................................................................................764
13.6.3 Relative address field (U-ADDR) ...................................................................................764
13.6.4 Full address field (F-ADDR) ..........................................................................................765
13.6.5 Address space indication field (MAP) ............................................................................765
13.7 Nexus message queues ..................................................................................................................766
13.7.1 Message queue overrun ..................................................................................................766
13.7.2 CPU stall .........................................................................................................................766
13.7.3 Message suppression .......................................................................................................766
13.7.4 Nexus message priority ...................................................................................................767
13.7.5 Data Acquisition Message (DQM) priority loss response ..............................................768
13.7.6 Ownership Trace Message (OTM) priority loss response ..............................................768
13.7.7 Program Trace Message (PTM) priority loss response ...................................................768
13.7.8 Data Trace Message (DTM) priority loss response ........................................................768
13.8 Debug Status messages .................................................................................................................768
13.9 Error messages ..............................................................................................................................769
13.10Ownership trace .............................................................................................................................769
13.10.1Overview .........................................................................................................................769
13.10.2Ownership Trace Messaging (OTM) ..............................................................................769
13.11Program trace ................................................................................................................................770
13.11.1Branch Trace messaging types ........................................................................................770
13.11.1.1Zen Indirect Branch message instructions ....................................................771
13.11.1.2Zen Direct Branch Message instructions ......................................................771
13.11.1.3BTM using Branch History Messages ..........................................................772
13.11.1.4BTM using Traditional Program Trace messages .........................................772
13.11.2BTM Message formats ....................................................................................................772
13.11.2.1Indirect Branch Messages (history) ..............................................................772
13.11.2.2Indirect Branch Messages (traditional) .........................................................773
13.11.2.3Direct Branch Messages (traditional) ...........................................................773
13.11.3Program Trace message fields ........................................................................................773
13.11.3.1Sequential Instruction Count field (ICNT) ...................................................773
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13.11.3.2Branch/Predicate Instruction History (HIST) ...............................................774
13.11.3.3Execution mode indication ...........................................................................774
13.11.4Resource Full Messages ..................................................................................................775
13.11.5Program Correlation Messages (PCM) ...........................................................................775
13.11.5.1 Program Correlation Message generation for TLB update with new address
translation .....................................................................................................................777
13.11.5.2Program Correlation Message generation for TLB invalidate (tlbivax)
operations ......................................................................................................................778
13.11.5.3 Program Correlation Message generation for PID updates or MSRIS updates ..
.......................................................................................................................................778
13.11.6Program trace overflow error messages ..........................................................................778
13.11.7Program trace synchronization messages .......................................................................778
13.11.8Enabling Program Trace .................................................................................................780
13.11.9Program Trace timing diagrams (2 MDO / 1 MSEO configuration) ..............................781
13.12 Data Trace ....................................................................................................................................782
13.12.1Data Trace Messaging (DTM) ........................................................................................782
13.12.2DTM Message formats ...................................................................................................782
13.12.2.1Data Write Messages ....................................................................................782
13.12.2.2Data Read Messages .....................................................................................782
13.12.2.3Data Trace Synchronization Messages .........................................................783
13.12.3DTM operation ...............................................................................................................784
13.12.3.1Data trace windowing ...................................................................................784
13.12.3.2Data access / instruction access data tracing ................................................785
13.12.3.3Data trace filtering ........................................................................................785
13.12.3.4Zen bus cycle special cases ...........................................................................785
13.12.4Data Trace Timing Diagrams(8 MDO / 2 MSEO configuration) ...................................786
13.13Data Acquisition messaging ..........................................................................................................786
13.13.1Data Acquisition ID Tag field .........................................................................................787
13.13.2Data Acquisition Data field ............................................................................................787
13.13.3Data Acquisition Trace event ..........................................................................................787
13.14Watchpoint Trace Messaging ........................................................................................................787
13.14.1Watchpoint Timing Diagram (2 MDO / 1 MSEO configuration) ...................................789
13.15Nexus 3 read/write access to memory-mapped resources .............................................................790
13.15.1Single write Access .........................................................................................................790
13.15.2Block write access ..........................................................................................................791
13.15.3Single read access ...........................................................................................................791
13.15.4Block read access ............................................................................................................792
13.15.5Error handling .................................................................................................................792
13.15.5.1AHB read/write error ....................................................................................793
13.15.5.2Access termination ........................................................................................793
13.15.6Read/write access error message ....................................................................................793
13.16Nexus 3 pin interface .....................................................................................................................793
13.16.1Pins implemented ............................................................................................................793
13.16.2Pin protocol .....................................................................................................................796
13.17Rules for output messages .............................................................................................................798
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13.18Auxiliary port arbitration ..............................................................................................................798
13.19Examples .......................................................................................................................................798
13.20Electrical characteristics ................................................................................................................801
13.21IEEE 1149.1 (JTAG) RD/WR sequences ......................................................................................801
13.21.1JTAG sequence for accessing internal Nexus registers ..................................................801
13.21.2JTAG sequence for read access of memory-mapped resources ......................................802
13.21.3JTAG sequence for write access of memory-mapped resources ....................................802
Chapter 14
External Core Complex Interfaces
14.1 Signal index ...................................................................................................................................806
14.2 Signal descriptions ........................................................................................................................813
14.2.1 e200z759n3 processor clock (m_clk) .............................................................................814
14.2.2 Reset-related signals .......................................................................................................814
14.2.2.1 Power-on reset (m_por) ................................................................................814
14.2.2.2 Reset (p_reset_b) ..........................................................................................814
14.2.2.3 Watchdog reset status (p_wrs[0:1]) ..............................................................815
14.2.2.4 Debug reset control (p_dbrstc[0:1]) ..............................................................815
14.2.2.5 Reset base (p_rstbase[0:29]) .........................................................................815
14.2.2.6 Reset endian mode (p_rst_endmode) ............................................................815
14.2.2.7 Reset VLE Mode (p_rst_vlemode) ...............................................................815
14.2.2.8 JTAG/OnCE reset (j_trst_b) .........................................................................815
14.2.3 Address and data buses ...................................................................................................816
14.2.3.1 Address bus (p_d_haddr[31:0], p_i_haddr[31:0]) ........................................816
14.2.3.2 Read data bus (p_d_hrdata[63:0], p_i_hrdata[63:0]) ....................................816
14.2.3.3 Write data bus (p_d_hwdata[63:0]) ..............................................................816
14.2.4 Transfer attribute signals .................................................................................................817
14.2.4.1 Transfer type (p_d_htrans[1:0], p_i_htrans[1:0]) .........................................817
14.2.4.2 Write (p_d_hwrite, p_i_hwrite) ....................................................................817
14.2.4.3 Transfer size (p_d_hsize[1:0], p_i_hsize[1:0]) .............................................817
14.2.4.4 Burst type (p_d_hburst[2:0], p_i_hburst[2:0]) ..............................................818
14.2.4.5 Protection control (p_d_hprot[5:0], p_i_hprot[5:0]) ....................................818
14.2.4.6 Transfer data error (p_d_htrans_derr) ...........................................................820
14.2.4.7 Globally coherent access — (p_d_gbl) .........................................................820
14.2.4.8 Cache way replacement (p_d_wayrep[0:1], p_i_wayrep[0:1]) ....................820
14.2.5 Byte lane specification ....................................................................................................820
14.2.5.1 Unaligned access (p_d_hunalign, p_i_hunalign) ..........................................821
14.2.5.2 Byte strobes (p_d_hbstrb[7:0], p_i_hbstrb[7:0]) ..........................................821
14.2.6 Transfer control signals ...................................................................................................831
14.2.6.1 Transfer ready (p_d_hready, p_i_hready) .....................................................831
14.2.6.2 Transfer response (p_d_hresp[2:0], p_i_hresp[1:0]) ....................................831
14.2.6.3 Bus stall global write request (p_stall_bus_gwrite) ......................................832
14.2.7 AHB clock enable signals ...............................................................................................832
14.2.7.1 Instruction AHB clock enable (p_i_ahb_clken) ...........................................832
14.2.7.2 Data AHB clock enable (p_d_ahb_clken) ....................................................833
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14.2.8 Master ID configuration signals .....................................................................................833
14.2.8.1 CPU master ID (p_masterid[3:0]) .................................................................833
14.2.8.2 Nexus master ID (nex_masterid[3:0]) ..........................................................833
14.2.9 Coherency control signals ...............................................................................................833
14.2.9.1 Snoop ready (p_snp_rdy) ..............................................................................833
14.2.9.2 Snoop request (p_snp_req) ...........................................................................834
14.2.9.3 Snoop command input (p_snp_cmd_in[0:1]) ...............................................834
14.2.9.4 Snoop request ID input (p_snp_id_in[0:3]) ..................................................834
14.2.9.5 Snoop address input (p_snp_addr_in[0:26]) .................................................835
14.2.9.6 Snoop acknowledge (p_snp_ack) .................................................................835
14.2.9.7 Snoop request ID output (p_snp_id_out[0:3]) ..............................................835
14.2.9.8 Snoop response (p_snp_resp[0:4]) ................................................................835
14.2.9.9 Cache stalled (p_cac_stalled) ........................................................................836
14.2.9.10Data cache enabled (p_d_cache_en) .............................................................836
14.2.10Memory synchronization control signals ........................................................................836
14.2.10.1Synchronization request in (p_sync_req_in) ................................................836
14.2.10.2Synchronization request acknowledge out (p_sync_ack_out) ......................836
14.2.10.3Synchronization request out (p_sync_req_out) ............................................837
14.2.10.4Synchronization request acknowledge in (p_sync_ack_in) ..........................837
14.2.11Interrupt signals ..............................................................................................................837
14.2.11.1External input interrupt request (p_extint_b) ................................................837
14.2.11.2Critical input interrupt request (p_critint_b) .................................................838
14.2.11.3Non-maskable input interrupt request (p_nmi_b) .........................................838
14.2.11.4Interrupt pending (p_ipend) ..........................................................................838
14.2.11.5Autovector (p_avec_b) .................................................................................838
14.2.11.6Interrupt vector offset (p_voffset[0:15]) .......................................................838
14.2.11.7Interrupt vector acknowledge (p_iack) .........................................................839
14.2.11.8 Machine check (p_mcp_b) ............................................................................839
14.2.12External translation alteration signals .............................................................................839
14.2.12.1External PID enable (p_extpid_en) ...............................................................839
14.2.12.2External PID in (p_extpid[6:7]) ....................................................................839
14.2.13Timer facility signals ......................................................................................................840
14.2.13.1Timer disable (p_tbdisable) ..........................................................................840
14.2.13.2Timer external clock (p_tbclk) ......................................................................840
14.2.13.3Timer interrupt status (p_tbint) .....................................................................840
14.2.14Processor reservation signals ..........................................................................................840
14.2.14.1CPU reservation status (p_rsrv) ....................................................................840
14.2.14.2CPU reservation clear (p_rsrv_clr) ...............................................................840
14.2.15Miscellaneous processor signals .....................................................................................841
14.2.15.1CPU ID (p_cpuid[0:7]) .................................................................................841
14.2.15.2PID0 outputs (p_pid0[0:7]) ...........................................................................841
14.2.15.3PID0 update (p_pid0_updt) ..........................................................................841
14.2.15.4System version (p_sysvers[0:31]) .................................................................841
14.2.15.5Processor version (p_pvrin[16:31]) ..............................................................841
14.2.15.6HID1 system control (p_hid1_sysctl[0:7]) ...................................................842
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14.2.15.7Debug event outputs (p_devnt_out[0:7]) ......................................................842
14.2.16Processor state signals ....................................................................................................842
14.2.16.1Processor mode (p_mode[0:3]) .....................................................................842
14.2.16.2Processor execution pipeline status (p_pstat_pipe0[0:5], p_pstat_pipe1[0:5]) ..
.......................................................................................................................................842
14.2.16.3Branch prediction status (p_brstat[0:1]) .......................................................843
14.2.16.4Processor exception enable MSR values (p_msr_EE, p_msr_CE, p_msr_DE,
p_msr_ME) ...................................................................................................................844
14.2.16.5Processor return from interrupt (p_rfi, p_rfci, p_rfdi, p_rfmci) ...................844
14.2.16.6Processor machine check (p_mcp_out) ........................................................844
14.2.17Power management control signals ................................................................................844
14.2.17.1Processor waiting (p_waiting) ......................................................................844
14.2.17.2Processor halt request (p_halt) ......................................................................845
14.2.17.3Processor halted (p_halted) ...........................................................................845
14.2.17.4Processor stop request (p_stop) ....................................................................845
14.2.17.5Processor stopped (p_stopped) .....................................................................845
14.2.17.6Low-power mode signals (p_doze, p_nap, p_sleep) .....................................845
14.2.17.7Wakeup (p_wakeup) .....................................................................................845
14.2.18Performance monitor signals ..........................................................................................846
14.2.18.1Performance monitor event (p_pm_event) ...................................................846
14.2.18.2Performance monitor counter 0 overflow state (p_pmc0_ov) ......................846
14.2.18.3Performance monitor counter 1 overflow state (p_pmc1_ov) ......................846
14.2.18.4Performance monitor counter 2 overflow state (p_pmc2_ov) ......................846
14.2.18.5Performance monitor counter 3 overflow state (p_pmc3_ov) ......................846
14.2.18.6Performance monitor counter 3 qualifier inputs (p_pmc[0,1,2,3]_qual) ......846
14.2.19Debug event input signals ...............................................................................................846
14.2.19.1Unconditional debug event (p_ude) ..............................................................847
14.2.19.2External debug event 1 (p_devt1) .................................................................847
14.2.19.3External debug event 2 (p_devt2) .................................................................847
14.2.20Debug event output signals (p_devnt_out[0:7]) .............................................................847
14.2.21Debug/emulation (Nexus 1/ OnCE) support signals .......................................................847
14.2.21.1OnCE enable (jd_en_once) ...........................................................................848
14.2.21.2Debug session (jd_debug_b) .........................................................................848
14.2.21.3Debug request (jd_de_b) ...............................................................................848
14.2.21.4DE_b active high output enable (jd_de_en) .................................................849
14.2.21.5Processor clock on (jd_mclk_on) .................................................................849
14.2.21.6Watchpoint events (jd_watchpt[0:29]) ..........................................................849
14.2.22Development support (Nexus 3) signals .........................................................................849
14.2.23JTAG support signals ......................................................................................................850
14.2.23.1JTAG/OnCE serial input (j_tdi) ....................................................................850
14.2.23.2JTAG/OnCE serial clock (j_tclk) ..................................................................850
14.2.23.3JTAG/OnCE serial output (j_tdo) .................................................................850
14.2.23.4JTAG/OnCE test mode select (j_tms) ...........................................................850
14.2.23.5JTAG/OnCE test reset (j_trst_b) ...................................................................851
14.2.23.6Test-Logic-Reset (j_tst_log_rst) ...................................................................851
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14.2.23.7Run-Test/Idle (j_rti) ......................................................................................851
14.2.23.8Capture IR (j_capture_ir) ..............................................................................851
14.2.23.9Shift IR (j_shift_ir) .......................................................................................851
14.2.23.10Update IR (j_update_ir) ...............................................................................852
14.2.23.11Capture DR (j_capture_dr) ..........................................................................852
14.2.23.12Shift DR (j_shift_dr) ....................................................................................852
14.2.23.13Update DR w/write (j_update_gp_reg) .......................................................852
14.2.23.14Register select (j_gp_regsel) .......................................................................852
14.2.23.15Enable OnCE register select (j_en_once_regsel) ........................................852
14.2.23.16External Nexus register select (j_nexus_regsel) ..........................................853
14.2.23.17External LSRL register select (j_lsrl_regsel) ..............................................853
14.2.23.18Serial data (j_serial_data) ............................................................................853
14.2.23.19Key data in (j_key_in) .................................................................................854
14.2.24JTAG ID signals ..............................................................................................................854
14.2.24.1JTAG ID sequence (j_id_sequence[0:1]) ......................................................855
14.2.24.2JTAG ID sequence (j_id_sequence[2:9]) ......................................................855
14.2.24.3JTAG ID version (j_id_version[0:3]) ............................................................855
14.2.25Test signals ......................................................................................................................856
14.3 Timing diagrams ............................................................................................................................856
14.3.1 AHB clock enable and the internal HCLK .....................................................................856
14.3.2 Processor instruction/data transfers ................................................................................856
14.3.2.1 Basic read transfer cycles .............................................................................858
14.3.2.2 Read transfer with wait state .........................................................................859
14.3.2.3 Basic write transfer cycles ............................................................................860
14.3.2.4 Write transfer with wait states ......................................................................862
14.3.2.5 Read and write transfers ...............................................................................863
14.3.2.6 Misaligned accesses ......................................................................................867
14.3.2.7 Burst accesses ...............................................................................................870
14.3.2.8 Error termination operation ..........................................................................874
14.3.3 Memory synchronization control operation ....................................................................877
14.3.4 Cache coherency interface operation ..............................................................................880
14.3.4.1 Stop mode entry/exit and snoop ready signaling ..........................................884
14.3.5 Power management .........................................................................................................885
14.3.6 Interrupt Interface ...........................................................................................................886
14.3.7 Time base interface .........................................................................................................888
14.3.8 JTAG test interface .........................................................................................................889
Chapter 15
Internal Core Interfaces
15.1 Signal index ...................................................................................................................................891
15.2 Signal descriptions ........................................................................................................................896
15.2.1 Address and data buses ...................................................................................................896
15.2.1.1 Data address bus (p_d_addr[0:31]) ...............................................................896
15.2.1.2 Instruction address bus (p_i_addr[0:31]) ......................................................897
15.2.1.3 Data input data bus (p_d_data_in[0:63]) ......................................................897
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15.2.1.4 Instruction input data bus (p_i_data_in[0:63]) .............................................897
15.2.1.5 Data output data bus (p_d_data_out[0:63]) ..................................................897
15.2.2 Transfer attribute signals .................................................................................................897
15.2.2.1 Read/write (p_d_rw_b) .................................................................................897
15.2.2.2 Data transfer code (p_d_tc[0:1]) ...................................................................897
15.2.2.3 Instruction transfer code (p_i_tc[0:4]) ..........................................................897
15.2.2.4 Data transfer size (p_d_tsiz[0:2]) .................................................................899
15.2.2.5 Element size (p_elsiz[0:1]) ...........................................................................899
15.2.2.6 Instruction Transfer Size (p_i_tsiz[0:2]) .......................................................900
15.2.2.7 Data Transfer Type (p_d_ttype[0:5]) ............................................................900
15.2.2.8 Data sequential access (p_d_seq_b) .............................................................901
15.2.2.9 Instruction sequential access (p_i_seq_b) .....................................................901
15.2.2.10Misaligned access (p_d_misal_b) .................................................................901
15.2.2.11Block data transfer (p_d_bdt) .......................................................................901
15.2.2.12Error kill control (p_d_err_kill, p_i_err_kill) ...............................................901
15.2.3 Transfer control signals ...................................................................................................902
15.2.3.1 Halt ZLB (p_d_halt_zlb, p_i_halt_zlb) ........................................................902
15.2.3.2 Transfer request (p_d_treq_b, p_i_treq_b) ...................................................902
15.2.3.3 Transfer busy (p_d_tbusy[0:1]_b, p_i_tbusy[0:1]_b) ...................................902
15.2.3.4 Transfer abort (p_d_abort_b, p_i_abort_b) ...................................................902
15.2.3.5 Transfer acknowledge (p_d_ta_b, p_i_ta_b) ................................................903
15.2.3.6 Transfer error acknowledge (p_d_tea_b, p_i_tea_b) ....................................903
15.2.3.7 Translation miss (p_d_tmiss_b, p_i_tmiss_b) ..............................................903
15.2.3.8 Byte ordering error (p_d_boerr_b, p_i_boerr_b) ..........................................903
15.2.3.9 Alignment error (p_d_alignerr_b) ................................................................903
15.2.3.10Cache tag parity error (p_d_tag_perr_b, p_i_tag_perr_b) ............................903
15.2.3.11 Cache data parity error (p_d_data_perr_b, p_i_data_perr_b) .......................904
15.2.3.12External termination error (p_d_xte_b, p_i_xte_b) ......................................904
15.2.3.13Guarded termination status (p_d_ta_g) .........................................................904
15.2.3.14Cache-inhibited termination status (p_d_ta_ci) ............................................904
15.2.3.15Access physical address (p_[d,i]_ta_addr[0:31]) ..........................................904
15.2.3.16Termination error signaling and qualification ...............................................904
15.2.3.17Store exclusive failure (p_d_xfail_b) ............................................................905
15.2.3.18Read endian mode select (p_d_rdbigend_b, p_i_rdbigend_b) .....................906
15.2.3.19Write endian mode select (p_d_wrbigend_b) ...............................................906
15.2.3.20VLE mode select (p_rd_vle) .........................................................................906
15.2.4 Byte lane specification ....................................................................................................906
15.2.5 External SPR interface signals ........................................................................................929
15.2.5.1 SPR number (p_sprnum[0:9]) .......................................................................929
15.2.5.2 SPR read data (p_spr_in[0:31]) ....................................................................929
15.2.5.3 SPR write data (p_spr_out[0:31]) .................................................................929
15.2.5.4 SPR read control (p_rd_spr) .........................................................................929
15.2.5.5 SPR write control (p_wr_spr) .......................................................................929
15.2.6 Miscellaneous processor signals .....................................................................................929
15.2.6.1 PID0 outputs (p_pid0[0:7]) ...........................................................................929
e200z759n3 Core Reference Manual, Rev. 2
Freescale Semiconductor 21
15.2.6.2 PID0 update (p_pid0_updt) ..........................................................................929
15.2.7 Cache/MMU status signals .............................................................................................930
15.2.7.1 Cache enabled (p_d_cache_enabled, p_i_cache_enabled) ...........................930
15.2.7.2 Cache/MMU busy (p_d_cmbusy, p_i_cmbusy) ...........................................930
15.2.7.3 Cache set CUL (p_d_set_cul, p_i_set_cul) ...................................................930
15.2.7.4 User cache lock DSI control (p_ucl_dsi) ......................................................930
15.2.7.5 Cache push parity error (p_d_cp_perr) .........................................................930
15.2.7.6 Cache push address (p_d_push_addr[0:31]) .................................................930
15.2.7.7 Bus write error (p_d_bus_wrerr) ..................................................................931
15.2.7.8 Bus write error address (p_d_bus_wrerr_addr[0:31]) ..................................931
15.2.7.9 Cache linefill status (p_d_lf_status[0:3], p_i_lf_status[0:3]) .......................931
15.2.7.10Linefill status address (p_d_lf_addr[0:31], p_i_lf_addr[0:31]) ....................931
15.2.7.11Debug mode MMU disable (p_d_dmdis, p_i_dmdis) ..................................931
15.2.7.12Debug mode MMU ‘VLE’ attribute (p_dbg_vle) .........................................931
15.2.7.13Debug mode MMU ‘W’ attribute (p_d_dbg_w) ...........................................932
15.2.7.14Debug mode MMU ‘I’ attribute (p_d_dbg_i, p_i_dbg_i) .............................932
15.2.7.15Debug mode MMU ‘M’ attribute (p_d_dbg_m, p_i_dbg_m) ......................932
15.2.7.16Debug mode MMU ‘G’ attribute (p_d_dbg_g) ............................................932
15.2.7.17Debug mode MMU ‘E’ attribute (p_d_dbg_e, p_i_dbg_e) ..........................932
15.2.8 EFPU interface signals ....................................................................................................932
15.2.9 Test signals ......................................................................................................................932
15.3 Timing diagrams ............................................................................................................................932
15.3.1 Processor instruction/data transfers ................................................................................932
15.3.1.1 Basic read transfer cycles .............................................................................934
15.3.1.2 Read transfer with wait states .......................................................................936
15.3.1.3 Basic write transfer cycles ............................................................................938
15.3.1.4 Write transfer with wait states ......................................................................940
15.3.1.5 Read and write transfers ...............................................................................941
15.3.1.6 Misaligned accesses ......................................................................................944
15.3.1.7 Abort operation .............................................................................................949
15.3.1.8 Error termination and abort operation ..........................................................950
15.3.2 SPR interface operation ..................................................................................................953
Appendix A
Register Summary
Appendix B
Revision History
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