Table of Contents
6.9.1. IO3Standard Mode....................................................................................... 6-21
6.9.2. Watchdog Mode............................................................................................ 6-21
6.9.3. IO3Timing Mode .......................................................................................... 6-21
6.9.3.1. On IO3Direction = Input:...................................................................... 6-22
6.9.3.2. IO3Direction = Output: ......................................................................... 6-22
6.9.4. IO3TimerInterrupt Mode ............................................................................. 6-22
6.10. B
US SIGNALS...................................................................................................... 6-23
6.10.1. Bus Signals for the E1-32XS Processor ..................................................... 6-23
6.10.2. Bus Signals for the E1-16XS Processor ..................................................... 6-24
6.10.3. Bus Signal Description............................................................................... 6-25
6.11. B
US CYCLES....................................................................................................... 6-30
6.11.1. SRAM and ROM Accesses.......................................................................... 6-30
6.11.1.1. SRAM and ROM Single-Cycle Read Access ..................................... 6-30
6.11.1.2. SRAM Single-Cycle Write Access ..................................................... 6-30
6.11.1.3. SRAM and ROM Multi-Cycle Read Access....................................... 6-31
6.11.1.4. SRAM Multi-Cycle Write Access....................................................... 6-31
6.11.2. MEM2 Read Access with WAIT Pin........................................................... 6-32
6.11.3. I/O Read Access ......................................................................................... 6-33
6.11.4. I/O Read Access with WAIT Pin................................................................. 6-34
6.11.5. I/O Write Access......................................................................................... 6-35
6.11.6. DRAM......................................................................................................... 6-36
6.11.6.1. Fast Page Mode DRAM Access.......................................................... 6-36
6.11.6.2. EDO DRAM Single-Cycle Access ..................................................... 6-37
6.11.6.3. EDO DRAM Multi-Cycle Access....................................................... 6-38
6.11.6.4. Fast Page Mode or EDO DRAM Refresh ........................................... 6-39
6.11.6.5. SDRAM Access .................................................................................. 6-40
6.12. DC C
HARACTERISTICS ....................................................................................... 6-41
6.12.1. Absolute Maximum Ratings........................................................................ 6-41
6.12.2. D.C. Parameters......................................................................................... 6-41
6.13. AC C
HARACTERISTICS ....................................................................................... 6-42
6.13.1. Processor Clock and CLKIN...................................................................... 6-42
6.13.2. GRANT# response time .............................................................................. 6-42
7. MECHANICAL DATA ............................................................................................. 7-1
7.1.
HYPERSTONE E1-32XS, 144-PIN LQFP PACKAGE.................................................. 7-1
7.1.1. Pin Configuration - View from Top Side........................................................ 7-1
7.1.2. Pin Cross Reference by Pin Name ................................................................. 7-2
7.1.3. Pin Cross Reference by Location................................................................... 7-3
7.2. HYPERSTONE E1-16XS, 100-PIN LQFP PACKAGE.................................................. 7-4
7.2.1. Pin Configuration - View from Top Side........................................................ 7-4
7.2.2. Pin Cross Reference by Pin Name ................................................................. 7-5
7.2.3. Pin Cross Reference by Location................................................................... 7-6
7.3.
HYPERSTONE E1-32XSB, 144-PIN TFBGA PACKAGE............................................ 7-7
7.3.1. Pin Configuration – View from Top Side....................................................... 7-7
7.3.2. Pin Cross Reference by Pin Name ................................................................. 7-8
7.3.3. Pin Cross Rreference by Location ................................................................. 7-9
7.4.
HYPERSTONE E1-16XSB, 100-PIN TFBGA PACKAGE.......................................... 7-10
7.4.1. Pin Configuration – View from Top Side..................................................... 7-10
7.4.2. Pin Cross Reference by Pin Name ............................................................... 7-11
7.4.3. Pin Cross Rreference by Location ............................................................... 7-12
7.5. P
ACKAGE DIMENSIONS......................................................................................... 7-13