Loader) from the QSPI flash and transfer it to the HPS on-chip RAM, and releases the
HPS reset to let the HPS start using the FSBL hardware handoff file to setup the clocks,
HPS dedicated I/Os, and peripherals.
The FSBL then loads the SSBL(Second-Stage Boot Loader) from the Micro SD Card
into HPS SDRAM and passes the control to the SSBL. The SSBL enables more
advanced peripherals and loads OS into SDRAM.
Finally, the OS boots and applications are scheduled for runtime launch.
JTAG Programming
The JTAG interface of the Apollo Agilex is mainly implemented by the USB Blaster II
circuit on the board. For programming by on-board USB Blaster II, the following
procedures show how to download a configuration bit stream into the Agilex SoC
FPGA:
Make sure that power is provided to the FPGA board
Connect your PC to the FPGA board using a micro-USB cable and make
sure the USB Blaster II driver is installed on the PC.
Launch Quartus Prime programmer and make sure the USB Blaster II is
detected.
In Quartus Prime Programmer, add the configuration bit stream file (.sof),
check the associated “Program/Configure” item, and click “Start” to start
FPGA programming.
2.2 Setup and Status Components
This section will introduce the use of the switch for setup on the Apollo Agilex board,
as well as a description of the various status LEDs.
Status LED
The FPGA development board includes board-specific status LEDs to indicate board
status. Please refer to Table 2-1 for the description of the LED indicators. Figure 2-4
shows the location of all these status LED.