NXP JN5189/88 (T) User guide

Type
User guide
JN5189(T)/JN5188(T)JN5189(T)/JN5188(T) User Manual
JN5189(T)/JN5188(T) User
Manual
UM11138
Rev. 1.4 — June 2020 User manual
Document information
Info Content
Keywords Arm Cortex-M4, microcontroller, Zigbee, Thread
Abstract JN5189 User Manual
JN5189 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 1.4 — June 2020 2 of 350
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
NXP Semiconductors
UM11138
JN5189(T)/JN5188(T) User Manual
Revision history
Rev Date Description
1.4 202006
Added to support Thread as well as Zigbee across the whole book.
Corrected the Tag of JN5189T/JN5188T to be NT3H2211.
Updated SPIFI feature in the Section 1.2.1 “Microcontroller features”.
Updated to “1.9 V to 3.6 V supply voltage” in the Section 1.2.2 “Radio features”.
Updated Table 3 “Pin descriptions” to correct typos and make the descriptions aligned with the
Figure 3 “Pinout diagram”.
Updated the Range of MAIN_CLK to be “12-48 MHz” in the Table 56 “Base clock sources for DMIC
interface peripheral”.
Updated SPIFI features in the Section 34.2 “Features”, the Remark in the Table 64 “Available pins
and configuration registers”, and Section 34.8.4 “SPIFI intermediate data register”, Section 34.9.2
“Software requirements and capabilities”.
Updated the ISP usage restrictions in the Section 38.8 “Usage restrictions”.
Updated the Section 41.7.6.2 “Memory mapping”, descriptions in the Section 41.9 “Antenna
Diversity”.
Updated Section 42.5 “General description”.
Updated to reserve the CT32B_IR[7:6].
1.3 202002 Initial public release
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1.1 Introduction
The JN5189(T) and JN5188(T) (called JN5189(T)/JN5188(T) throughout this document)
are ultra-low power, high performance Arm
®
Cortex
®
-M4 based wireless microcontrollers
supporting Zigbee 3.0 and Thread networking stacks to facilitate the development of
home automation, smart lighting and wireless sensor network applications.
The JN5189(T)/JN5188(T) includes a 2.4 GHz IEEE 802.15.4 and a comprehensive mix
of analog and digital peripherals. Ultra-low current consumption in radio receive and radio
transmit modes allows use of coin cell batteries.
JN5189(T) has 640 KB embedded Flash, 152 KB RAM and 128 KB ROM memory. The
embedded flash can support Over The Air (OTA) code download to applications. The
devices include 10-channel PWM, two timers, one RTC/alarm timer, a Windowed
Watchdog Timer (WWDT), two USARTs, two SPI interfaces, two I
2
C interfaces, a DMIC
subsystem with dual-channel PDM microphone interface with voice activity detector, one
12-bit ADC, temperature sensor and comparator.
The JN5189T/JN5188T variant has an internal NTAG I
2
C plus NFC tag and connections
for the external NFC antenna. The tag is an NXP device NT3H2211.
The JN5188 variant has the same functionality as the JN5189 except for reduced memory
sizes of 320 KB embedded Flash, 88 KB RAM. The JN5188T variant is that it has the
functionality of the JN5188 with the addition of an embedded NTAG I
2
C plus NFC tag.
The Arm Cortex-M4 is a 32-bit core that offers system enhancements such as low-power
consumption and enhanced debug features. The Arm Cortex-M4 CPU, operating at up to
48 MHz, incorporates a 3-stage pipeline, uses a Harvard architecture with separate local
instruction and data buses as well as a third bus for peripherals, and includes an internal
prefetch unit that supports speculative branching. The Arm Cortex-M4 supports
single-cycle digital signal processing and SIMD instructions. Debug is supported using the
Serial Wire Debug.
Refer to the data sheet for complete details on specific products and configurations.
1.2 Features
1.2.1 Microcontroller features
Application CPU, Arm Cortex-M4 CPU:
Arm Cortex-M4 processor, running at a frequency of up to 48 MHz.
Arm built-in Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit (MPU)
Non-maskable Interrupt (NMI) with a selection of sources
Serial Wire Debug (SWD) with 8 breakpoints and 4 watchpoints
System tick timer
UM11138
Chapter 1: Introductory Information
Rev. 1.4 — June 2020 User manual
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Chapter 1: Introductory Information
Includes Serial Wire Output for enhanced debug capabilities.
On-Chip memory:
640 KB flash (320 KB for JN5188)
152 KB SRAM (88 KB for JN5188)
128 KB ROM
12 MHz to 48 MHz system clock speed for low-power
2 x I
2
C-bus interface, operate as either master or slave
10 x PWM
2 x Low-power timers
2 x USART, one with flow control
2 x SPI-bus, master or slave
1 x PDM digital audio interface with a hardware based voice activity detector to
reduce power consumption in voice applications. Support for dual-channel
microphone interface, flexible decimators, 16 entry FIFOs and optional DC blocking
19-channel DMA engine for efficient data transfer between peripherals and SRAM, or
SRAM to SRAM. DMA can operate with fixed or incrementing addresses. Operations
can be chained together to provide complex functionality with low CPU overhead
Up to four GPIOs can be selected as pin interrupts (PINT), triggered by rising, falling
or both input edges
Two GPIO grouped interrupts (GINT) enable an interrupt based on a logical
(AND/OR) combination of input states.
32-bit Real Time clock (RTC) with 1 s resolution. A timer in the RTC can be used to
wake from Sleep, Deep-sleep and Power-down, with 1 ms resolution
Voltage Brown Out with 8 programmable thresholds
8-input 12-bit ADC, 190 kS/sec. HW support for continuous operation or single
conversions, single or multiple inputs can be sampled within a sequence. DMA
operation can be linked to achieve low overhead operation.
1 x analog comparator
Battery voltage measurement
Temperature sensor
Watchdog timer and POR
Standby power controller
Up to 22 Digital IOs (DIO)
1 x Quad SPIFI for reading or writing to external flash device
NTAG NFC Forum Type 2 on JN5189T and JN5188T only
Random Number Generator engine
AES engine
Hash hardware accelerator
EFuse :
128-bit random AES key
configuration modes
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Chapter 1: Introductory Information
Trimming
1.2.2 Radio features
2.4 GHz IEEE 802.15.4 compliant
Receive current 4.3 mA
IEEE 802.15.4 receiver sensitivity -100 dBm
Improved co-existence with WiFi
Flexible output power up to 11 dBm, programmable with 46 dB range
Transmit power +10 dBm current 20.28 mA
Transmit power +3 dBm current 9.44 mA
Transmit power 0 dBm current 7.36 mA
1.9 V to 3.6 V supply voltage
32 MHz XTAL cell with internal capacitors, able with suitable external XTAL, to meet
the required accuracy for radio operation over the operating conditions
Antenna Diversity control
Integrated RF balun
Integrated ultra Low-power sleep oscillator
Deep Power-down current 350 nA (with wake-up from IO)
128-bit or 256-bit AES security processor
MAC accelerator with packet formatting, CRCs, address check, auto-acks, timers
1.2.3 Low-power features
Sleep mode supported, CPU in low-power state waiting for interrupt
Deep-sleep mode supported, CPU in low-power state waiting for interrupt, but extra
functionality disabled or in low-power state compared to sleep mode
Power Down mode, main functionality powered down, wakeup possible from IOs,
wakeup possible from some peripherals (I
2
C, USART, SPI) in a limited function mode
and low-power timers
Deep power down, very low-power state with option of reset triggered by IOs, 350 nA
41-bit and 28-bit Low power timers can run in power down mode, clocked by 32 kHz
FRO or 32 kHz XTAL. Timers can run for over one year or 2 days
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Chapter 1: Introductory Information
1.3 Block diagram
1.4 Architectural overview
The Arm Cortex-M4 includes three AHB-Lite buses, one system bus and the I-code and
D-code buses. One bus is dedicated for instruction fetch (I-code), and one bus is
dedicated for data access (D-code). The use of two core buses allows for simultaneous
operations if concurrent operations target different devices.
A multi-layer AHB matrix connects the CPU buses and other bus masters to peripherals in
a flexible manner that optimizes performance by allowing peripherals on different slaves
ports of the matrix to be accessed simultaneously by different bus masters. More
information on the multilayer matrix can be found in
Section 2.1.3 “AHB multilayer matrix”.
Connections in the multilayer matrix are shown in
Figure 1. Note that while the AHB bus
itself supports word, halfword, and byte accesses, not all AHB peripherals need or provide
that support.
APB peripherals are connected to the AHB matrix via two APB buses using separate
slave ports from the multilayer AHB matrix. This allows for better performance by reducing
collisions between the CPU and the DMA controller, and also for peripherals on the
asynchronous bridge to have a fixed clock that does not track the system clock. Note that
APB, by definition, does not directly support byte or halfword accesses.
Fig 1. Chip block diagram
Master
Slave
pmu_top
Analog
Comparator
ADC
32 kHz
XTAL
Oscillator
Temperature
Sensor
32 kHz
Free Running
Oscillator
192 MHz
Free Running
Oscillator
Power
On
Reset
Brown Out
Detectors
DCDC
Converter
1 MHz
Free Running
Oscillator
core_digital
AHB Multi-Layer Matrix
APB Bridge 0
ARM
Cortex-M4
with MPU
Quad
SPIFI
MODEM
System
APB Bridge 1
FLASH
640K
(1 * 640K)
FLASH
Functional
Muxes I/Os
Func
MUX
0
Func
MUX
1
Func
MUX
2
Func
MUX
21
Func
MUX
20
Func
MUX
...
AES
256
ADC
Controller
Debug
Access
Port
DMA
Controller
(19channels)
DMIC
USART 0 SPI 0
GPIO
(22I/Os)
Power
Management
Controller
(PMC)
Watchdog
Timer
Pin
Interrupt
&
Pattern
Matching
USART 1
SPI 1
I2C 1
ISO7816
PWM
(10 channels)
Peripheral
Input Mux
Infra Red
Random
Number
Generator
Async
System
Config.
CTimers
0/1
GPIO
Global
Interrupt
Sync.
System
Config.
RTC
I/O
Config.
Wake-up
Timers 0/1
Sleep
Config.
Reset
Controller
Clock
Controller
Analog
Interrupt
Controller
Zigbee/
Thread
MAC
MODEM
AHB
Master
Radio
Controller
RFP
Zigbee/
Thread
MODEM
Flash
Controller
SRAM
88 K
(2*4K + 2*8K
+ 4*16K)
SRAM 0
SRAM
Controller
SRAM
64 K
(4 * 16K)
SRAM 1
SRAM
Controller
ROM
128 K
(1*128K)
ROM
Code
Patch
radio_top
32 MHz
XTAL
Oscillator
Radio
LDOs
Band Gap
(Bias)
Hash
(SHA-1,
SHA-2 256)
I2C 0
Analog Mixed SignalDigital Units
System Control Bus
(AMBA AHB/APB)
ROM, RAM, FLASH
I2C 2
(NTAG
control)
eFUSE
1K
(64 * 16)
OTP
OTP
Controller
Interface
Key:
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Chapter 1: Introductory Information
The multi-layer has several master interfaces and slave interfaces. The following table
shows which slaves the master interfaces are able to access; indicated with a 'x'. Where a
block has '-REG' in the name, this shows that it is the register interface of the block.
SPIFI-MEM is the direct memory access function of the block and not the register
interface.
1.5 Arm Cortex-M4 processor
The Cortex-M4 is a general purpose 32-bit microprocessor, which offers high performance
and very low-power consumption. The Cortex-M4 offers a Thumb-2 instruction set, low
interrupt latency, interruptible/continuable multiple load and store instructions, automatic
state save and restore for interrupts, tightly integrated interrupt controller, and multiple
core buses capable of simultaneous accesses.
A 3-stage pipeline is employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
Information about Cortex-M4 configuration options can be found in
Chapter 43 “Arm
Cortex-M4 Appendix”.
Table 1. AHB master interface accessibility to the slaves
AHB slave AHB master
CPU DMA HASH MODEM
I-code D-code System
Slave port 0 Flash x x x x
Slave port 1 ROM x x x
Slave port 2 SRAM0 x x x x x
Slave port 3 SRAM1 x x x x x
Slave port 4 SPIFI-MEM x x
Slave port 5 APB bridge 0 x x
Slave port 6 APB bridge 1 x
Slave port 7 SPIFI-REG x x
GPIO x x
DMA-REG x x
AES x x
ADC x x
DMIC x x
USART0 x x
USART1 x x
SPI0 x x
SPI1 x x
HASH x x
Slave port 8 Zigbee/Thread MODEM x x
Zigbee/Thread MAC x x
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2.1 General description
The JN5189(T)/JN5188(T) incorporates several distinct memory regions. Figure 2 shows
the overall map of the entire address space from the user program viewpoint following
reset.
The APB peripheral area (detailed in
Figure 2) is divided into fixed 4 KB slots to simplify
addressing.
The registers incorporated into the CPU, such as NVIC, SysTick, and sleep mode control,
are located on the private peripheral bus.
2.1.1 Main SRAM
The main SRAM is composed of 152 KB of on-chip static RAM memory. The SRAM is
accessed through two controllers SRAM-CTRL0 and SRAM-CTRL1. SRAM-CTRL0 gives
access to the first 88 KB and SRAM-CTRL1 gives access to the remaining 64 KB. In a
JN5188 device, SRAM-CTRL1 is held in reset to prevent access to this memory. The
memory is contiguous within the two separate regions but not contiguous from
SRAM-CTRL0 to SRAM-CTRL1. Each SRAM has a separate clock control and power
switch.
2.1.1.1 SRAM usage notes
The SRAM controllers, SRAM-CTRL0 and SRAM-CTRL1, are placed on different AHB
matrix ports. This allows user programs to potentially obtain better performance by
dividing RAM usage among the ports. For example, simultaneous access to SRAM0 by
the CPU and SRAM1 by the system DMA controller does not result in any bus stalls for
either master.
Generally, data being communicated via peripherals will be accessed by the CPU at some
point, even when peripheral data is mainly being transferred via DMA. So, in order to
minimizing data read/write stalls, data buffers may be placed in RAMs on different AHB
matrix ports. For instance, if DMA is writing to one buffer on a specific AHB matrix port
while the CPU is reading data from a buffer on a different AHB matrix port, there is no stall
for either the CPU or the DMA. Sequences of data from the same peripheral could be
alternated between RAM on each port. This could be helpful if DMA fills or empties a RAM
buffer, then signals the CPU before proceeding on to a second buffer. The CPU would
then tend to access the data while the DMA is using the other RAM.
UM11138
Chapter 2: Memory Map
Rev. 1.4 — June 2020 User manual
Table 2. SRAM configuration
SRAM Controller SRAM-CTRL0 SRAM-CTRL1
(total main SRAM = up to 152 KB)
Size 88 KB Up to 64 KB
Address range 0x0400 0000 to 0x0401 5FFF 0x0402 0000 to 0x0402 FFFF
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Chapter 2: Memory Map
2.1.2 Memory mapping
The overall memory map and also details of the APB peripheral mapping are shown in
Figure 2 “Main memory map”.
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Chapter 2: Memory Map
1) The private peripheral bus includes CPU peripherals such as the NVIC, SysTick, and the core control registers.
2) The total size of flash and SRAM is part dependent, see the ordering information in the specific device data sheet for details.
3) Memory region 0x00000000 to 0x000001FF can be mapped to flash, as shown here, or ROM or RAM depending upon the
Vector Table Remapping setting.
Fig 2. Main memory map
FLASH Memory
Reserved
(Do not access)
0x0000_0000
0x0301_FFFF
0x4000_0000
640 KBytes
APB Bridge 0
(Synchronous)
0xFFFF_FFFF
General Purpose I/O
Synchronous System
Configuration
ROM
0x0009_FFFF
0x0300_0000
Main Memory Map (AHB)
APB Bridge 0 Memory Map
32-bit Words
32-bit Words
Reserved
(Do not access)
SRAM-CTRL0
(2*4KB, 2*8KB, 4*16KB)
0x0400_0000
0x0401_5FFF
Reserved
Quad SPIFI
(Memory-Mapped Space)
0x1000_0000
0x103F_FFFF
Reserved
Reserved
(Do not access)
0x4001_FFFF
0x4008_0000
0x4008_3FFF
SPIFI Registers
DMA Controller
AES-256
Reserved
(Do not access)
Private Peripheral
Bus (Internal)
Private Peripheral
Bus (External)
Reserved
(Do not access)
0x4008_4FFF
0x4008_5FFF
0x4008_6FFF
0x4008_4000
0x4008_5000
0x4008_6000
0xE003_FFFF
0xE00F_FFFF
0xE004_0000
0xE000_0000
128 KBytes
88 KBytes
4 MBytes
4 KBytes
768 KBytes
16 KBytes
4 KBytes
128 KBytes
4 KBytes
0x4000_0000
Reserved (do not
access)
4 KBytes
0x4000_1000
Reserved (do not
access)
4 KBytes
0x4000_2000
I2C 0
4 KBytes
0x4000_3000
I2C 1
4 KBytes
0x4000_4000
I2C 2
4 KBytes
0x4000_5000
ISO7816
4 KBytes
0x4000_6000
IR Modulator
4 KBytes
0x4000_7000
Code Patch
Module
4 KBytes
0x4000_8000
Flash Controller
4 KBytes
0x4000_9000
WWDT
4 KBytes
0x4000_A000
RTC
4 KBytes
0x4000_B000
PWM
4 KBytes
0x4000_C000
4 KBytes
0x4000_D000
Random Number
Generator
4 KBytes
0x4000_E000
INPUT MUX
4 KBytes
0x4000_F000
IO CONFIG
(IOCON)
4 KBytes
0x4001_0000
Interrupt (PINT)
4 KBytes
0x4001_1000
CTIMER 0
4 KBytes
0x4001_2000
RFP MODEM
4 KBytes
0x4001_3000
Reserved
(Do not access)
4 KBytes
0x4001_4000
Reserved
(Do not access)
0x4001_5000
40 KBytes
GPIO Group
Interrupt (GINT0)
APB Bridge 1
(Asynchronous)
0x4002_0000
0x4003_FFFF
CTIMER 1
APB Bridge 1 Memory Map
4 KBytes
0x4002_0000
Reserved
(Do not access)
116 KBytes
0x4002_1000
SRAM 0
(16 KB)
SRAMs Memory Map
0x0400_0000
SRAM 1
(16 KB)
0x0400_4000
SRAM 2
(16 KB)
0x0400_8000
SRAM 5
(8 KB)
0x0400_C000
0x0401_4000
128 KBytes
0x4003_FFFF
0x4002_0FFF
0x4001_FFFF
32-bit Words
PMC
4 Kbytes
Asynchronous
System Configuration
0x4002_1FFF
0x4002_2000
0x4002_2FFF
0x4002_3000
4 KBytes
4 KBytes
SRAM 6
(4 KB)
SRAM 7
(4 KB)
SRAM 8
(16 KB)
SRAM 9
(16 KB)
0x0401_5000
0x0402_0000
0x0402_4000
0x0401_5FFF
0x0402_3FFF
0x0401_4FFF
0x0401_3FFF
0x0400_BFFF
0x0400_7FFF
0x0400_3FFF
0x0402_7FFF
Reserved
(Do not access)
Zigbee/Thread MODEM
Zigbee/Thread MAC
0x400A_0000
0x400B_0000
0x400B_1000
0x400A_FFFF
0x400B_0FFF
0x400B_1FFF
4 Kbytes
4 Kbytes
64 Kbytes
Reserved
(Do not access)
Reserved
(Do not access)
4 Kbytes
4 Kbytes
0x4008_8FFF
0x4008_7FFF
0x4008_7000
0x4008_8000
Reserved
(Do not access)
0x4008_9000
ADC
4 Kbytes
0x4008_9FFF
DMIC
4 Kbytes
0x4008_A000
0x4008_AFFF
USART 0
USART 1
4 Kbytes
4 Kbytes
0x4008_CFFF
0x4008_BFFF
0x4008_B000
0x4008_C000
0x4008_D000
SPI 0
4 Kbytes
0x4008_DFFF
SPI 1
4 Kbytes
0x4008_E000
0x4008_EFFF
SRAM 3
(16 KB)
SRAM 4
(8 KB)
0x0400_FFFF
0x0401_0000
0x0401_2000
0x0401_1FFF
SRAM-CTRL1
(4*16KB)
64 KBytes
0x0402_0000
0x0402_FFFF
Reserved
SRAM 10
(16 KB)
SRAM 11
(16 KB)
0x0402_8000
0x0402_FFFF
0x0402_C000
0x0402_BFFF
Reserved
(Do not access)
4 KBytes
0x4001_6000
Hash
4 Kbytes
0x4008_F000
0x4008_FFFF
GPIO Pattern
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Chapter 2: Memory Map
2.1.3 AHB multilayer matrix
The JN5189(T)/JN5188(T) uses a multi-layer AHB matrix to connect the CPU buses and
other bus masters to peripherals in a flexible manner that optimizes performance by
allowing peripherals that are on different slave ports of the matrix to be accessed
simultaneously by different bus masters.
Figure 2 and shows details of the potential
matrix connections.
2.1.4 Memory Protection Unit (MPU)
The Cortex-M4 processor has a memory protection unit (MPU) that provides fine grain
memory control, enabling applications to implement security privilege levels, separating
code, data and stack on a task-by-task basis. Such requirements are critical in many
embedded applications.
The MPU register interface is located on the private peripheral bus and is described in
detail in
Ref. 1 “Cortex-M4 TRM”.
2.1.5 Vector table remapping
The Cortex boot address is 0x00000000. The memory map in Figure 2 shows flash at this
address. However, the first 512 bytes in the memory map are treated specially to give
flexibility to the location of the vector table. This region will be referred to here as the
Vector Table Region.
The MEMORYREMAP MAP field is used to indicate if this Vector Table Region is located
in ROM, Flash or RAM. Depending upon this setting, cortex address 0x00000000 to
0x000001FF will either access the bottom of the ROM, the bottom of the Flash or the
bottom of SRAM0.
The default / reset condition is to use ROM code so that a known boot sequence is
followed. Typically, during the boot sequence, this setting is changed so that the vector
table region is in Flash. This allows application specific interrupt vectors to be used.
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User manual Rev. 1.4 — June 2020 12 of 350
3.1 How to read this chapter
JN5189(T)/JN5188(T) package is a HVQFN40 (6x6 mm). The pinout and IO cells are
consistent across all product types except for the NTAG antenna connections.
There are some functional differences between the IO cells used for different digital pins
and these are presented in this chapter.
3.2 Pinout diagram
UM11138
Chapter 3: Pin and Pad Descriptions
Rev. 1.4 — June 2020 User manual
Fig 3. Pinout diagram
SS(RF)
SS(RF)
RSTN
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Chapter 3: Pin and Pad Descriptions
3.3 Pinout signaling descriptions
Table 3. Pin descriptions
Symbol Pin Type Default at reset Description
XTAL_P 1 System crystal oscillator 32 MHz
XTAL_N 2 System crystal oscillator 32 MHz
PIO0 3 IO GPIO0
[1]
GPIO0 — General Purpose digital Input/Output 0
USART0_SCK — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - synchronous clock
USART1_TXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 1 - transmit data output
PWM0 — Pulse Width Modulator output 0
SPI1_SCK — Serial Peripheral Interface-bus 1 clock input/output
PDM0_DATAPulse Density Modulation Data input from digital
microphone (channel 0)
PIO1 4 IO GPIO1
[1]
GPIO1 — General Purpose digital Input/Output 1
USART1_RXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 1 - receive data input
PWM1 — Pulse Width Modulator output 1
SPI1_MISO — Serial Peripheral Interface-bus 1 master data input
PDM0_CLK — Pulse Density Modulation Clock output to digital
microphone (channel 0)
PIO2 5 IO GPIO2
[1]
GPIO2 — General Purpose digital Input/Output 2
SPI0_SCK — Serial Peripheral Interface-bus 0 clock input/output
PWM2 — Pulse Width Modulator output 2
SPI1_MOSI — Serial Peripheral Interface-bus 1 master output slave
input
USART0_RXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - receive data input
ISO7816_RST — RST signal, output, for ISO7816 interface
MCLK — External clock, can be provided to DMIC IP
PIO3 6 IO GPIO3
[1]
GPIO3 — General Purpose digital Input/Output 3
SPI0_MISO — Serial Peripheral Interface-bus 0 master input
PWM3 — Pulse Width Modulator output 3
SPI1_SSELN0 — Serial Peripheral Interface-bus 1 slave select not 0
USART0_TXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - transmit data output
ISO7816_CLK — Clock output for ISO7816 interface
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Chapter 3: Pin and Pad Descriptions
PIO4 7 IO GPIO4
[1][2]
GPIO4 — General Purpose digital Input/Output 4
SPI0_MOSI — Serial Peripheral Interface-bus 0 master output slave
input
PWM4 — Pulse Width Modulator output 4
SPI1_SSELN1 — Serial Peripheral Interface-bus 1 slave select not 1
USART0_CTS — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - Clear To Send input
ISO7816_IO — IO of ISO7816 interface
RFTX — Radio Transmit Control Output
ISP_SEL — In-System Programming Mode Selection
PIO5/ISP_ENT
RY
8 IO GPIO5/ISP_EN
TRY
[1][3]
GPIO5/ISP_ENTRY — General Purpose digital Input/Output 5;
In-System Programming Entry
SPI0_SSELN — Serial Peripheral Interface-bus 0 slave select not
SPI1_MISO — Serial Peripheral Interface-bus 1 master data input
SPI1_SSELN2 — Serial Peripheral Interface-bus 1 slave select not 2
USART0_RTS — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - Request To Send output
RFRX — Radio Receiver Control Output
PIO6 9 IO GPIO6
[1]
GPIO6 — General Purpose digital Input/Output 6
USART0_RTS — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - Request to Send output
CT32B1_MAT0 — 32-bit CT32B1 match output 0
PWM6 — Pulse Width Modulator output 6
I2C1_SCL — I
2
C-bus 1 master/slave SCL input/output
USART1_TXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 1 - transmit data output
ADE — Antenna Diversity Even output
SPI0_SCK — Serial Peripheral Interface 0- synchronous clock
PIO7 10 IO GPIO7
[1]
GPIO7 — General Purpose digital Input/Output 7
USART0_CTS — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - Clear to Send input
CT32B1_MAT1 — 32-bit CT32B1 match output 1
PWM7 — Pulse Width Modulator output 7
I2C1_SDAI
2
C-bus 1 master/slave SDA input/output
USART1_RXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 1 - receive data input
ADO — Antenna Diversity Odd Output
SPI0_MISO — Serial Peripheral Interface-bus 0 master input
Table 3. Pin descriptions
Symbol Pin Type Default at reset Description
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Chapter 3: Pin and Pad Descriptions
PIO8/TXD0 11 IO GPIO8
[1][4]
GPIO8 — General Purpose digital Input/Output 8
USART0_TXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - transmit data output
CT32B0_MAT0 — 32-bit CT32B0 match output 0
PWM8 — Pulse Width Modulator output 8
ANA_COMP_OUT — Analog Comparator digital output
PDM1_DATAPulse Density Modulation Data input from digital
microphone (channel 1)
SPI0_MOSI — Serial Peripheral Interface-bus 0 master output slave
input
RFTX — Radio Transmit Control Output
PIO9/RXD0 12 IO GPIO9
[1][5]
GPIO9 — General Purpose digital Input/Output 9
USART0_RXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - receive data input
CT32B1_CAP1 — 32-bit CT32B1 capture input 1
PWM9 — Pulse Width Modulator output 9
USART1_SCK — Universal Synchronous/Asynchronous
Receiver/Transmitter 1 - synchronous clock
PDM1_CLK — Pulse Density Modulation Clock output
to digital microphone (channel 1)
SPI0_SSELN — Serial Peripheral Interface-bus 0 slave select not
ADO — Antenna Diversity Odd Output
PIO10 13 IO GPIO10
[1]
GPIO10 — General Purpose digital Input/Output 10
CT32B0_CAP0 — 32-bit CT32B0 capture input 0
USART1_TXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 1 - transmit data output
RFTX — Radio Transmit Control Output
I2C0_SCL — I
2
C-bus 0 master/slave SCL input/output (open drain)
SPI0_SCK — Serial Peripheral Interface-bus 0 clock input/output
PDM0_DATAPulse Density Modulation Data input from digital
microphone (channel 0)
PIO11 14 IO GPIO11
[1]
GPIO11 — General Purpose digital Input/Output 11
CT32B1_CAP0 — 32-bit CT32B1 capture input 0
USART1_RXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 1 - receive data input
RFRX — Radio Receiver Control Output
I2C0_SDAI
2
C-bus 0 master/slave SDA input/output (open drain)
SPI0_MISO — Serial Peripheral Interface-bus 0 master input slave
output
PDM0_CLK — Pulse Density Modulation Clock output to digital
microphone (channel 0)
Table 3. Pin descriptions
Symbol Pin Type Default at reset Description
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Chapter 3: Pin and Pad Descriptions
PIO12/SWCLK 15 IO SWCLK GPIO12 — General Purpose digital Input/Output 12
SWCLK — Serial Wire Debug Clock
PWM0 — Pulse Width Modulator output 0
I2C1_SCL — I
2
C-bus 1 master/slave SCL input/output (open drain)
SPI0_MOSI — Serial Peripheral Interface-bus 0 master output slave
input
ANA_COMP_OUT — Analog Comparator digital output
IR_BLASTER — Infra-Red Modulator output
PIO13/SWDIO 16 IO SWDIO GPIO13 — General Purpose digital Input/Output 13
SPI1_SSELN2 — Serial Peripheral Interface-bus 1, slave select not 2
SWDIO — Serial Wire Debug Input/Output
PWM2 — Pulse Width Modulator output 2
I2C1_SDAI
2
C-bus 1 master/slave SDA input/output (open drain)
SPI0_SSELN — Serial Peripheral Interface-bus 0, slave select not
PIO14/ADC0 17 IO GPIO14
[1]
ADC0 — ADC input 0
GPIO14 — General Purpose digital Input/Output 14
SPI1_SSELN1 — Serial Peripheral Interface-bus 1, slave select not 1
CT32B0_CAP1 — 32-bit CT32B0 capture input 1
PWM1 — Pulse Width Modulator output 1
SWO — Serial Wire Output
USART0_SCK — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - synchronous clock
MCLK — External clock, can be provided to DMIC IP
RFTX — Radio Transmit Control Output
PIO15/ADC1 18 IO GPIO15
[1]
ADC1 — ADC input 1
GPIO15 — General Purpose digital Input/Output 15
SPI1_SCK — Serial Peripheral Interface-bus 1, clock input/output
ANA_COMP_OUT — Analog Comparator digital output
PWM3 — Pulse Width Modulator output 3
PDM1_DATAPulse Density Modulation Data input from digital
microphone (channel 1)
I2C0_SCL — I2C-bus 0 master/slave SCL input/output (open drain)
RFRX — Radio Receiver Control Output
PIO16/ADC2 19 IO GPIO16
[1]
ADC2 — ADC input 2
GPIO16 — General Purpose digital Input/Output 16
SPI1_SSELN0 — Serial Peripheral Interface-bus 1, slave select not 0
PWM5 — Pulse Width Modulator output 5
PDM1_CLK — Pulse Density Modulation Clock output to digital
microphone (channel 1)
SPIFI_CSN — Quad-SPI Chip Select Not, output
ISO7816_RST — RST signal, output, for ISO7816 interface
I2C0_SDAI2C-bus 0 master/slave SDA input/output (open drain)
Table 3. Pin descriptions
Symbol Pin Type Default at reset Description
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User manual Rev. 1.4 — June 2020 17 of 350
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Chapter 3: Pin and Pad Descriptions
V
DDE
20 P V
DDE
Supply voltage for IO
PIO17/ADC3 21 IO GPIO17
[1]
ADC3 — ADC input 3
GPIO17 — General Purpose digital Input/Output 17
SPI1_MOSI — Serial Peripheral Interface-bus 1, master output slave
input
SWO — Serial Wire Output
PWM6 — Pulse Width Modulator output 6
SPIFI_IO3 — Quad-SPI Input/Output 3
ISO7816_CLK — Clock output for ISO7816 interface
CLK_OUT — Clock out
PIO18/ADC4 22 IO GPIO18
[1]
ADC4 — ADC input 4
GPIO18 — General Purpose digital Input/Output 18
SPI1_MISO — Serial Peripheral Interface-bus 1, master data input
CT32B0_MAT1 — 32-bit CT32B0 match output 1
PWM7 — Pulse Width Modulator output 7
SPIFI_CLK — Quad-SPI Clock output
ISO7816_IO — IO of ISO7816 interface
USART0_TXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - transmit data output
PIO19/ADC5 23 IO GPIO19
[1]
ADC5 — ADC input 5
GPIO19 — General Purpose digital Input/Output 19
ADO — Antenna Diversity Odd Output
PWM4 — Pulse Width Modulator output 4
SPIFI_IO0 — Quad-SPI Input/Output 0
USART1_RXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 1 - receive data input
CLK_IN — External clock
USART0_RXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - receive data input
PIO20/ACP 24 IO GPIO20
[1]
ACP — Analog Comparator Positive input
GPIO20 — General Purpose digital Input/Output 20
IR_BLASTER — Infra-Red Modulator output
PWM8 — Pulse Width Modulator output 8
RFTX — Radio Transmit control Output
SPIFI_IO2 — Quad-SPI Input/Output 2
USART1_TXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 1 - transmit data output
Table 3. Pin descriptions
Symbol Pin Type Default at reset Description
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Chapter 3: Pin and Pad Descriptions
[1] I: input at reset.
[2] For standard operation (normal boot or ISP programming mode), this pin should be high during the release
of reset. If there is no external driver to this pin, then the internal pull-up will keep this pin high.
[3] ISP programming mode: leave pin floating high during reset to avoid entering UART programming mode or
hold it low to program.
[4] In ISP mode, it is configured to USART0_TXD.
[5] In ISP mode, it is configured to USART0_RXD.
3.4 Pin properties
Table 4 presents the different functionality and default states of the pins. PIO10 and PIO11
have IO cells that support true I2C operation and also general purpose digital modes. The
reset and test reset pins support a narrow range of functionality. All other digital IOs are
standard GPIO IO cells.
PIO21/ACM 25 IO GPIO21
[1]
ACM — Analog Comparator Negative input
GPIO21 — General Purpose digital Input/Output 21
IR_BLASTER — Infra-Red Modulator output
PWM9 — Pulse Width Modulator output 9
RFRX — Radio Receiver Control Output
SWO — Serial Wire Output
SPIFI_IO1 — Quad-SPI Input/Output 1
USART1_SCK — Universal Synchronous/Asynchronous
Receiver/Transmitter 1 - synchronous clock
TRST 26 G TRST — must be connected to GND
RSTN 27 I RSTN — Reset Not input
V
BAT
28 P V
BAT
Supply voltage DCDC input
LX 29 LX — DCDC filter
V
SS(DCDC)
30 G V
SS(DCDC)
ground for DCDC section
FB 31 FB — DCDC Feedback input
V
DD(PMU)
32 P V
DD(PMU)
supply voltage for PMU section
XTAL_32K_P 33 crystal oscillator 32.768 kHz
XTAL_32K_N 34 crystal oscillator 32.768 kHz
V
DD(RADIO)
35 P V
DD(RADIO)
supply voltage for radio section
V
SS(RF)
36 G V
SS(RF)
RF ground
RF_IO 37 IO RF_IO — RF antenna, RF pin which can be considered as RF
Input/output. The radio transceiver is connected here.
V
SS(RF)
38 G V
SS(RF)
RF ground
LB 39 NFC tag antenna input B
LA 40 NFC tag antenna input A
exposed die
pad
G must be connected to RF ground plane
Table 3. Pin descriptions
Symbol Pin Type Default at reset Description
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User manual Rev. 1.4 — June 2020 19 of 350
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Chapter 3: Pin and Pad Descriptions
Table 4. Pin properties
Pin No.
Pin Name
Default status after POR
Pullup/ Pulldown enable after POR
Pullup/ pulldown selection after POR
Slew rate after POR
Passive pin filter after POR
Open drain enable at reset
Open drain enable control
Pin interrupt
Fast capability
1XTAL_P 
2XTAL_N 
3PIO0 Hi-ZYPUSSNNNYN
4PIO1 Hi-ZYPDSSNNNYN
5PIO2 Hi-ZYPDSSNNNYN
6PIO3 Hi-ZYPUSSNNNYN
7PIO4 Hi-ZYPUSSNNNYN
8PIO5/ISP_ENTRY Hi-ZYPUSSNNNYN
9PIO6 Hi-ZYPDSSNNNYN
10PIO7 Hi-ZYPDSSNNNYN
11PIO8/TXD0 Hi-ZYPUSSNNNYN
12PIO9/RXD0 Hi-ZYPUSSNNNYN
13 PIO10 Hi-Z N
[1]
SSNNYYY
14 PIO11 Hi-Z N
[1]
SSNNYYY
15PIO12/SWCLK Hi-ZYPUSSNNNYN
16PIO13/SWDIO Hi-ZYPUSSNNNYN
17PIO14/ADC0 Hi-ZYPUSSNNNYN
18PIO15/ADC1 Hi-ZYPUSSNNNYN
19PIO16/ADC2 Hi-ZYPUSSNNNYN
20 V
DDE

21PIO17/ADC3 Hi-ZYPDSSNNNYN
22PIO18/ADC4 Hi-ZYPDSSNNNYN
23PIO19/ADC5 Hi-ZYPDSSNNNYN
24PIO20/ACP Hi-ZYPDSSNNNYN
25PIO21/ACM Hi-ZYPUSSNNNYN
26 TRST
[2]
Hi-Z N N
27 RSTN H Y PU N
28 V
BAT

29 LX 
30 V
SS(DCDC)

31 FB 
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User manual Rev. 1.4 — June 2020 20 of 350
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Chapter 3: Pin and Pad Descriptions
[1] External pullup required
[2] Tie to ground for functional mode
32 V
DD(PMU)

33 XTAL_32K_P 
34 XTAL_32K_N 
35 V
DD(RADIO)

36 V
SS(RF)

37 RF_IO 
38 V
SS(RF)

39 LB 
40 LA 
Table 4. Pin properties
Pin No.
Pin Name
Default status after POR
Pullup/ Pulldown enable after POR
Pullup/ pulldown selection after POR
Slew rate after POR
Passive pin filter after POR
Open drain enable at reset
Open drain enable control
Pin interrupt
Fast capability
Table 5: Abbreviation used in the Table 4
Properties Abbreviation Descriptions
Default status after POR Hi-Z High impedance
H High level
L Low level
Pullup/pulldown Enable after
POR
Y Enabled
N Disabled
Pullup/pulldown selection after
POR
PU Pullup (ie reg ICON.MODE = 0x0)
PD Pulldown (ie reg ICON.MODE = 0x3)
Slew rate after POR FS Fast slew rate
For MFIO pads ie all except PIO10&11: IOCON.SLEW = 0 or
1, IOCON.SLEW1 = 1
For IICFPGPIO pads ie PIO10&11: IOCON.SLEW = 1
SS Slow slew rate
For MFIO pads ie all except PIO10&11: IOCON.SLEW = 0,
IOCON.SLEW1 = 0
For IICFPGPIO pads ie PIO10&11: IOCON.SLEW = 0
Passive Pin Filter after POR N Disabled (ie reg IOCON.FILTEROFF = 1)
Y Enabled (ie reg IOCON.FILTEROFF = 0)
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NXP JN5189/88 (T) User guide

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User guide

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