Holtek HT32F61641 User manual

32-Bit Arm® Cortex®-M0+ Li-Battery Protection Microcontroller

HT32F61641

User Manual

Revision: V1.00 Date: April 27, 2023

Rev. 1.00 2 of 477 April 27, 2023

32-Bit Arm® Cortex®-M0+ Li-Battery Protection MCU

HT32F61641

Table of Contents

1 Introduction ........................................................................................................... 22

Overview .............................................................................................................................. 22

Features ............................................................................................................................... 23

Device Information ............................................................................................................... 26

Block Diagram ..................................................................................................................... 27

Internal Connection Signal Lines ......................................................................................... 28

2 Document Conventions ....................................................................................... 29

3 System Architecture ............................................................................................. 30

Arm® Cortex®-M0+ Processor .............................................................................................. 30

Bus Architecture ................................................................................................................... 31

Memory Organization .......................................................................................................... 32

Memory Map ................................................................................................................................... 33

Embedded Flash Memory ............................................................................................................... 35

Embedded SRAM Memory ............................................................................................................. 35

AHB Peripherals ............................................................................................................................. 35

APB Peripherals ............................................................................................................................. 35

4 Flash Memory Controller (FMC) .......................................................................... 36

Introduction .......................................................................................................................... 36

Features ............................................................................................................................... 36

Functional Descriptions ....................................................................................................... 37

Flash Memory Map ......................................................................................................................... 37

Flash Memory Architecture ............................................................................................................. 37

Booting Conguration ..................................................................................................................... 38

Page Erase ..................................................................................................................................... 39

Mass Erase ..................................................................................................................................... 40

Word Programming ......................................................................................................................... 41

Option Byte Description .................................................................................................................. 42

Page Erase / Program Protection ................................................................................................... 42

Security Protection .......................................................................................................................... 43

Register Map ....................................................................................................................... 44

Register Descriptions ........................................................................................................... 45

Flash Target Address Register – TADR .......................................................................................... 45

Flash Write Data Register – WRDR ............................................................................................... 46

Flash Operation Command Register – OCMR ............................................................................... 47

Flash Operation Control Register – OPCR ..................................................................................... 48

Flash Operation Interrupt Enable Register – OIER ........................................................................ 49

Flash Operation Interrupt and Status Register – OISR .................................................................. 50

Flash Page Erase / Program Protection Status Register – PPSR .................................................. 52

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32-Bit Arm® Cortex®-M0+ Li-Battery Protection MCU

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Table of Contents

Flash Security Protection Status Register – CPSR ........................................................................ 53

Flash Vector Mapping Control Register – VMCR ........................................................................... 54

Flash Manufacturer and Device ID Register – MDID ...................................................................... 55

Flash Page Number Status Register – PNSR ................................................................................ 56

Flash Page Size Status Register – PSSR ...................................................................................... 57

Device ID Register – DIDR ............................................................................................................. 57

Custom ID Register n – CIDRn, n = 0 ~ 3 ...................................................................................... 58

5 Power Control Unit (PWRCU) .............................................................................. 59

Introduction .......................................................................................................................... 59

Features ............................................................................................................................... 60

Functional Descriptions ....................................................................................................... 60

VDD Power Domain .......................................................................................................................... 60

VCORE Power Domain ....................................................................................................................... 62

Operation Modes ............................................................................................................................ 62

Register Map ....................................................................................................................... 64

Register Descriptions ........................................................................................................... 64

Power Control Status Register – PWRSR ...................................................................................... 64

Power Control Register – PWRCR ................................................................................................. 65

Low Voltage / Brown Out Detect Control and Status Register – LVDCSR ..................................... 67

6 Clock Control Unit (CKCU) .................................................................................. 69

Introduction .......................................................................................................................... 69

Features ............................................................................................................................... 71

Functional Descriptions ....................................................................................................... 71

High Speed External Crystal Oscillator – HSE ............................................................................... 71

High Speed Internal RC Oscillator – HSI ........................................................................................ 72

Auto Trimming of High Speed Internal RC Oscillator – HSI ............................................................ 72

Low Speed External Crystal Oscillator – LSE ................................................................................. 73

Low Speed Internal RC Oscillator – LSI ......................................................................................... 74

Clock Ready Flag ........................................................................................................................... 74

System Clock (CK_SYS) Selection ................................................................................................ 74

HSE Clock Monitor ......................................................................................................................... 75

Clock Output Capability .................................................................................................................. 75

Register Map ....................................................................................................................... 76

Register Descriptions ........................................................................................................... 77

Global Clock Conguration Register – GCFGR .............................................................................. 77

Global Clock Control Register – GCCR .......................................................................................... 78

Global Clock Status Register – GCSR ........................................................................................... 79

Global Clock Interrupt Register – GCIR .......................................................................................... 80

AHB Conguration Register – AHBCFGR ...................................................................................... 81

AHB Clock Control Register – AHBCCR ........................................................................................ 82

APB Conguration Register – APBCFGR ....................................................................................... 83

APB Clock Control Register 0 – APBCCR0 .................................................................................... 84

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32-Bit Arm® Cortex®-M0+ Li-Battery Protection MCU

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Table of Contents

APB Clock Control Register 1 – APBCCR1 .................................................................................... 85

Clock Source Status Register – CKST ........................................................................................... 86

APB Peripheral Clock Selection Register 0 – APBPCSR0 ............................................................. 87

APB Peripheral Clock Selection Register 1 – APBPCSR1 ............................................................. 89

HSI Control Register – HSICR ........................................................................................................ 90

HSI Auto Trimming Counter Register – HSIATCR .......................................................................... 91

APB Peripheral Clock Selection Register 2 – APBPCSR2 ............................................................. 92

MCU Debug Control Register – MCUDBGCR ................................................................................ 93

7 Reset Control Unit (RSTCU) ................................................................................ 95

Introduction .......................................................................................................................... 95

Functional Descriptions ....................................................................................................... 95

Power On Reset ............................................................................................................................. 95

System Reset ................................................................................................................................. 96

AHB and APB Unit Reset ................................................................................................................ 96

Register Map ....................................................................................................................... 96

Register Descriptions ........................................................................................................... 97

Global Reset Status Register – GRSR ........................................................................................... 97

AHB Peripheral Reset Register – AHBPRSTR ............................................................................... 98

APB Peripheral Reset Register 0 – APBPRSTR0 .......................................................................... 99

APB Peripheral Reset Register 1 – APBPRSTR1 ........................................................................ 100

8 General Purpose I/O (GPIO) ............................................................................... 102

Introduction ........................................................................................................................ 102

Features ............................................................................................................................. 103

Functional Descriptions ..................................................................................................... 103

Default GPIO Pin Conguration .................................................................................................... 103

General Purpose I/O – GPIO ........................................................................................................ 103

GPIO Locking Mechanism ............................................................................................................ 105

Register Map ..................................................................................................................... 105

Register Descriptions ......................................................................................................... 106

Port A Data Direction Control Register – PADIRCR ..................................................................... 106

Port A Input Function Enable Control Register – PAINER ............................................................ 107

Port A Pull-Up Selection Register – PAPUR ................................................................................. 108

Port A Pull-Down Selection Register – PAPDR ............................................................................ 109

Port A Open-Drain Selection Register – PAODR ...........................................................................110

Port A Drive Current Selection Register – PADRVR ......................................................................111

Port A Lock Register – PALOCKR .................................................................................................112

Port A Data Input Register – PADINR ............................................................................................113

Port A Output Data Register – PADOUTR .....................................................................................113

Port A Output Set / Reset Control Register – PASRR ...................................................................114

Port A Output Reset Register – PARR ...........................................................................................115

Port A Sink Current Enhanced Selection Register – PASCER ......................................................115

Port B Data Direction Control Register – PBDIRCR ......................................................................116

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Table of Contents

Port B Input Function Enable Control Register – PBINER ............................................................117

Port B Pull-Up Selection Register – PBPUR .................................................................................118

Port B Pull-Down Selection Register – PBPDR .............................................................................119

Port B Open-Drain Selection Register – PBODR ......................................................................... 120

Port B Drive Current Selection Register – PBDRVR .................................................................... 121

Port B Lock Register – PBLOCKR ................................................................................................ 122

Port B Data Input Register – PBDINR .......................................................................................... 123

Port B Output Data Register – PBDOUTR ................................................................................... 123

Port B Output Set / Reset Control Register – PBSRR .................................................................. 124

Port B Output Reset Register – PBRR ......................................................................................... 125

Port B Sink Current Enhanced Selection Register – PBSCER ..................................................... 125

Port C Data Direction Control Register – PCDIRCR .................................................................... 126

Port C Input Function Enable Control Register – PCINER ........................................................... 127

Port C Pull-Up Selection Register – PCPUR ................................................................................ 128

Port C Pull-Down Selection Register – PCPDR ........................................................................... 129

Port C Open Drain Selection Register – PCODR ......................................................................... 130

Port C Current Drive Selection Register – PCDRVR .................................................................... 131

Port C Lock Register – PCLOCKR ............................................................................................... 132

Port C Data Input Register – PCDINR .......................................................................................... 133

Port C Output Data Register – PCDOUTR ................................................................................... 133

Port C Output Set / Reset Control Register – PCSRR ................................................................. 134

Port C Output Reset Register – PCRR ......................................................................................... 135

Port C Sink Current Enhanced Selection Register – PCSCER .................................................... 135

9 Alternate Function Input / Output Control Unit (AFIO) .................................... 136

Introduction ........................................................................................................................ 136

Features ............................................................................................................................. 137

Functional Descriptions ..................................................................................................... 137

External Interrupt Pin Selection .................................................................................................... 137

Alternate Function ......................................................................................................................... 138

Lock Mechanism .......................................................................................................................... 138

Register Map ..................................................................................................................... 138

Register Descriptions ......................................................................................................... 139

EXTI Source Selection Register 0 – ESSR0 ................................................................................ 139

EXTI Source Selection Register 1 – ESSR1 ................................................................................ 140

GPIO Port x Conguration Low Register – GPxCFGLR, x = A, B, C ............................................ 141

GPIO Port x Conguration High Register – GPxCFGHR, x = A, B, C .......................................... 142

10 Nested Vectored Interrupt Controller (NVIC) .................................................. 143

Introduction ........................................................................................................................ 143

Features ............................................................................................................................. 144

Functional Descriptions ..................................................................................................... 145

SysTick Calibration ....................................................................................................................... 145

Register Map ..................................................................................................................... 145

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Table of Contents

11 External Interrupt / Event Controller (EXTI) .................................................... 146

Introduction ........................................................................................................................ 146

Features ............................................................................................................................. 146

Functional Descriptions ..................................................................................................... 147

Wakeup Event Management......................................................................................................... 147

External Interrupt / Event Line Mapping ....................................................................................... 148

Interrupt and Debounce ................................................................................................................ 148

Register Map ..................................................................................................................... 149

Register Descriptions ......................................................................................................... 150

EXTI Interrupt n Conguration Register – EXTICFGRn, n = 0 ~ 3, 7 ~ 15 ................................... 150

EXTI Interrupt Control Register – EXTICR ................................................................................... 151

EXTI Interrupt Edge Flag Register – EXTIEDGEFLGR ................................................................ 152

EXTI Interrupt Edge Status Register – EXTIEDGESR ................................................................. 153

EXTI Interrupt Software Set Command Register – EXTISSCR .................................................... 154

EXTI Interrupt Wakeup Control Register – EXTIWAKUPCR ........................................................ 155

EXTI Interrupt Wakeup Polarity Register – EXTIWAKUPPOLR ................................................... 156

EXTI Interrupt Wakeup Flag Register – EXTIWAKUPFLG ........................................................... 157

12 Analog to Digital Converter (ADC) .................................................................. 158

Introduction ........................................................................................................................ 158

Features ............................................................................................................................. 159

Functional Descriptions ..................................................................................................... 159

ADC Clock Setup .......................................................................................................................... 159

Channel Selection ......................................................................................................................... 159

Conversion Mode .......................................................................................................................... 160

Start Conversion on External Event .............................................................................................. 162

Sampling Time Setting .................................................................................................................. 163

Data Format .................................................................................................................................. 163

Analog Watchdog.......................................................................................................................... 163

Interrupts ....................................................................................................................................... 164

Register Map ..................................................................................................................... 165

Register Descriptions ......................................................................................................... 166

ADC Conversion Control Register – ADCCR ............................................................................... 166

ADC Conversion List Register 0 – ADCLST0 .............................................................................. 167

ADC Conversion List Register 1 – ADCLST1 ............................................................................... 168

ADC Input Sampling Time Register – ADCSTR ........................................................................... 169

ADC Conversion Data Register y – ADCDRy, y = 0 ~ 7 ............................................................... 170

ADC Trigger Control Register – ADCTCR .................................................................................... 171

ADC Trigger Source Register – ADCTSR ..................................................................................... 172

ADC Watchdog Control Register – ADCWCR .............................................................................. 173

ADC Watchdog Threshold Register – ADCTR .............................................................................. 175

ADC Interrupt Enable Register – ADCIER .................................................................................... 176

ADC Interrupt Raw Status Register – ADCIRAW ......................................................................... 177

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32-Bit Arm® Cortex®-M0+ Li-Battery Protection MCU

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Table of Contents

ADC Interrupt Status Register – ADCISR ..................................................................................... 178

ADC Interrupt Clear Register – ADCICLR .................................................................................... 179

13 General-Purpose Timer (GPTM) ...................................................................... 180

Introduction ........................................................................................................................ 180

Features ............................................................................................................................. 181

Functional Descriptions ..................................................................................................... 181

Counter Mode ............................................................................................................................... 181

Clock Controller ............................................................................................................................ 183

Trigger Controller .......................................................................................................................... 185

Slave Controller ............................................................................................................................ 186

Master Controller .......................................................................................................................... 188

Channel Controller ........................................................................................................................ 189

Input Stage ................................................................................................................................... 191

Quadrature Decoder ..................................................................................................................... 193

Output Stage ................................................................................................................................. 194

Update Management .................................................................................................................... 198

Single Pulse Mode ........................................................................................................................ 199

Asymmetric PWM Mode ............................................................................................................... 201

Timer Interconnection ................................................................................................................... 201

Trigger Peripherals Start .............................................................................................................. 204

Register Map ..................................................................................................................... 204

Register Descriptions ......................................................................................................... 205

Timer Counter Conguration Register – CNTCFR ....................................................................... 205

Timer Mode Conguration Register – MDCFR ............................................................................. 206

Timer Trigger Conguration Register – TRCFR ............................................................................ 209

Timer Control Register – CTR ...................................................................................................... 210

Channel 0 Input Conguration Register – CH0ICFR .....................................................................211

Channel 1 Input Conguration Register – CH1ICFR .................................................................... 212

Channel 2 Input Conguration Register – CH2ICFR .................................................................... 214

Channel 3 Input Conguration Register – CH3ICFR .................................................................... 215

Channel 0 Output Conguration Register – CH0OCFR ............................................................... 217

Channel 1 Output Conguration Register – CH1OCFR ............................................................... 219

Channel 2 Output Conguration Register – CH2OCFR ............................................................... 221

Channel 3 Output Conguration Register – CH3OCFR ............................................................... 223

Channel Control Register – CHCTR ............................................................................................. 225

Channel Polarity Conguration Register – CHPOLR .................................................................... 226

Timer PDMA/Interrupt Control Register – DICTR ......................................................................... 227

Timer Event Generator Register – EVGR ..................................................................................... 228

Timer Interrupt Status Register – INTSR ...................................................................................... 229

Timer Counter Register – CNTR................................................................................................... 231

Timer Prescaler Register – PSCR ................................................................................................ 232

Timer Counter-Reload Register – CRR ........................................................................................ 233

Channel 0 Capture/Compare Register – CH0CCR ...................................................................... 234

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Table of Contents

Channel 1 Capture/Compare Register – CH1CCR ...................................................................... 235

Channel 2 Capture/Compare Register – CH2CCR ...................................................................... 236

Channel 3 Capture/Compare Register – CH3CCR ...................................................................... 237

Channel 0 Asymmetric Compare Register – CH0ACR ................................................................. 238

Channel 1 Asymmetric Compare Register – CH1ACR ................................................................. 238

Channel 2 Asymmetric Compare Register – CH2ACR ................................................................. 239

Channel 3 Asymmetric Compare Register – CH3ACR ................................................................. 239

14 Pulse-Width-Modulation Timer (PWM) ............................................................ 240

Introduction ........................................................................................................................ 240

Features ............................................................................................................................. 241

Functional Descriptions ..................................................................................................... 241

Counter Mode ............................................................................................................................... 241

Clock Controller ............................................................................................................................ 244

Trigger Controller .......................................................................................................................... 245

Slave Controller ............................................................................................................................ 246

Restart Mode ................................................................................................................................ 246

Pause Mode .................................................................................................................................. 247

Trigger Mode................................................................................................................................. 247

Master Controller .......................................................................................................................... 248

Channel Controller ........................................................................................................................ 249

Output Stage ................................................................................................................................. 249

Update Management .................................................................................................................... 253

Single Pulse Mode ........................................................................................................................ 254

Asymmetric PWM Mode ............................................................................................................... 256

Timer Interconnection ................................................................................................................... 256

Trigger Peripherals Start ............................................................................................................... 258

Register Map ..................................................................................................................... 259

Register Descriptions ......................................................................................................... 260

Timer Counter Conguration Register – CNTCFR ....................................................................... 260

Timer Mode Conguration Register – MDCFR ............................................................................. 261

Timer Trigger Conguration Register – TRCFR ............................................................................ 263

Timer Control Register – CTR ...................................................................................................... 264

Channel 0 Output Conguration Register – CH0OCFR ............................................................... 265

Channel 1 Output Conguration Register – CH1OCFR ............................................................... 267

Channel 2 Output Conguration Register – CH2OCFR ............................................................... 269

Channel 3 Output Conguration Register – CH3OCFR ............................................................... 271

Channel Control Register – CHCTR ............................................................................................. 273

Channel Polarity Conguration Register – CHPOLR .................................................................... 274

Timer PDMA/Interrupt Control Register – DICTR ......................................................................... 275

Timer Event Generator Register – EVGR ..................................................................................... 276

Timer Interrupt Status Register – INTSR ...................................................................................... 277

Timer Counter Register – CNTR................................................................................................... 278

Timer Prescaler Register – PSCR ................................................................................................ 279

Timer Counter-Reload Register – CRR ........................................................................................ 280

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32-Bit Arm® Cortex®-M0+ Li-Battery Protection MCU

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Channel 0 Compare Register – CH0CR ....................................................................................... 280

Channel 1 Compare Register – CH1CR ....................................................................................... 281

Channel 2 Compare Register – CH2CR ....................................................................................... 281

Channel 3 Compare Register – CH3CR ....................................................................................... 282

Channel 0 Asymmetric Compare Register – CH0ACR ................................................................. 282

Channel 1 Asymmetric Compare Register – CH1ACR ................................................................. 283

Channel 2 Asymmetric Compare Register – CH2ACR ................................................................. 283

Channel 3 Asymmetric Compare Register – CH3ACR ................................................................. 284

15 Basic Function Timer (BFTM) .......................................................................... 285

Introduction ........................................................................................................................ 285

Features ............................................................................................................................. 285

Functional Description ....................................................................................................... 285

Repetitive Mode ............................................................................................................................ 286

One Shot Mode ............................................................................................................................. 286

Register Map ..................................................................................................................... 287

Register Descriptions ......................................................................................................... 288

BFTM Control Register – BFTMCR .............................................................................................. 288

BFTM Status Register – BFTMSR ................................................................................................ 289

BFTM Counter Value Register – BFTMCNTR .............................................................................. 290

BFTM Compare Value Register – BFTMCMPR ........................................................................... 290

16 Motor Control Timer (MCTM) ........................................................................... 291

Introduction ........................................................................................................................ 291

Features ............................................................................................................................. 292

Functional Descriptions ..................................................................................................... 292

Counter Mode ............................................................................................................................... 292

Clock Controller ............................................................................................................................ 296

Trigger Controller .......................................................................................................................... 297

Slave Controller ............................................................................................................................ 298

Master Controller .......................................................................................................................... 300

Channel Controller ........................................................................................................................ 301

Input Stage ................................................................................................................................... 302

Output Stage ................................................................................................................................. 304

Update Management .................................................................................................................... 315

Single Pulse Mode ........................................................................................................................ 317

Asymmetric PWM Mode ............................................................................................................... 319

Timer Interconnection ................................................................................................................... 320

Trigger Peripherals Start ............................................................................................................... 324

Lock Level Table ........................................................................................................................... 324

Register Map ..................................................................................................................... 325

Register Descriptions ......................................................................................................... 326

Timer Counter Conguration Register – CNTCFR ....................................................................... 326

Timer Mode Conguration Register – MDCFR ............................................................................. 327

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32-Bit Arm® Cortex®-M0+ Li-Battery Protection MCU

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Timer Trigger Conguration Register – TRCFR ............................................................................ 329

Timer Control Register – CTR ...................................................................................................... 330

Channel 0 Input Conguration Register – CH0ICFR .................................................................... 331

Channel 1 Input Conguration Register – CH1ICFR .................................................................... 332

Channel 2 Input Conguration Register – CH2ICFR .................................................................... 334

Channel 3 Input Conguration Register – CH3ICFR .................................................................... 335

Channel 0 Output Conguration Register – CH0OCFR ............................................................... 337

Channel 1 Output Conguration Register – CH1OCFR ............................................................... 339

Channel 2 Output Conguration Register – CH2OCFR ............................................................... 341

Channel 3 Output Conguration Register – CH3OCFR ............................................................... 343

Channel Control Register – CHCTR ............................................................................................. 345

Channel Polarity Conguration Register – CHPOLR .................................................................... 347

Channel Break Conguration Register – CHBRKCFR ................................................................. 348

Channel Break Control Register – CHBRKCTR ........................................................................... 349

Timer Interrupt Control Register – DICTR .................................................................................... 351

Timer Event Generator Register – EVGR ..................................................................................... 352

Timer Interrupt Status Register – INTSR ...................................................................................... 354

Timer Counter Register – CNTR................................................................................................... 356

Timer Prescaler Register – PSCR ................................................................................................ 357

Timer Counter-Reload Register – CRR ........................................................................................ 358

Timer Repetition Register – REPR ............................................................................................... 358

Channel 0 Capture/Compare Register – CH0CCR ...................................................................... 359

Channel 1 Capture/Compare Register – CH1CCR ...................................................................... 360

Channel 2 Capture/Compare Register – CH2CCR ...................................................................... 361

Channel 3 Capture/Compare Register – CH3CCR ...................................................................... 362

Channel 0 Asymmetric Compare Register – CH0ACR ................................................................. 363

Channel 1 Asymmetric Compare Register – CH1ACR ................................................................. 363

Channel 2 Asymmetric Compare Register – CH2ACR ................................................................. 364

Channel 3 Asymmetric Compare Register – CH3ACR ................................................................. 364

17 Real-Time Clock (RTC) ..................................................................................... 365

Introduction ........................................................................................................................ 365

Features ............................................................................................................................. 365

Functional Descriptions ..................................................................................................... 366

RTC Related Register Reset ........................................................................................................ 366

Low Speed Clock Conguration ................................................................................................... 366

RTC Counter Operation ................................................................................................................ 366

Interrupt and Wakeup Control ....................................................................................................... 366

RTCOUT Output Pin Conguration............................................................................................... 367

Register Map ..................................................................................................................... 368

Register Descriptions ......................................................................................................... 368

RTC Counter Register – RTCCNT ................................................................................................ 368

RTC Compare Register – RTCCMP ............................................................................................. 369

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RTC Control Register – RTCCR ................................................................................................... 370

RTC Status Register – RTCSR..................................................................................................... 372

RTC Interrupt and Wakeup Enable Register – RTCIWEN ............................................................ 373

18 Watchdog Timer (WDT) .................................................................................... 374

Introduction ........................................................................................................................ 374

Features ............................................................................................................................. 374

Functional Description ....................................................................................................... 375

Register Map ..................................................................................................................... 376

Register Descriptions ......................................................................................................... 377

Watchdog Timer Control Register – WDTCR ............................................................................... 377

Watchdog Timer Mode Register 0 – WDTMR0............................................................................. 378

Watchdog Timer Mode Register 1 – WDTMR1............................................................................. 379

Watchdog Timer Status Register – WDTSR ................................................................................. 380

Watchdog Timer Protection Register – WDTPR ........................................................................... 381

Watchdog Timer Clock Selection Register – WDTCSR ................................................................ 382

19 Inter-Integrated Circuit (I2C) ............................................................................. 383

Introduction ........................................................................................................................ 383

Features ............................................................................................................................. 384

Functional Descriptions ..................................................................................................... 384

Two-Wire Serial Interface ............................................................................................................. 384

START and STOP Conditions ....................................................................................................... 384

Data Validity .................................................................................................................................. 385

Addressing Format ....................................................................................................................... 385

Data Transfer and Acknowledge ................................................................................................... 386

Clock Synchronization .................................................................................................................. 387

Arbitration ..................................................................................................................................... 387

General Call Addressing ............................................................................................................... 388

Bus Error ....................................................................................................................................... 388

Address Mask Enable ................................................................................................................... 388

Address Snoop ............................................................................................................................. 388

Operation Mode ............................................................................................................................ 388

Conditions of Holding SCL Line .................................................................................................... 393

I2C Timeout Function .................................................................................................................... 394

Register Map ..................................................................................................................... 394

Register Descriptions ......................................................................................................... 395

I2C Control Register – I2CCR ....................................................................................................... 395

I2C Interrupt Enable Register – I2CIER ........................................................................................ 396

I2C Address Register – I2CADDR ................................................................................................. 397

I2C Status Register – I2CSR ......................................................................................................... 398

I2C SCL High Period Generation Register – I2CSHPGR .............................................................. 401

I2C SCL Low Period Generation Register – I2CSLPGR ............................................................... 402

I2C Data Register – I2CDR ........................................................................................................... 403

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I2C Target Register – I2CTAR ....................................................................................................... 404

I2C Address Mask Register – I2CADDMR .................................................................................... 405

I2C Address Snoop Register – I2CADDSR ................................................................................... 406

I2C Timeout Register – I2CTOUT.................................................................................................. 407

20 Serial Peripheral Interface (SPI) ...................................................................... 408

Introduction ........................................................................................................................ 408

Features ............................................................................................................................. 409

Functional Descriptions ..................................................................................................... 409

Master Mode ................................................................................................................................. 409

Slave Mode ................................................................................................................................... 409

SPI Serial Frame Format .............................................................................................................. 410

SPI Dual Mode .............................................................................................................................. 413

Status Flags .................................................................................................................................. 416

Register Map ..................................................................................................................... 419

Register Descriptions ......................................................................................................... 419

SPI Control Register 0 – SPICR0 ................................................................................................. 419

SPI Control Register 1 – SPICR1 ................................................................................................. 421

SPI Interrupt Enable Register – SPIIER ....................................................................................... 423

SPI Clock Prescaler Register – SPICPR ...................................................................................... 424

SPI Data Register – SPIDR .......................................................................................................... 425

SPI Status Register – SPISR ........................................................................................................ 426

SPI FIFO Control Register – SPIFCR ........................................................................................... 427

SPI FIFO Status Register – SPIFSR ............................................................................................ 429

SPI FIFO Time Out Counter Register – SPIFTOCR ..................................................................... 430

21 Universal Synchronous Asynchronous Receiver Transmitter (USART) ..... 431

Introduction ........................................................................................................................ 431

Features ............................................................................................................................. 432

Functional Descriptions ..................................................................................................... 432

Serial Data Format ........................................................................................................................ 432

Baud Rate Generation .................................................................................................................. 433

Hardware Flow Control ................................................................................................................. 434

IrDA ............................................................................................................................................... 435

RS485 Mode ................................................................................................................................. 437

Synchronous Master Mode ........................................................................................................... 439

Interrupts and Status .................................................................................................................... 441

Register Map ..................................................................................................................... 441

Register Descriptions ......................................................................................................... 442

USART Data Register – USRDR .................................................................................................. 442

USART Control Register – USRCR .............................................................................................. 443

USART FIFO Control Register – USRFCR................................................................................... 445

USART Interrupt Enable Register – USRIER ............................................................................... 446

USART Status & Interrupt Flag Register – USRSIFR................................................................... 448

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USART Timing Parameter Register – USRTPR ........................................................................... 450

USART IrDA Control Register – IrDACR ...................................................................................... 451

USART RS485 Control Register – RS485CR............................................................................... 452

USART Synchronous Control Register – SYNCR ........................................................................ 453

USART Divider Latch Register – USRDLR................................................................................... 454

USART Test Register – USRTSTR ............................................................................................... 455

22 Universal Asynchronous Receiver Transmitter (UART) ................................ 456

Introduction ........................................................................................................................ 456

Features ............................................................................................................................. 457

Functional Descriptions ..................................................................................................... 457

Serial Data Format ........................................................................................................................ 457

Baud Rate Generation .................................................................................................................. 458

Interrupts and Status .................................................................................................................... 459

Register Map ..................................................................................................................... 459

Register Descriptions ......................................................................................................... 460

UART Data Register – URDR ....................................................................................................... 460

UART Control Register – URCR ................................................................................................... 461

UART Interrupt Enable Register – URIER .................................................................................... 462

UART Status & Interrupt Flag Register – URSIFR ....................................................................... 463

UART Divider Latch Register – URDLR ....................................................................................... 465

UART Test Register – URTSTR .................................................................................................... 466

23 Divider (DIV) ...................................................................................................... 467

Introduction ........................................................................................................................ 467

Features ............................................................................................................................. 467

Functional Descriptions ..................................................................................................... 467

Register Map ..................................................................................................................... 468

Register Descriptions ......................................................................................................... 468

Divider Control Register – CR ...................................................................................................... 468

Dividend Data Register – DDR ..................................................................................................... 469

Divisor Data Register – DSR ........................................................................................................ 469

Quotient Data Register – QTR ...................................................................................................... 470

Remainder Data Register – RMR ................................................................................................. 470

24 Cyclic Redundancy Check (CRC) .................................................................... 471

Introduction ....................................................................................................................... 471

Features ............................................................................................................................. 471

Functional Descriptions ..................................................................................................... 472

CRC Computation ......................................................................................................................... 472

Byte and Bit Reversal for CRC Computation ................................................................................ 472

Register Map ..................................................................................................................... 473

Register Descriptions ......................................................................................................... 473

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Table of Contents

CRC Control Register – CRCCR .................................................................................................. 473

CRC Seed Register – CRCSDR ................................................................................................... 474

CRC Checksum Register – CRCCSR .......................................................................................... 475

CRC Data Register – CRCDR ...................................................................................................... 476

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Table of Contents

List of Tables

Table 1. Features and Peripheral List ..................................................................................................... 26

Table 2. Internal Connection Signal Lines .............................................................................................. 28

Table 3. Document Conventions ............................................................................................................. 29

Table 4. Register Map ............................................................................................................................. 34

Table 5. Flash Memory and Option Byte ................................................................................................. 38

Table 6. Booting Modes .......................................................................................................................... 38

Table 7. Option Byte Memory Map ......................................................................................................... 42

Table 8. Access Permission of Protected Main Flash Page .................................................................... 43

Table 9. Access Permission When Security Protection is Enabled ......................................................... 43

Table 10. FMC Register Map .................................................................................................................. 44

Table 11. Operation Mode Denitions ..................................................................................................... 62

Table 12. Enter / Exit Power Saving Modes ............................................................................................ 63

Table 13. Power Status After System Reset ........................................................................................... 63

Table 14. PWRCU Register Map ............................................................................................................ 64

Table 15. CKOUT Clock Source ............................................................................................................. 75

Table 16. CKCU Register Map ............................................................................................................... 76

Table 17. RSTCU Register Map ............................................................................................................. 96

Table 18. AFIO, GPIO and I/O Pad Control Signal True Table.............................................................. 104

Table 19. GPIO Register Map ............................................................................................................... 105

Table 20. AFIO Selection for Peripheral Map Example ......................................................................... 138

Table 21. AFIO Register Map ................................................................................................................ 138

Table 22. Exception Types .................................................................................................................... 143

Table 23. NVIC Register Map ............................................................................................................... 145

Table 24. EXTI Register Map ................................................................................................................ 149

Table 25. Data Format in ADCDR [15:0] ............................................................................................... 163

Table 26. A/D Converter Register Map ................................................................................................. 165

Table 27. Counting Direction and Encoding Signals ............................................................................. 194

Table 28. Compare Match Output Setup .............................................................................................. 195

Table 29. GPTM Register Map ............................................................................................................. 204

Table 30. GPTM Internal Trigger Connection ....................................................................................... 209

Table 31. Compare Match Output Setup .............................................................................................. 250

Table 32. PWM Register Map ............................................................................................................... 259

Table 33. PWM Internal Trigger Connection ......................................................................................... 263

Table 34. BFTM Register Map .............................................................................................................. 287

Table 35. Compare Match Output Setup .............................................................................................. 305

Table 36. Output Control Bits for Complementary Output with a Break Event Occurrence .................. 314

Table 37. Lock Level Table.................................................................................................................... 324

Table 38. MCTM Register Map ............................................................................................................. 325

Table 39. MCTM Internal Trigger Connection ....................................................................................... 329

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List of Tables

Table 40. LSE Startup Mode Operating Current and Startup Time ....................................................... 366

Table 41. RTCOUT Output Mode and Active Level Setting .................................................................. 367

Table 42. RTC Register Map................................................................................................................. 368

Table 43. Watchdog Timer Register Map .............................................................................................. 376

Table 44. Conditions of Holding SCL line .............................................................................................. 393

Table 45. I2C Register Map ................................................................................................................... 394

Table 46. I2C Clock Setting Example .................................................................................................... 402

Table 47. SPI Interface Format Setup ................................................................................................... 410

Table 48. SPI Mode Fault Trigger Conditions ....................................................................................... 417

Table 49. SPI Master Mode SPI_SEL Pin Status .................................................................................. 418

Table 50. SPI Register Map .................................................................................................................. 419

Table 51. Baud Rate Deviation Error Calculation – CK_USART = 20 MHz .......................................... 434

Table 52. Baud Rate Deviation Error Calculation – CK_USART = 10 MHz .......................................... 434

Table 53. USART Register Map ............................................................................................................ 441

Table 54. Baud Rate Deviation Error Calculation – CK_UART = 20 MHz ............................................ 458

Table 55. Baud Rate Deviation Error Calculation – CK_UART = 10 MHz ............................................ 458

Table 56. UART Register Map .............................................................................................................. 459

Table 57. DIV Register Map .................................................................................................................. 468

Table 58. CRC Register Map ................................................................................................................ 473

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List of Tables

List of Figures

Figure 1. Block Diagram ......................................................................................................................... 27

Figure 2. Cortex®-M0+ Block Diagram .................................................................................................... 31

Figure 3. Bus Architecture ...................................................................................................................... 32

Figure 4. Memory Map ............................................................................................................................ 33

Figure 5. Flash Memory Controller Block Diagram ................................................................................. 36

Figure 6. Flash Memory Map .................................................................................................................. 37

Figure 7. Vector Remapping ................................................................................................................... 38

Figure 8. Page Erase Operation Flowchart ............................................................................................ 39

Figure 9. Mass Erase Operation Flowchart ............................................................................................ 40

Figure 10. Word Programming Operation Flowchart .............................................................................. 41

Figure 11. PWRCU Block Diagram ......................................................................................................... 59

Figure 12. Power On Reset / Power Down Reset Waveform ................................................................. 61

Figure 13. CKCU Block Diagram ............................................................................................................ 70

Figure 14. External Crystal, Ceramic and Resonators for HSE .............................................................. 71

Figure 15. HSI Auto Trimming Block Diagram ........................................................................................ 73

Figure 16. External Crystal, Ceramic and Resonators for LSE .............................................................. 74

Figure 17. RSTCU Block Diagram .......................................................................................................... 95

Figure 18. Power On Reset Sequence ................................................................................................... 96

Figure 19. GPIO Block Diagram ........................................................................................................... 102

Figure 20. AFIO / GPIO Control Signal ................................................................................................. 104

Figure 21. AFIO Block Diagram ............................................................................................................ 136

Figure 22. EXTI Channel Input Selection ............................................................................................. 137

Figure 23. EXTI Block Diagram (n = 0 ~ 3, 7 ~ 15) ............................................................................... 146

Figure 24. EXTI Wakeup Event Management (n = 0 ~ 3, 7 ~ 15) ......................................................... 147

Figure 25. EXTI Wakeup Interrupt Service Routine Management (n = 0 ~ 3, 7 ~ 15) .......................... 148

Figure 26. EXTI Interrupt Debounce Function (n = 0 ~ 3, 7 ~ 15) ........................................................ 148

Figure 27. ADC Block Diagram ............................................................................................................. 158

Figure 28. One Shot Conversion Mode ................................................................................................ 160

Figure 29. Continuous Conversion Mode ............................................................................................. 161

Figure 30. Discontinuous Conversion Mode ......................................................................................... 162

Figure 31. GPTM Block Diagram .......................................................................................................... 180

Figure 32. Up-counting Example .......................................................................................................... 182

Figure 33. Down-counting Example ...................................................................................................... 182

Figure 34. Center-aligned Counting Example ....................................................................................... 183

Figure 35. GPTM Clock Source Selection ............................................................................................ 184

Figure 36. Trigger Controller Block ....................................................................................................... 185

Figure 37. Slave Controller Diagram .................................................................................................... 186

Figure 38. GPTM in Restart Mode ........................................................................................................ 186

Figure 39. GPTM in Pause Mode ......................................................................................................... 187

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List of Figures

Figure 40. GPTM in Trigger Mode ........................................................................................................ 187

Figure 41. Master GPTMn and Slave GPTMm/MCTMm Connection ................................................... 188

Figure 42. MTO Selection ..................................................................................................................... 188

Figure 43. Capture/Compare Block Diagram ........................................................................................ 189

Figure 44. Input Capture Mode ............................................................................................................. 189

Figure 45. PWM Pulse Width Measurement Example .......................................................................... 190

Figure 46. Channel 0 and Channel 1 Input Stages ............................................................................... 191

Figure 47. Channel 2 and Channel 3 Input Stages ............................................................................... 192

Figure 48. TI0 Digital Filter Diagram with N = 2 .................................................................................... 192

Figure 49. Input Stage and Quadrature Decoder Block Diagram ......................................................... 193

Figure 50. Both TI0 and TI1 Quadrature Decoder Counting ................................................................. 194

Figure 51. Output Stage Block Diagram ............................................................................................... 194

Figure 52. Toggle Mode Channel Output Reference Signal (CHxPRE = 0) ......................................... 195

Figure 53. Toggle Mode Channel Output Reference Signal (CHxPRE = 1) ......................................... 196

Figure 54. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode ............ 196

Figure 55. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode ....... 197

Figure 56. PWM Mode Channel Output Reference Signal and Counter in Centre-aligned Mode ........ 197

Figure 57. Update Event Setting Diagram ............................................................................................ 198

Figure 58. Single Pulse Mode ............................................................................................................... 199

Figure 59. Immediate Active Mode Delay ............................................................................................. 200

Figure 60. Asymmetric PWM Mode versus Center-Aligned Counting Mode ........................................ 201

Figure 61. Pausing MTCM using the GPTM CH0OREF Signal ............................................................ 202

Figure 62. Triggering MTCM with GPTM Update Event ....................................................................... 202

Figure 63. Trigger GPTM and MTCM with the GPTM CH0 Input ......................................................... 203

Figure 64. PWM Block Diagram ........................................................................................................... 240

Figure 65. Up-counting Example .......................................................................................................... 241

Figure 66. Down-counting Example ...................................................................................................... 242

Figure 67. Center-aligned Counting Example ....................................................................................... 243

Figure 68. PWM Clock Source Selection .............................................................................................. 244

Figure 69. Trigger Controller Block ....................................................................................................... 245

Figure 70. Slave Controller Diagram .................................................................................................... 246

Figure 71. PWM in Restart Mode ......................................................................................................... 246

Figure 72. PWM in Pause Mode ........................................................................................................... 247

Figure 73. PWM in Trigger Mode .......................................................................................................... 247

Figure 74. Master PWMn and Slave PWMm/TMm Connection ............................................................ 248

Figure 75. MTO Selection ..................................................................................................................... 248

Figure 76. Compare Block Diagram ..................................................................................................... 249

Figure 77. Output Stage Block Diagram ............................................................................................... 249

Figure 78. Toggle Mode Channel Output Reference Signal (CHxPRE = 0) ......................................... 250

Figure 79. Toggle Mode Channel Output Reference Signal (CHxPRE = 1) ......................................... 251

Figure 80. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode ............ 251

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List of Figures

Figure 81. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode ....... 252

Figure 82. PWM Mode Channel Output Reference Signal and Counter in Center-aligned Mode ........ 252

Figure 83. Update Event Setting Diagram ............................................................................................ 253

Figure 84. Single Pulse Mode ............................................................................................................... 254

Figure 85. Immediate Active Mode Delay ............................................................................................. 255

Figure 86. Asymmetric PWM Mode versus Center-aligned Counting Mode ......................................... 256

Figure 87. Pausing PWM1 using the PWM0 CH0OREF Signal ........................................................... 257

Figure 88. Triggering PWM1 with PWM0 Update Event ....................................................................... 257

Figure 89. Trigger PWM0 and PWM1 with the PWM0 Timer Enable Signal ........................................ 258

Figure 90. BFTM Block Diagram .......................................................................................................... 285

Figure 91. BFTM – Repetitive Mode ..................................................................................................... 286

Figure 92. BFTM – One Shot Mode ...................................................................................................... 286

Figure 93. BFTM – One Shot Mode Counter Updating ........................................................................ 287

Figure 94. MCTM Block Diagram ......................................................................................................... 291

Figure 95. Up-counting Example .......................................................................................................... 293

Figure 96. Down-counting Example ...................................................................................................... 293

Figure 97. Center-aligned Counting Example ....................................................................................... 294

Figure 98. Update Event 1 Dependent Repetition Mechanism Example .............................................. 295

Figure 99. MCTM Clock Source Selection ............................................................................................ 296

Figure 100. Trigger Controller Block ..................................................................................................... 297

Figure 101. Slave Controller Diagram .................................................................................................. 298

Figure 102. MCTM in Restart Mode ..................................................................................................... 298

Figure 103. MCTM in Pause Mode ....................................................................................................... 299

Figure 104. MCTM in Trigger Mode ...................................................................................................... 299

Figure 105. Master MCTMn and Slave GPTMm Connection ............................................................... 300

Figure 106. MTO Selection ................................................................................................................... 300

Figure 107. Capture/Compare Block Diagram ...................................................................................... 301

Figure 108. Input Capture Mode ........................................................................................................... 301

Figure 109. PWM Pulse Width Measurement Example ........................................................................ 302

Figure 110. Channel 0 and Channel 1 Input Stages ............................................................................. 303

Figure 111. Channel 2 and Channel 3 Input Stages ............................................................................. 303

Figure 112. TI0 Digital Filter Diagram with N = 2 .................................................................................. 304

Figure 113. Output Stage Block Diagram ............................................................................................. 304

Figure 114. Toggle Mode Channel Output Reference Signal – CHxPRE = 0 ....................................... 305

Figure 115. Toggle Mode Channel Output Reference Signal – CHxPRE = 1 ....................................... 306

Figure 116. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode .......... 306

Figure 117. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode ...... 307

Figure 118. PWM Mode 1 Channel Output Reference Signal and Counter in Centre-aligned Counting

Mode ...................................................................................................................................................... 307

Figure 119. Dead-time Insertion Performed for Complementary Outputs............................................. 308

Figure 120. MCTM Break Signal Bolck Diagram .................................................................................. 309

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List of Figures

Figure 121. MT_BRK Pin Digital Filter Diagram with N = 2 .................................................................. 309

Figure 122. Channel 3 Output with a Break Event Occurrence ............................................................ 310

Figure 123. Channel 0 ~ 2 Complementary Outputs with a Break Event Occurrence...........................311

Figure 124. Channel 0 ~ 2 Only One Output Enabled when Break Event Occurs ............................... 312

Figure 125. Hardware Protection When Both CHxO and CHxNO are in Active Condition ................... 313

Figure 126. Update Event 1 Setup Diagram ......................................................................................... 315

Figure 127. CHxE, CHxNE and CHxOM Updated by Update Event 2 ................................................. 316

Figure 128. Update Event 2 Setup Diagram ......................................................................................... 316

Figure 129. Single Pulse Mode ............................................................................................................. 317

Figure 130. Immediate Active Mode Delay ........................................................................................... 318

Figure 131. Asymmetric PWM Mode versus Center-aligned Counting Mode ....................................... 319

Figure 132. Pausing GPTM using the MCTM CH0OREF Signal .......................................................... 320

Figure 133. Triggering GPTM with MCTM Update Event 1 .................................................................. 321

Figure 134. Trigger MCTM and GPTM with the MCTM CH0 Input ....................................................... 322

Figure 135. CH0XOR Input as Hall Sensor Interface ........................................................................... 323

Figure 136. RTC Block Diagram ........................................................................................................... 365

Figure 137. Watchdog Timer Block Diagram ....................................................................................... 374

Figure 138. Watchdog Timer Behavior ................................................................................................. 376

Figure 139. I2C Module Block Diagram ................................................................................................. 383

Figure 140. START and STOP Condition ............................................................................................. 384

Figure 141. Data Validity ....................................................................................................................... 385

Figure 142. 7-Bit Addressing Mode ...................................................................................................... 385

Figure 143. 10-Bit Addressing Write Transmit Mode ............................................................................ 386

Figure 144. 10-Bit Addressing Read Receive Mode ............................................................................ 386

Figure 145. I2C Bus Acknowledge ........................................................................................................ 386

Figure 146. Clock Synchronization during Arbitration ........................................................................... 387

Figure 147. Two Master Arbitration Procedure ..................................................................................... 387

Figure 148. Master Transmitter Timing Diagram .................................................................................. 389

Figure 149. Master Receiver Timing Diagram ...................................................................................... 391

Figure 150. Slave Transmitter Timing Diagram .................................................................................... 392

Figure 151. Slave Receiver Timing Diagram ........................................................................................ 393

Figure 152. SCL Timing Diagram .......................................................................................................... 402

Figure 153. SPI Block Diagram ............................................................................................................ 408

Figure 154. SPI Single Byte Transfer Timing Diagram – CPOL = 0, CPHA = 0 .................................... 410

Figure 155. SPI Continuous Data Transfer Timing Diagram – CPOL = 0, CPHA = 0 ............................411

Figure 156. SPI Single Byte Transfer Timing Diagram – CPOL = 0, CPHA = 1 .....................................411

Figure 157. SPI Continuous Transfer Timing Diagram – CPOL = 0, CPHA = 1 .....................................411

Figure 158. SPI Single Byte Transfer Timing Diagram – CPOL = 1, CPHA = 0 .................................... 412

Figure 159. SPI Continuous Transfer Timing Diagram – CPOL = 1, CPHA = 0 .................................... 412

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Holtek HT32F61641 User manual

Holtek HT32F61641 User manual

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