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SH7262 Group, SH7264 Group
User's Manual: Hardware
Rev.4.00 2014.09
SH7262 R5S72620 SH7264 R5S72640
R5S72621 R5S72641
R5S72622 R5S72642
R5S72623 R5S72643
R5S72624 R5S72644
R5S72625 R5S72645
R5S72626 R5S72646
R5S72627 R5S72647
Renesas 32-Bit RISC Microcomputer
SuperH
TM
RISC engine Family / SH7260 Series
32
The revision list can be viewed directly by clicking the title page.
The revision list summarizes the locations of revisions and
additions. Details should always be checked by referring to the
relevant text.
Page ii of xl R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
R01UH0134EJ0400 Rev. 4.00 Page iii of xl
Sep 24, 2014
Notice
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you
or third parties arising from the use of these circuits, software, or information.
2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics
does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages
incurred by you resulting from errors in or omissions from the information included herein.
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(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-
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(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
(2012.4)
Page iv of xl R01UH0134EJ0400 Rev. 4.00
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General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass-
through current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product's state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system's
operation is not guaranteed if they are accessed.
R01UH0134EJ0400 Rev. 4.00 Page v of xl
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Configuration of This Manual
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
CPU and System-Control Modules
On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
• Package Dimensions, etc.
10. Main Revisions for This Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Page vi of xl R01UH0134EJ0400 Rev. 4.00
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R01UH0134EJ0400 Rev. 4.00 Page vii of xl
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Preface
This LSI is an RISC (Reduced Instruction Set Computer) microcomputer which includes a
Renesas-original RISC CPU as its core, and the peripheral functions required to configure a
system.
Target Users: This manual was written for users who will be using this LSI in the design of
application systems. Target users are expected to understand the fundamentals of
electrical circuits, logical circuits, and microcomputers.
Objective: This manual was written to explain the hardware functions and electrical
characteristics of this LSI to the target users.
Refer to the SH-2A, SH2A-FPU Software Manual for a detailed description of the
instruction set.
Notes on reading this manual:
In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
In order to understand the details of the CPU's functions
Read the SH-2A, SH2A-FPU Software Manual.
In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 36,
List of Registers.
Page viii of xl R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
Description of Numbers and Symbols
Aspects of the notations for register names, bit names, numbers, and symbolic names in this
manual are explained below.
CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter
input clock. Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0.
14.3 Operation
The style "register name"_"instance number" is used in cases where there is more than one
instance of the same function or similar functions.
[Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0.
In descriptions involving the names of bits and bit fields within this manual, the modules and
registers to which the bits belong may be clarified by giving the names in the forms
"module name"."register name"."bit name" or "register name"."bit name".
(1) Overall notation
(2) Register notation
Rev. 0.50, 10/04, page 416 of 914
14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1)
14.3.1 Interval Count Operation
(4)
(3)
(2)
Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary),
hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn.
[Examples] Binary: B'11 or 11
Hexadecimal: H'EFA0 or 0xEFA0
Decimal: 1234
(3) Number notation
An overbar on the name indicates that a signal or pin is active-low.
[Example] WDTOVF
Note: The bit names and sentences in the above figure are examples and do not refer to
specific data in this manual.
(4) Notation for active-low
When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in
CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in
CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000
and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time,
a f/4 clock is selected.
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Description of Registers
Each register description includes a bit chart, illustrating the arrangement of bits, and a table of
bits, describing the meanings of the bit settings. The standard format and notation for bit charts
and tables are described below.
Indicates the bit number or numbers.
In the case of a 32-bit register, the bits are arranged in order from 31 to 0. In the case
of a 16-bit register, the bits are arranged in order from 15 to 0.
Indicates the name of the bit or bit field.
When the number of bits has to be clearly indicated in the field, appropriate notation is
included (e.g., ASID[3:0]).
A reserved bit is indicated by "−".
Certain kinds of bits, such as those of timer counters, are not assigned bit names. In such
cases, the entry under Bit Name is blank.
(1) Bit
(2) Bit name
Indicates the value of each bit immediately after a power-on reset, i.e., the initial value.
0: The initial value is 0
1: The initial value is 1
−: The initial value is undefined
(3) Initial value
For each bit and bit field, this entry indicates whether the bit or field is readable or writable,
or both writing to and reading from the bit or field are impossible.
The notation is as follows:
R/W:
R/(W):
R:
W:
The bit or field is readable and writable.
The bit or field is readable and writable.
However, writing is only performed to flag clearing.
The bit or field is readable.
"R" is indicated for all reserved bits. When writing to the register, write
the value under Initial Value in the bit chart to reserved bits or fields.
The bit or field is writable.
Note: The bit names and sentences in the above figure are examples, and have nothing to do with the contents of this
manual.
(4) R/W
Describes the function of the bit or field and specifies the values for writing.
(5) Description
Bit
15
13 to 11
10
9
0
All 0
0
0
1
R
R/W
R
R
Address Identifier
These bits enable or disable the pin function.
Reserved
This bit is always read as 0.
Reserved
This bit is always read as 1.
−
ASID2 to
ASID0
−
−
−
Bit Name Initial Value R/W
Description
[Bit Chart]
[Table of Bits]
14
1514131211109876543210
Bit:
Initial value:
R/W:
0000001000000000
R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W
⎯
ASID2
⎯⎯⎯⎯⎯⎯
ACMP2Q
IFE
⎯
ASID1 ASID0 ACMP1 ACMP0
−
0
R
(1) (2) (3) (4)
(5)
Reserved
These bits are always read as 0.
All trademarks and registered trademarks are the property of their respective owners.
Page x of xl R01UH0134EJ0400 Rev. 4.00
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R01UH0134EJ0400 Rev. 4.00 Page xi of xl
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Contents
Section 1 Overview ................................................................................................ 1
1.1 SH7262/7264 Features .......................................................................................................... 1
1.2 Product Lineup .................................................................................................................... 12
1.3 Block Diagram .................................................................................................................... 14
1.4 Pin Assignment ................................................................................................................... 15
1.5 Pin Functions ...................................................................................................................... 19
1.6 List of Pins .......................................................................................................................... 29
Section 2 CPU ...................................................................................................... 49
2.1 Register Configuration ........................................................................................................ 49
2.1.1 General Registers ................................................................................................ 49
2.1.2 Control Registers ................................................................................................ 50
2.1.3 System Registers ................................................................................................. 52
2.1.4 Register Banks .................................................................................................... 53
2.1.5 Initial Values of Registers ................................................................................... 53
2.2 Data Formats ....................................................................................................................... 54
2.2.1 Data Format in Registers .................................................................................... 54
2.2.2 Data Formats in Memory .................................................................................... 54
2.2.3 Immediate Data Format ...................................................................................... 55
2.3 Instruction Features ............................................................................................................. 56
2.3.1 RISC-Type Instruction Set .................................................................................. 56
2.3.2 Addressing Modes .............................................................................................. 60
2.3.3 Instruction Format ............................................................................................... 65
2.4 Instruction Set ..................................................................................................................... 69
2.4.1 Instruction Set by Classification ......................................................................... 69
2.4.2 Data Transfer Instructions ................................................................................... 75
2.4.3 Arithmetic Operation Instructions ...................................................................... 79
2.4.4 Logic Operation Instructions .............................................................................. 82
2.4.5 Shift Instructions ................................................................................................. 83
2.4.6 Branch Instructions ............................................................................................. 84
2.4.7 System Control Instructions ................................................................................ 85
2.4.8 Floating-Point Operation Instructions ................................................................. 87
2.4.9 FPU-Related CPU Instructions ........................................................................... 89
2.4.10 Bit Manipulation Instructions ............................................................................. 90
2.5 Processing States ................................................................................................................. 92
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Section 3 Floating-Point Unit (FPU) ................................................................... 95
3.1 Features ............................................................................................................................... 95
3.2 Data Formats ....................................................................................................................... 96
3.2.1 Floating-Point Format ......................................................................................... 96
3.2.2 Non-Numbers (NaN) .......................................................................................... 99
3.2.3 Denormalized Numbers .................................................................................... 100
3.3 Register Descriptions ........................................................................................................ 101
3.3.1 Floating-Point Registers ................................................................................... 101
3.3.2 Floating-Point Status/Control Register (FPSCR) ............................................. 102
3.3.3 Floating-Point Communication Register (FPUL) ............................................. 104
3.4 Rounding .......................................................................................................................... 105
3.5 FPU Exceptions ................................................................................................................ 106
3.5.1 FPU Exception Sources .................................................................................... 106
3.5.2 FPU Exception Handling .................................................................................. 106
Section 4 Boot Mode ......................................................................................... 109
4.1 Features ............................................................................................................................. 109
4.2 Boot Mode and Pin Function Setting ................................................................................ 109
4.3 Operation .......................................................................................................................... 110
4.3.1 Boot Mode 0 ..................................................................................................... 110
4.3.2 Boot Modes 1 and 3 .......................................................................................... 110
4.3.3 Boot Mode 2 ..................................................................................................... 111
4.4 Notes ................................................................................................................................. 114
4.4.1 Boot Related Pins ............................................................................................. 114
Section 5 Clock Pulse Generator ....................................................................... 115
5.1 Features ............................................................................................................................. 115
5.2 Input/Output Pins .............................................................................................................. 118
5.3 Clock Operating Modes .................................................................................................... 119
5.4 Register Descriptions ........................................................................................................ 122
5.4.1 Frequency Control Register (FRQCR) ............................................................. 122
5.5 Changing the Frequency ................................................................................................... 125
5.5.1 Changing the Division Ratio ............................................................................. 125
5.6 Usage of the Clock Pins .................................................................................................... 126
5.6.1 In the Case of Inputting an External Clock ....................................................... 126
5.6.2 In the Case of Using a Crystal Resonator ......................................................... 127
5.6.3 In the Case of Not Using the Clock Pin ............................................................ 127
5.7 Oscillation Stabilizing Time ............................................................................................. 128
5.7.1 Oscillation Stabilizing Time of the On-chip Crystal Oscillator ........................ 128
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5.7.2 Oscillation Stabilizing Time of the PLL circuit ................................................ 128
5.8 Notes on Board Design ..................................................................................................... 129
5.8.1 Note on Using a PLL Oscillation Circuit .......................................................... 129
Section 6 Exception Handling ........................................................................... 131
6.1 Overview ........................................................................................................................... 131
6.1.1 Types of Exception Handling and Priority ........................................................ 131
6.1.2 Exception Handling Operations ........................................................................ 132
6.1.3 Exception Handling Vector Table ..................................................................... 134
6.2 Resets ................................................................................................................................ 137
6.2.1 Input/Output Pins .............................................................................................. 137
6.2.2 Types of Reset .................................................................................................. 137
6.2.3 Power-On Reset ................................................................................................ 139
6.2.4 Manual Reset .................................................................................................... 140
6.3 Address Errors .................................................................................................................. 142
6.3.1 Address Error Sources ...................................................................................... 142
6.3.2 Address Error Exception Handling ................................................................... 143
6.4 Register Bank Errors ......................................................................................................... 143
6.4.1 Register Bank Error Sources ............................................................................. 143
6.4.2 Register Bank Error Exception Handling ......................................................... 144
6.5 Interrupts ........................................................................................................................... 144
6.5.1 Interrupt Sources ............................................................................................... 144
6.5.2 Interrupt Priority Level ..................................................................................... 145
6.5.3 Interrupt Exception Handling ........................................................................... 146
6.6 Exceptions Triggered by Instructions ............................................................................... 147
6.6.1 Types of Exceptions Triggered by Instructions ................................................ 147
6.6.2 Trap Instructions ............................................................................................... 148
6.6.3 Slot Illegal Instructions ..................................................................................... 148
6.6.4 General Illegal Instructions ............................................................................... 149
6.6.5 Integer Division Exceptions .............................................................................. 149
6.6.6 FPU Exceptions ................................................................................................ 150
6.7 When Exception Sources Are Not Accepted .................................................................... 151
6.8 Stack Status after Exception Handling Ends ..................................................................... 151
6.9 Usage Notes ...................................................................................................................... 153
6.9.1 Value of Stack Pointer (SP) .............................................................................. 153
6.9.2 Value of Vector Base Register (VBR) .............................................................. 153
6.9.3 Address Errors Caused by Stacking of Address Error Exception Handling ..... 153
6.9.4 Interrupt Control via Modification of Interrupt Mask Bits ............................... 153
6.9.5 Note before Exception Handling Begins Running ............................................ 154
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Section 7 Interrupt Controller ............................................................................ 157
7.1 Features ............................................................................................................................. 157
7.2 Input/Output Pins .............................................................................................................. 159
7.3 Register Descriptions ........................................................................................................ 160
7.3.1 Interrupt Priority Registers 01, 02, 05 to 22
(IPR01, IPR02, IPR05 to IPR22) ..................................................................... 162
7.3.2 Interrupt Control Register 0 (ICR0) .................................................................. 164
7.3.3 Interrupt Control Register 1 (ICR1) .................................................................. 166
7.3.4 Interrupt Control Register 2 (ICR2) .................................................................. 167
7.3.5 IRQ Interrupt Request Register (IRQRR) ......................................................... 168
7.3.6 PINT Interrupt Enable Register (PINTER) ....................................................... 169
7.3.7 PINT Interrupt Request Register (PIRR) .......................................................... 170
7.3.8 Bank Control Register (IBCR) .......................................................................... 171
7.3.9 Bank Number Register (IBNR) ........................................................................ 172
7.4 Interrupt Sources ............................................................................................................... 173
7.4.1 NMI Interrupt .................................................................................................... 173
7.4.2 User Debugging Interface Interrupt .................................................................. 174
7.4.3 IRQ Interrupts ................................................................................................... 174
7.4.4 PINT Interrupts ................................................................................................. 175
7.4.5 On-Chip Peripheral Module Interrupts ............................................................. 176
7.5 Interrupt Exception Handling Vector Table and Priority .................................................. 177
7.6 Operation .......................................................................................................................... 191
7.6.1 Interrupt Operation Sequence ........................................................................... 191
7.6.2 Stack after Interrupt Exception Handling ......................................................... 194
7.7 Interrupt Response Time ................................................................................................... 195
7.8 Register Banks .................................................................................................................. 201
7.8.1 Banked Register and Input/Output of Banks .................................................... 202
7.8.2 Bank Save and Restore Operations ................................................................... 202
7.8.3 Save and Restore Operations after Saving to All Banks ................................... 204
7.8.4 Register Bank Exception .................................................................................. 205
7.8.5 Register Bank Error Exception Handling ......................................................... 205
7.9 Data Transfer with Interrupt Request Signals ................................................................... 206
7.9.1 Handling Interrupt Request Signals as Sources for
CPU Interrupt but Not Direct Memory Access Controller Activating .............. 207
7.9.2 Handling Interrupt Request Signals as Sources for
Activating Direct Memory Access Controller but Not CPU Interrupt .............. 207
7.10 Usage Note ....................................................................................................................... 208
7.10.1 Timing to Clear an Interrupt Source ................................................................. 208
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Section 8 Cache ................................................................................................. 209
8.1 Features ............................................................................................................................. 209
8.1.1 Cache Structure ................................................................................................. 209
8.2 Register Descriptions ........................................................................................................ 212
8.2.1 Cache Control Register 1 (CCR1) .................................................................... 212
8.2.2 Cache Control Register 2 (CCR2) .................................................................... 214
8.3 Operation .......................................................................................................................... 218
8.3.1 Searching Cache ............................................................................................... 218
8.3.2 Read Access ...................................................................................................... 220
8.3.3 Prefetch Operation (Only for Operand Cache) ................................................. 220
8.3.4 Write Operation (Only for Operand Cache) ...................................................... 221
8.3.5 Write-Back Buffer (Only for Operand Cache) .................................................. 221
8.3.6 Coherency of Cache and External Memory or
Large-Capacity On-Chip RAM ......................................................................... 223
8.4 Memory-Mapped Cache ................................................................................................... 224
8.4.1 Address Array ................................................................................................... 224
8.4.2 Data Array ........................................................................................................ 225
8.4.3 Usage Examples ................................................................................................ 227
8.4.4 Usage Notes ...................................................................................................... 228
Section 9 Bus State Controller ........................................................................... 229
9.1 Features ............................................................................................................................. 229
9.2 Input/Output Pins .............................................................................................................. 232
9.3 Area Overview .................................................................................................................. 234
9.3.1 Address Map ..................................................................................................... 234
9.3.2 Data Bus Width and Endian Specification of Each Area and
Related Pin Settings Depending on Boot Mode ................................................ 235
9.4 Register Descriptions ........................................................................................................ 237
9.4.1 Common Control Register (CMNCR) .............................................................. 239
9.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0 to 6) ................................. 242
9.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0 to 6) .............................. 247
9.4.4 SDRAM Control Register (SDCR) ................................................................... 280
9.4.5 Refresh Timer Control/Status Register (RTCSR) ............................................. 284
9.4.6 Refresh Timer Counter (RTCNT) ..................................................................... 286
9.4.7 Refresh Time Constant Register (RTCOR) ...................................................... 287
9.4.8 AC Characteristics Switching Register (ACSWR) ........................................... 288
9.4.9 AC Characteristics Switching Key Register (ACKEYR) ................................. 289
9.4.10 Sequence to Write to ACSWR .......................................................................... 290
9.5 Operation .......................................................................................................................... 291
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9.5.1 Endian/Access Size and Data Alignment .......................................................... 291
9.5.2 Normal Space Interface .................................................................................... 294
9.5.3 Access Wait Control ......................................................................................... 298
9.5.4 CSn Assert Period Expansion ........................................................................... 300
9.5.5 MPX-I/O Interface ............................................................................................ 301
9.5.6 SDRAM Interface ............................................................................................. 306
9.5.7 Burst ROM (Clocked Asynchronous) Interface ................................................ 342
9.5.8 SRAM Interface with Byte Selection ............................................................... 344
9.5.9 PCMCIA Interface ............................................................................................ 348
9.5.10 Burst ROM (Clocked Synchronous) Interface .................................................. 355
9.5.11 Wait between Access Cycles ............................................................................ 356
9.5.12 Bus Arbitration ................................................................................................. 364
9.5.13 Others ................................................................................................................ 366
Section 10 Direct Memory Access Controller ................................................... 371
10.1 Features ............................................................................................................................. 371
10.2 Input/Output Pins .............................................................................................................. 374
10.3 Register Descriptions ........................................................................................................ 375
10.3.1 DMA Source Address Registers (SAR) ............................................................ 384
10.3.2 DMA Destination Address Registers (DAR) .................................................... 384
10.3.3 DMA Transfer Count Registers (DMATCR) ................................................... 385
10.3.4 DMA Channel Control Registers (CHCR) ....................................................... 385
10.3.5 DMA Reload Source Address Registers (RSAR) ............................................. 396
10.3.6 DMA Reload Destination Address Registers (RDAR) ..................................... 396
10.3.7 DMA Reload Transfer Count Registers (RDMATCR) .................................... 397
10.3.8 DMA Operation Register (DMAOR) ............................................................... 398
10.3.9 DMA Extension Resource Selectors 0 to 7 (DMARS0 to DMARS7) .............. 402
10.4 Operation .......................................................................................................................... 408
10.4.1 Transfer Flow .................................................................................................... 408
10.4.2 DMA Transfer Requests ................................................................................... 410
10.4.3 Channel Priority ................................................................................................ 417
10.4.4 DMA Transfer Types ........................................................................................ 417
10.4.5 Number of Bus Cycles and DREQ Pin Sampling Timing ................................ 426
10.5 Usage Notes ...................................................................................................................... 430
10.5.1 Timing of DACK and TEND Outputs .............................................................. 430
10.5.2 Notes on Using Flag Bits .................................................................................. 430
Section 11 Multi-Function Timer Pulse Unit 2 ................................................. 431
11.1 Features ............................................................................................................................. 431
11.2 Input/Output Pins .............................................................................................................. 436
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11.3 Register Descriptions ........................................................................................................ 437
11.3.1 Timer Control Register (TCR) .......................................................................... 441
11.3.2 Timer Mode Register (TMDR) ......................................................................... 445
11.3.3 Timer I/O Control Register (TIOR) .................................................................. 448
11.3.4 Timer Interrupt Enable Register (TIER) ........................................................... 466
11.3.5 Timer Status Register (TSR) ............................................................................. 469
11.3.6 Timer Buffer Operation Transfer Mode Register (TBTM) ............................... 474
11.3.7 Timer Input Capture Control Register (TICCR) ............................................... 475
11.3.8 Timer A/D Converter Start Request Control Register (TADCR) ..................... 477
11.3.9 Timer A/D Converter Start Request Cycle Set Registers
(TADCORA_4 and TADCORB_4) .................................................................. 480
11.3.10 Timer A/D Converter Start Request Cycle Set Buffer Registers
(TADCOBRA_4 and TADCOBRB_4)............................................................. 480
11.3.11 Timer Counter (TCNT) ..................................................................................... 481
11.3.12 Timer General Register (TGR) ......................................................................... 481
11.3.13 Timer Start Register (TSTR) ............................................................................ 482
11.3.14 Timer Synchronous Register (TSYR) ............................................................... 483
11.3.15 Timer Read/Write Enable Register (TRWER) ................................................. 485
11.3.16 Timer Output Master Enable Register (TOER) ................................................ 486
11.3.17 Timer Output Control Register 1 (TOCR1) ...................................................... 488
11.3.18 Timer Output Control Register 2 (TOCR2) ...................................................... 491
11.3.19 Timer Output Level Buffer Register (TOLBR) ................................................ 494
11.3.20 Timer Gate Control Register (TGCR) .............................................................. 495
11.3.21 Timer Subcounter (TCNTS) ............................................................................. 497
11.3.22 Timer Dead Time Data Register (TDDR) ......................................................... 498
11.3.23 Timer Cycle Data Register (TCDR) ................................................................. 498
11.3.24 Timer Cycle Buffer Register (TCBR) ............................................................... 499
11.3.25 Timer Interrupt Skipping Set Register (TITCR) ............................................... 499
11.3.26 Timer Interrupt Skipping Counter (TITCNT) ................................................... 501
11.3.27 Timer Buffer Transfer Set Register (TBTER) .................................................. 502
11.3.28 Timer Dead Time Enable Register (TDER) ...................................................... 504
11.3.29 Timer Waveform Control Register (TWCR) .................................................... 505
11.3.30 Bus Master Interface ......................................................................................... 506
11.4 Operation .......................................................................................................................... 507
11.4.1 Basic Functions ................................................................................................. 507
11.4.2 Synchronous Operation ..................................................................................... 513
11.4.3 Buffer Operation ............................................................................................... 515
11.4.4 Cascaded Operation .......................................................................................... 519
11.4.5 PWM Modes ..................................................................................................... 524
11.4.6 Phase Counting Mode ....................................................................................... 529
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11.4.7 Reset-Synchronized PWM Mode ..................................................................... 536
11.4.8 Complementary PWM Mode ............................................................................ 539
11.4.9 A/D Converter Start Request Delaying Function .............................................. 578
11.4.10 TCNT Capture at Crest and/or Trough in Complementary PWM Operation ... 582
11.5 Interrupt Sources ............................................................................................................... 583
11.5.1 Interrupt Sources and Priorities ........................................................................ 583
11.5.2 Activation of Direct Memory Access Controller .............................................. 585
11.5.3 A/D Converter Activation ................................................................................. 585
11.6 Operation Timing .............................................................................................................. 587
11.6.1 Input/Output Timing ......................................................................................... 587
11.6.2 Interrupt Signal Timing .................................................................................... 594
11.7 Usage Notes ...................................................................................................................... 598
11.7.1 Module Standby Mode Setting ......................................................................... 598
11.7.2 Input Clock Restrictions ................................................................................... 598
11.7.3 Caution on Period Setting ................................................................................. 599
11.7.4 Contention between TCNT Write and Clear Operations .................................. 599
11.7.5 Contention between TCNT Write and Increment Operations ........................... 600
11.7.6 Contention between TGR Write and Compare Match ...................................... 601
11.7.7 Contention between Buffer Register Write and Compare Match ..................... 602
11.7.8 Contention between Buffer Register Write and TCNT Clear ........................... 603
11.7.9 Contention between TGR Read and Input Capture ........................................... 604
11.7.10 Contention between TGR Write and Input Capture .......................................... 605
11.7.11 Contention between Buffer Register Write and Input Capture ......................... 606
11.7.12 TCNT2 Write and Overflow/Underflow Contention in
Cascade Connection .......................................................................................... 606
11.7.13 Counter Value during Complementary PWM Mode Stop ................................ 608
11.7.14 Buffer Operation Setting in Complementary PWM Mode ............................... 608
11.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag .............. 609
11.7.16 Overflow Flags in Reset Synchronous PWM Mode ......................................... 610
11.7.17 Contention between Overflow/Underflow and Counter Clearing ..................... 611
11.7.18 Contention between TCNT Write and Overflow/Underflow ............................ 612
11.7.19 Cautions on Transition from Normal Operation or
PWM Mode 1 to Reset-Synchronized PWM Mode .......................................... 612
11.7.20 Output Level in Complementary PWM Mode and
Reset-Synchronized PWM Mode ..................................................................... 613
11.7.21 Interrupts in Module Standby Mode ................................................................. 613
11.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection ........ 613
11.7.23 Notes on Output Waveform Control During Synchronous Counter Clearing
in Complementary PWM Mode ........................................................................ 614
11.8 Output Pin Initialization for Multi-Function Timer Pulse Unit 2 ..................................... 616
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11.8.1 Operating Modes ............................................................................................... 616
11.8.2 Reset Start Operation ........................................................................................ 616
11.8.3 Operation in Case of Re-Setting Due to Error during Operation, etc. .............. 617
11.8.4 Overview of Initialization Procedures and Mode Transitions in Case of
Error during Operation, etc. .............................................................................. 618
Section 12 Compare Match Timer ..................................................................... 649
12.1 Features ............................................................................................................................. 649
12.2 Register Descriptions ........................................................................................................ 650
12.2.1 Compare Match Timer Start Register (CMSTR) .............................................. 651
12.2.2 Compare Match Timer Control/Status Register (CMCSR) .............................. 652
12.2.3 Compare Match Counter (CMCNT) ................................................................. 654
12.2.4 Compare Match Constant Register (CMCOR) ................................................. 654
12.3 Operation .......................................................................................................................... 655
12.3.1 Interval Count Operation .................................................................................. 655
12.3.2 CMCNT Count Timing ..................................................................................... 655
12.4 Interrupts ........................................................................................................................... 656
12.4.1 Interrupt Sources and DMA Transfer Requests ................................................ 656
12.4.2 Timing of Compare Match Flag Setting ........................................................... 656
12.4.3 Timing of Compare Match Flag Clearing ......................................................... 657
12.5 Usage Notes ...................................................................................................................... 658
12.5.1 Conflict between Write and Compare-Match Processes of CMCNT ............... 658
12.5.2 Conflict between Word-Write and Count-Up Processes of CMCNT ............... 659
12.5.3 Conflict between Byte-Write and Count-Up Processes of CMCNT ................. 660
12.5.4 Compare Match between CMCNT and CMCOR ............................................. 660
Section 13 Watchdog Timer .............................................................................. 661
13.1 Features ............................................................................................................................. 661
13.2 Input/Output Pin ............................................................................................................... 662
13.3 Register Descriptions ........................................................................................................ 663
13.3.1 Watchdog Timer Counter (WTCNT) ................................................................ 663
13.3.2 Watchdog Timer Control/Status Register (WTCSR) ........................................ 664
13.3.3 Watchdog Reset Control/Status Register (WRCSR) ........................................ 667
13.3.4 Notes on Register Access .................................................................................. 668
13.4 Usage ................................................................................................................................ 670
13.4.1 Canceling Software Standby Mode ................................................................... 670
13.4.2 Using Watchdog Timer Mode........................................................................... 670
13.4.3 Using Interval Timer Mode .............................................................................. 672
13.5 Usage Notes ...................................................................................................................... 673
13.5.1 Timer Variation ................................................................................................. 673
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13.5.2 Prohibition against Setting H'FF to WTCNT .................................................... 673
13.5.3 Interval Timer Overflow Flag ........................................................................... 673
13.5.4 System Reset by WDTOVF Signal ................................................................... 674
13.5.5 Manual Reset in Watchdog Timer Mode .......................................................... 674
13.5.6 Internal Reset in Watchdog Timer Mode .......................................................... 674
Section 14 Realtime Clock ................................................................................ 675
14.1 Features ............................................................................................................................. 675
14.2 Input/Output Pin ............................................................................................................... 677
14.3 Register Descriptions ........................................................................................................ 677
14.3.1 64-Hz Counter (R64CNT) ................................................................................ 678
14.3.2 Second Counter (RSECCNT) ........................................................................... 679
14.3.3 Minute Counter (RMINCNT) ........................................................................... 680
14.3.4 Hour Counter (RHRCNT) ................................................................................ 681
14.3.5 Day of Week Counter (RWKCNT) .................................................................. 682
14.3.6 Date Counter (RDAYCNT) .............................................................................. 683
14.3.7 Month Counter (RMONCNT) .......................................................................... 684
14.3.8 Year Counter (RYRCNT) ................................................................................. 685
14.3.9 Second Alarm Register (RSECAR) .................................................................. 686
14.3.10 Minute Alarm Register (RMINAR) .................................................................. 687
14.3.11 Hour Alarm Register (RHRAR) ....................................................................... 688
14.3.12 Day of Week Alarm Register (RWKAR) ......................................................... 689
14.3.13 Date Alarm Register (RDAYAR) ..................................................................... 690
14.3.14 Month Alarm Register (RMONAR) ................................................................. 691
14.3.15 Year Alarm Register (RYRAR) ........................................................................ 692
14.3.16 Control Register 1 (RCR1) ............................................................................... 693
14.3.17 Control Register 2 (RCR2) ............................................................................... 695
14.3.18 Control Register 3 (RCR3) ............................................................................... 697
14.3.19 Control Register 5 (RCR5) ............................................................................... 698
14.3.20 Frequency Register H/L (RFRH/L) .................................................................. 699
14.4 Operation .......................................................................................................................... 701
14.4.1 Initial Settings of Registers after Power-On ..................................................... 701
14.4.2 Setting Time...................................................................................................... 701
14.4.3 Reading Time .................................................................................................... 702
14.4.4 Alarm Function ................................................................................................. 703
14.5 Usage Notes ...................................................................................................................... 704
14.5.1 Register Writing during Count.......................................................................... 704
14.5.2 Use of Realtime Clock Periodic Interrupts ....................................................... 704
14.5.3 Transition to Standby Mode after Setting Register ........................................... 704
14.5.4 Usage Notes when Writing to and Reading the Register .................................. 705
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