2. Hitachi
  3. HD6432628
HD6432628

Hitachi HD6432628, H8S/2627, H8S/2628, HD6432627, HD64F2628 User manual

  • Hello! I am an AI chatbot trained to assist you with the Hitachi HD6432628 User manual. I’ve already reviewed the document and can help you find the information you need or explain it in simple terms. Just ask your questions, and providing more details will help me assist you more effectively!
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
To all our customers
Cautions
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better
and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corporation product best suited to the customer's application; they do not convey any
license under any intellectual property rights, or any other rights, belonging to Renesas Technology
Corporation or a third party.
2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any
third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corporation without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corporation
or an authorized Renesas Technology Corporation product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss
rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corporation by various
means, including the Renesas Technology Corporation Semiconductor home page
(http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams,
charts, programs, and algorithms, please be sure to evaluate all information as a total system before
making a final decision on the applicability of the information and products. Renesas Technology
Corporation assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.
5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device
or system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor
when considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in
whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be
exported under a license from the Japanese government and cannot be imported into a country other
than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.
8. Please contact Renesas Technology Corporation for further details on these materials or the products
contained therein.
Hitachi 16-bit Single-Chip Microcomputer
H8S/2628 Series
H8S/2628
HD64F2628, HD6432628
H8S/2627
HD6432627
Hardware Manual
ADE-602-278
Rev. 1.0
09/13/02
Hitachi, Ltd.
Rev. 1.0, 09/02, page
ii
of
xxxvi
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s
patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi
semiconductor products.
Rev. 1.0, 09/02 page
iii
of
xxxvi
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass-
through current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product’s state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system’s
operation is not guaranteed if they are accessed.
Rev. 1.0, 09/02, page
iv
of
xxxvi
Configuration of This Manual
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 1.0, 09/02 page
v
of
xxxvi
Preface
The H8S/2628 Series are single-chip microcomputers made up of the high-speed H8S/2600 CPU
as its core, and the peripheral functions required to configure a system. The H8S/2600 CPU has an
instruction set that is compatible with the H8/300 and H8/300H CPUs.
This LSI is equipped with a data transfer controller (DTC), ROM and RAM memory, a PC break
controller (PBC), a 16-bit timer pulse unit (TPU), a programmable pulse generator (PPG), a
watchdog timer (WDT), a serial communication interface (SCI), a Hitachi controller area network
(HCAN), a synchronous serial communication unit (SSU), an A/D converter, and I/O ports as on-
chip peripheral modules required for system configuration. This LSI is suitable for use as an
embedded microcomputer for high-level control systems. A single-power flash memory (F-
ZTAT
TM
) version is available for this LSI's ROM. This provides flexibility as it can be
reprogrammed in no time to cope with all situations from the early stages of mass production to
full-scale mass production. This is particularly applicable to application devices with
specifications that will most probably change.
Note:* F-ZTAT
TM
is a trademark of Hitachi, Ltd.
Target Users: This manual was written for users who will be using the H8S/2628 Series in the
design of application systems. Target users are expected to understand the
fundamentals of electrical circuits, logical circuits, and microcomputers.
Objective: This manual was written to explain the hardware functions and electrical
characteristics of the H8S/2628 Series to the target users.
Refer to the H8S/2600 Series Programming Manual for a detailed description of
the instruction set.
Notes on reading this manual:
• In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
• In order to understand the details of the CPU's functions
Read the H8/300H Series Programming Manual.
• In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 22,
List of Registers.
Rev. 1.0, 09/02, page
vi
of
xxxvi
Example: Register name: The following notation is used for cases when the same or a
similar function, e.g. 16-bit timer pulse unit or serial
communication, is implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
Bit order: The MSB is on the left and the LSB is on the right.
Notes:
Related Manuals: The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.hitachisemiconductor.com/
H8S/2628 Series manuals:
Manual Title ADE No.
H8S/2628 Series Hardware Manual This manual
H8S/2600 Series, H8S/2000 Series Programming Manual ADE-602-083
User's manuals for development tools:
Manual Title ADE No.
H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor
User's Manual
ADE-702-247
H8S, H8/300 Series Simulator/Debugger User's Manual ADE-702-282
H8S, H8/300 Series Hitachi Embedded Workshop, Hitachi Debugging
Interface Tutorial
ADE-702-231
Hitachi Embedded Workshop User's Manual ADE-702-201
Rev. 1.0, 09/02 page
vii
of
xxxvi
Contents
Section 1 Overview........................................................................................... 1
1.1 Overview...........................................................................................................................1
1.2 Internal Block Diagram.....................................................................................................2
1.3 Pin Arrangement...............................................................................................................3
1.4 Pin Functions ....................................................................................................................4
Section 2 CPU................................................................................................... 9
2.1 Features.............................................................................................................................9
2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU ..................................10
2.1.2 Differences from H8/300 CPU.............................................................................11
2.1.3 Differences from H8/300H CPU..........................................................................11
2.2 CPU Operating Modes......................................................................................................12
2.2.1 Normal Mode.......................................................................................................12
2.2.2 Advanced Mode...................................................................................................13
2.3 Address Space...................................................................................................................16
2.4 Registers............................................................................................................................17
2.4.1 General Registers.................................................................................................18
2.4.2 Program Counter (PC) .........................................................................................19
2.4.3 Extended Control Register (EXR) .......................................................................19
2.4.4 Condition-Code Register (CCR)..........................................................................20
2.4.5 Multiply-Accumulate Register (MAC)................................................................21
2.4.6 Initial Values of CPU Registers...........................................................................21
2.5 Data Formats.....................................................................................................................22
2.5.1 General Register Data Formats............................................................................22
2.5.2 Memory Data Formats.........................................................................................24
2.6 Instruction Set...................................................................................................................25
2.6.1 Table of Instructions Classified by Function .......................................................26
2.6.2 Basic Instruction Formats ....................................................................................36
2.7 Addressing Modes and Effective Address Calculation.....................................................38
2.7.1 Register DirectRn.............................................................................................38
2.7.2 Register Indirect@ERn....................................................................................38
2.7.3 Register Indirect with Displacement@(d:16, ERn) or @(d:32, ERn)..............38
2.7.4 Register Indirect with Post-Increment or Pre-Decrement@ERn+ or @-ERn..39
2.7.5 Absolute Address@aa:8, @aa:16, @aa:24, or @aa:32....................................39
2.7.6 Immediate#xx:8, #xx:16, or #xx:32.................................................................40
2.7.7 Program-Counter Relative@(d:8, PC) or @(d:16, PC)....................................40
2.7.8 Memory Indirect@@aa:8 ................................................................................40
2.7.9 Effective Address Calculation..............................................................................41
2.8 Processing States...............................................................................................................44
Rev. 1.0, 09/02, page
viii
of
xxxvi
2.9 Usage Note........................................................................................................................45
2.9.1 Notes on Using the Bit Operation Instruction......................................................45
Section 3 MCU Operating Modes.....................................................................47
3.1 Operating Mode Selection ................................................................................................47
3.2 Register Descriptions........................................................................................................47
3.2.1 Mode Control Register (MDCR) .........................................................................48
3.2.2 System Control Register (SYSCR)......................................................................49
3.3 Pin Functions in Each Operating Mode............................................................................50
3.4 Address Map.....................................................................................................................51
Section 4 Exception Handling...........................................................................53
4.1 Exception Handling Types and Priority............................................................................53
4.2 Exception Sources and Exception Vector Table...............................................................53
4.3 Reset .................................................................................................................................55
4.3.1 Reset Exception Handling....................................................................................55
4.3.2 Interrupts after Reset............................................................................................57
4.3.3 State of On-Chip Peripheral Modules after Reset Release...................................57
4.4 Traces................................................................................................................................58
4.5 Interrupts...........................................................................................................................58
4.6 Trap Instruction.................................................................................................................59
4.7 Stack Status after Exception Handling..............................................................................60
4.8 Usage Note........................................................................................................................61
Section 5 Interrupt Controller............................................................................63
5.1 Features.............................................................................................................................63
5.2 Input/Output Pins..............................................................................................................65
5.3 Register Descriptions........................................................................................................65
5.3.1 Interrupt Priority Registers A to M (IPRA to IPRM)...........................................66
5.3.2 IRQ Enable Register (IER)..................................................................................67
5.3.3 IRQ Sense Control Registers H and L (ISCRH, ISCRL).....................................68
5.3.4 IRQ Status Register (ISR)....................................................................................70
5.4 Interrupt Sources...............................................................................................................71
5.4.1 External Interrupts ...............................................................................................71
5.4.2 Internal Interrupts ................................................................................................72
5.5 Interrupt Exception Handling Vector Table......................................................................72
5.6 Interrupt Control Modes and Interrupt Operation.............................................................76
5.6.1 Interrupt Control Mode 0.....................................................................................76
5.6.2 Interrupt Control Mode 2.....................................................................................78
5.6.3 Interrupt Exception Handling Sequence..............................................................79
5.6.4 Interrupt Response Times....................................................................................81
5.6.5 DTC Activation by Interrupt................................................................................82
5.7 Usage Notes......................................................................................................................82
Rev. 1.0, 09/02 page
ix
of
xxxvi
5.7.1 Conflict between Interrupt Generation and Disabling .........................................82
5.7.2 Instructions that Disable Interrupts......................................................................83
5.7.3 When Interrupts Are Disabled .............................................................................83
5.7.4 Interrupts during Execution of EEPMOV Instruction..........................................84
Section 6 PC Break Controller (PBC) .............................................................. 85
6.1 Features.............................................................................................................................85
6.2 Register Descriptions........................................................................................................86
6.2.1 Break Address Register A (BARA).....................................................................86
6.2.2 Break Address Register B (BARB)......................................................................87
6.2.3 Break Control Register A (BCRA)......................................................................87
6.2.4 Break Control Register B (BCRB).......................................................................88
6.3 Operation...........................................................................................................................88
6.3.1 PC Break Interrupt Due to Instruction Fetch .......................................................88
6.3.2 PC Break Interrupt Due to Data Access...............................................................88
6.3.3 PC Break Operation at Consecutive Data Transfer..............................................89
6.3.4 Operation in Transitions to Power-Down Modes.................................................89
6.3.5 When Instruction Execution Is Delayed by One State.........................................90
6.4 Usage Notes......................................................................................................................91
6.4.1 Module Stop Mode Setting..................................................................................91
6.4.2 PC Break Interrupts..............................................................................................91
6.4.3 CMFA and CMFB ...............................................................................................91
6.4.4 PC Break Interrupt when DTC Is Bus Master......................................................91
6.4.5 PC Break Set for Instruction Fetch at Address Following
BSR, JSR, JMP, TRAPA, RTE, or RTS Instruction............................................91
6.4.6 I Bit Set by LDC, ANDC, ORC, or XORC Instruction .......................................91
6.4.7 PC Break Set for Instruction Fetch at Address Following Bcc Instruction..........92
6.4.8 PC Break Set for Instruction Fetch at Branch Destination Address of Bcc
Instruction ............................................................................................................92
Section 7 Bus Controller................................................................................... 93
7.1 Basic Timing.....................................................................................................................93
7.1.1 On-Chip Memory Access Timing (ROM, RAM)................................................93
7.1.2 On-Chip Support Module Access Timing............................................................94
7.1.3 On-Chip HCAN Module Access Timing.............................................................94
7.1.4 On-chip SSU Module and Realtime Input Port Data Register Access Timing....95
7.2 Bus Arbitration..................................................................................................................95
7.2.1 Order of Priority of the Bus Masters....................................................................95
7.2.2 Bus Transfer Timing............................................................................................96
Section 8 Data Transfer Controller (DTC) ....................................................... 97
8.1 Features.............................................................................................................................97
8.2 Register Descriptions........................................................................................................99
Rev. 1.0, 09/02, page
x
of
xxxvi
8.2.1 DTC Mode Register A (MRA) ............................................................................100
8.2.2 DTC Mode Register B (MRB).............................................................................101
8.2.3 DTC Source Address Register (SAR)..................................................................101
8.2.4 DTC Destination Address Register (DAR)..........................................................101
8.2.5 DTC Transfer Count Register A (CRA) ..............................................................101
8.2.6 DTC Transfer Count Register B (CRB)...............................................................102
8.2.7 DTC Enable Registers (DTCER).........................................................................102
8.2.8 DTC Vector Register (DTVECR)........................................................................103
8.3 Activation Sources............................................................................................................103
8.4 Location of Register Information and DTC Vector Table................................................104
8.5 Operation ..........................................................................................................................107
8.5.1 Normal Mode.......................................................................................................109
8.5.2 Repeat Mode........................................................................................................110
8.5.3 Block Transfer Mode...........................................................................................111
8.5.4 Chain Transfer.....................................................................................................112
8.5.5 Interrupts..............................................................................................................113
8.5.6 Operation Timing.................................................................................................113
8.5.7 Number of DTC Execution States .......................................................................114
8.6 Procedures for Using DTC................................................................................................116
8.6.1 Activation by Interrupt.........................................................................................116
8.6.2 Activation by Software........................................................................................116
8.7 Examples of Use of the DTC............................................................................................116
8.7.1 Normal Mode.......................................................................................................116
8.7.2 Chain Transfer.....................................................................................................117
8.7.3 Software Activation.............................................................................................118
8.8 Usage Notes......................................................................................................................118
8.8.1 Module Stop Mode Setting..................................................................................118
8.8.2 On-Chip RAM .....................................................................................................119
8.8.3 DTCE Bit Setting.................................................................................................119
Section 9 I/O Ports.............................................................................................121
9.1 Port 1.................................................................................................................................125
9.1.1 Port 1 Data Direction Register (P1DDR).............................................................125
9.1.2 Port 1 Data Register (P1DR)................................................................................126
9.1.3 Port 1 Register (PORT1)......................................................................................126
9.1.4 Pin Functions.......................................................................................................127
9.2 Port 3.................................................................................................................................129
9.2.1 Port 3 Data Direction Register (P3DDR).............................................................129
9.2.2 Port 3 Data Register (P3DR)................................................................................130
9.2.3 Port 3 Register (PORT3)......................................................................................130
9.2.4 Port 3 Open-Drain Control Register (P3ODR)....................................................131
9.2.5 Pin Functions.......................................................................................................131
9.3 Port 4.................................................................................................................................133
Rev. 1.0, 09/02 page
xi
of
xxxvi
9.3.1 Port 4 Register (PORT4)......................................................................................133
9.4 Port 7.................................................................................................................................133
9.4.1 Port 7 Data Direction Register (P7DDR).............................................................134
9.4.2 Port 7 Data Register (P7DR)................................................................................134
9.4.3 Port 7 Register (PORT7)......................................................................................134
9.4.4 Pin Functions .......................................................................................................135
9.5 Port 9.................................................................................................................................136
9.5.1 Port 9 Register (PORT9)......................................................................................136
9.6 Port A................................................................................................................................138
9.6.1 Port A Data Direction Register (PADDR)...........................................................138
9.6.2 Port A Data Register (PADR)..............................................................................139
9.6.3 Port A Register (PORTA)....................................................................................139
9.6.4 Port A Pull-Up MOS Control Register (PAPCR)................................................140
9.6.5 Port A Open-Drain Control Register (PAODR) ..................................................140
9.6.6 Pin Functions .......................................................................................................141
9.7 Port B................................................................................................................................142
9.7.1 Port B Data Direction Register (PBDDR)............................................................142
9.7.2 Port B Data Register (PBDR) ..............................................................................143
9.7.3 Port B Register (PORTB) ....................................................................................143
9.7.4 Port B Pull-Up MOS Control Register (PBPCR).................................................144
9.7.5 Port B Open-Drain Control Register (PBODR)...................................................144
9.7.6 Pin Functions .......................................................................................................145
9.8 Port C................................................................................................................................146
9.8.1 Port C Data Direction Register (PCDDR)............................................................147
9.8.2 Port C Data Register (PCDR) ..............................................................................147
9.8.3 Port C Register (PORTC) ....................................................................................148
9.8.4 Port C Pull-Up MOS Control Register (PCPCR).................................................148
9.8.5 Port C Open-Drain Control Register (PCODR)...................................................148
9.8.6 Pin Functions .......................................................................................................149
9.9 Port D................................................................................................................................152
9.9.1 Port D Data Direction Register (PDDDR)...........................................................152
9.9.2 Port D Data Register (PDDR)..............................................................................153
9.9.3 Port D Register (PORTD)....................................................................................153
9.9.4 Port D Pull-up MOS Control Register (PDPCR).................................................153
9.9.5 Port D RealTime Input Data Register (PDRTIDR)..............................................154
9.10 Port F.................................................................................................................................154
9.10.1 Port F Data Direction Register (PFDDR) ............................................................155
9.10.2 Port F Data Register (PFDR)...............................................................................156
9.10.3 Port F Register (PORTF) .....................................................................................156
9.10.4 Pin Functions .......................................................................................................157
Section 10 16-Bit Timer Pulse Unit (TPU)....................................................... 159
10.1 Features.............................................................................................................................159
Rev. 1.0, 09/02, page
xii
of
xxxvi
10.2 Input/Output Pins..............................................................................................................163
10.3 Register Descriptions........................................................................................................164
10.3.1 Timer Control Register (TCR).............................................................................166
10.3.2 Timer Mode Register (TMDR)............................................................................171
10.3.3 Timer I/O Control Register (TIOR).....................................................................173
10.3.4 Timer Interrupt Enable Register (TIER)..............................................................190
10.3.5 Timer Status Register (TSR)................................................................................192
10.3.6 Timer Counter (TCNT)........................................................................................195
10.3.7 Timer General Register (TGR)............................................................................195
10.3.8 Timer Start Register (TSTR) ...............................................................................195
10.3.9 Timer Synchro Register (TSYR) .........................................................................196
10.4 Operation ..........................................................................................................................196
10.4.1 Basic Functions....................................................................................................196
10.4.2 Synchronous Operation........................................................................................203
10.4.3 Buffer Operation..................................................................................................204
10.4.4 Cascaded Operation.............................................................................................208
10.4.5 PWM Modes........................................................................................................209
10.4.6 Phase Counting Mode..........................................................................................214
10.5 Interrupt Sources...............................................................................................................221
10.6 DTC Activation.................................................................................................................223
10.7 A/D Converter Activation.................................................................................................223
10.8 Operation Timing..............................................................................................................224
10.8.1 Input/Output Timing............................................................................................224
10.8.2 Interrupt Signal Timing........................................................................................228
10.9 Usage Notes......................................................................................................................231
10.9.1 Module Stop Mode Setting..................................................................................231
10.9.2 Input Clock Restrictions ......................................................................................231
10.9.3 Caution on Period Setting....................................................................................231
10.9.4 Conflict between TCNT Write and Clear Operations..........................................232
10.9.5 Conflict between TCNT Write and Increment Operations ..................................233
10.9.6 Conflict between TGR Write and Compare Match..............................................234
10.9.7 Conflict between Buffer Register Write and Compare Match.............................235
10.9.8 Conflict between TGR Read and Input Capture..................................................236
10.9.9 Conflict between TGR Write and Input Capture.................................................237
10.9.10 Conflict between Buffer Register Write and Input Capture.................................238
10.9.11 Conflict between Overflow/Underflow and Counter Clearing ............................239
10.9.12 Conflict between TCNT Write and Overflow/Underflow ...................................240
10.9.13 Multiplexing of I/O Pins......................................................................................240
10.9.14 Interrupts in Module Stop Mode..........................................................................240
Section 11 8-Bit Timers.....................................................................................241
11.1 Features.............................................................................................................................241
11.2 Input/Output Pins..............................................................................................................242
Rev. 1.0, 09/02 page
xiii
of
xxxvi
11.3 Register Descriptions........................................................................................................243
11.3.1 Timer Counters (TCNT) ......................................................................................244
11.3.2 Time Constant Registers A (TCORA).................................................................244
11.3.3 Time Constant Registers B (TCORB)..................................................................244
11.3.4 Timer Control Registers (TCR) ...........................................................................244
11.3.5 Timer Control/Status Registers (TCSR) ..............................................................247
11.4 Operation...........................................................................................................................251
11.4.1 Pulse Output.........................................................................................................251
11.5 Operation Timing..............................................................................................................252
11.5.1 TCNT Incrementation Timing.............................................................................252
11.5.2 Timing of CMFA and CMFB Setting When a Compare-Match Occurs..............253
11.5.3 Timing of Timer Output When a Compare-Match Occurs..................................254
11.5.4 Timing of Compare-Match Clear When a Compare-Match Occurs ....................254
11.5.5 TCNT External Reset Timing..............................................................................254
11.5.6 Timing of Overflow Flag (OVF) Setting.............................................................255
11.6 Operation with Cascaded Connection...............................................................................255
11.6.1 16-Bit Count Mode..............................................................................................255
11.6.2 Compare-Match Count Mode ..............................................................................256
11.7 Interrupt Sources...............................................................................................................256
11.7.1 Interrupt Sources and DTC Activation ................................................................256
11.7.2 A/D Converter Activation....................................................................................257
11.8 Usage Notes......................................................................................................................258
11.8.1 Conflict between TCNT Write and Clear ............................................................258
11.8.2 Conflict between TCNT Write and Increment.....................................................258
11.8.3 Conflict between TCOR Write and Compare-Match...........................................259
11.8.4 Conflict between Compare-Matches A and B......................................................260
11.8.5 Switching of Internal Clocks and TCNT Operation.............................................260
11.8.6 Conflict between Interrupts and Module Stop Mode...........................................262
11.8.7 Notes on Cascaded Connection............................................................................262
Section 12 Programmable Pulse Generator (PPG) ........................................... 263
12.1 Features.............................................................................................................................263
12.2 Input/Output Pins..............................................................................................................265
12.3 Register Descriptions........................................................................................................265
12.3.1 Next Data Enable Registers H, L (NDERH, NDERL).........................................266
12.3.2 Output Data Registers H, L (PODRH, PODRL)..................................................267
12.3.3 Next Data Registers H, L (NDRH, NDRL) .........................................................268
12.3.4 PPG Output Control Register (PCR)....................................................................270
12.3.5 PPG Output Mode Register (PMR)......................................................................271
12.4 Operation...........................................................................................................................272
12.4.1 Overview..............................................................................................................272
12.4.2 Output Timing......................................................................................................273
12.4.3 Sample Setup Procedure for Normal Pulse Output..............................................274
Rev. 1.0, 09/02, page
xiv
of
xxxvi
12.4.4 Example of Normal Pulse Output (Example of Five-Phase Pulse Output)..........275
12.4.5 Non-Overlapping Pulse Output............................................................................276
12.4.6 Sample Setup Procedure for Non-Overlapping Pulse Output..............................278
12.4.7 Example of Non-Overlapping Pulse Output
(Example of Four-Phase Complementary Non-Overlapping Output)..................279
12.4.8 Inverted Pulse Output ..........................................................................................281
12.4.9 Pulse Output Triggered by Input Capture............................................................282
12.5 Usage Notes......................................................................................................................282
12.5.1 Module Stop Mode Setting..................................................................................282
12.5.2 Operation of Pulse Output Pins............................................................................282
Section 13 Watchdog Timer..............................................................................283
13.1 Features.............................................................................................................................283
13.2 Register Descriptions........................................................................................................284
13.2.1 Timer Counter (TCNT)........................................................................................284
13.2.2 Timer Control/Status Register (TCSR)................................................................284
13.2.3 Reset Control/Status Register (RSTCSR)............................................................286
13.3 Operation ..........................................................................................................................287
13.3.1 Watchdog Timer Mode Operation.......................................................................287
13.3.2 Interval Timer Mode............................................................................................287
13.4 Interrupts...........................................................................................................................288
13.5 Usage Notes......................................................................................................................288
13.5.1 Notes on Register Access.....................................................................................288
13.5.2 Conflict between Timer Counter (TCNT) Write and Increment..........................289
13.5.3 Changing Value of CKS2 to CKS0......................................................................290
13.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode................290
13.5.5 Internal Reset in Watchdog Timer Mode.............................................................290
13.5.6 OVF Flag Clearing in Interval Timer Mode........................................................290
Section 14 Serial Communication Interface (SCI)............................................291
14.1 Features.............................................................................................................................291
14.2 Input/Output Pins..............................................................................................................293
14.3 Register Descriptions........................................................................................................293
14.3.1 Receive Shift Register (RSR) ..............................................................................294
14.3.2 Receive Data Register (RDR)..............................................................................294
14.3.3 Transmit Data Register (TDR).............................................................................294
14.3.4 Transmit Shift Register (TSR).............................................................................294
14.3.5 Serial Mode Register (SMR) ...............................................................................295
14.3.6 Serial Control Register (SCR)..............................................................................299
14.3.7 Serial Status Register (SSR) ................................................................................302
14.3.8 Smart Card Mode Register (SCMR)....................................................................307
14.3.9 Bit Rate Register (BRR) ......................................................................................308
14.4 Operation in Asynchronous Mode ....................................................................................315
Rev. 1.0, 09/02 page
xv
of
xxxvi
14.4.1 Data Transfer Format...........................................................................................315
14.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode 317
14.4.3 Clock....................................................................................................................318
14.4.4 SCI Initialization (Asynchronous Mode).............................................................319
14.4.5 Data Transmission (Asynchronous Mode)...........................................................320
14.4.6 Serial Data Reception (Asynchronous Mode)......................................................322
14.5 Multiprocessor Communication Function.........................................................................326
14.5.1 Multiprocessor Serial Data Transmission............................................................328
14.5.2 Multiprocessor Serial Data Reception..................................................................329
14.6 Operation in Clocked Synchronous Mode........................................................................332
14.6.1 Clock....................................................................................................................332
14.6.2 SCI Initialization (Clocked Synchronous Mode).................................................333
14.6.3 Serial Data Transmission (Clocked Synchronous Mode) ....................................334
14.6.4 Serial Data Reception (Clocked Synchronous Mode)..........................................336
14.6.5 Simultaneous Serial Data Transmission and Reception
(Clocked Synchronous Mode) .............................................................................338
14.7 Operation in Smart Card Interface....................................................................................340
14.7.1 Pin Connection Example......................................................................................340
14.7.2 Data Format (Except for Block Transfer Mode)..................................................341
14.7.3 Block Transfer Mode...........................................................................................342
14.7.4 Receive Data Sampling Timing and Reception Margin
in Smart Card Interface Mode..............................................................................343
14.7.5 Initialization.........................................................................................................344
14.7.6 Data Transmission (Except for Block Transfer Mode)........................................344
14.7.7 Serial Data Reception (Except for Block Transfer Mode)...................................348
14.7.8 Clock Output Control...........................................................................................349
14.8 Interrupt Sources...............................................................................................................351
14.8.1 Interrupts in Normal Serial Communication Interface Mode...............................351
14.8.2 Interrupts in Smart Card Interface Mode .............................................................352
14.9 Usage Notes......................................................................................................................353
14.9.1 Module Stop Mode Setting..................................................................................353
14.9.2 Break Detection and Processing...........................................................................353
14.9.3 Mark State and Break Detection..........................................................................353
14.9.4 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only).....................................................................353
Section 15 Hitachi Controller Area Network (HCAN)..................................... 355
15.1 Features.............................................................................................................................355
15.2 Input/Output Pins..............................................................................................................357
15.3 Register Descriptions........................................................................................................357
15.3.1 Master Control Register (MCR)...........................................................................358
15.3.2 General Status Register (GSR) ............................................................................359
15.3.3 Bit Configuration Register (BCR) .......................................................................361
Rev. 1.0, 09/02, page
xvi
of
xxxvi
15.3.4 Mailbox Configuration Register (MBCR)...........................................................363
15.3.5 Transmit Wait Register (TXPR)..........................................................................364
15.3.6 Transmit Wait Cancel Register (TXCR)..............................................................365
15.3.7 Transmit Acknowledge Register (TXACK) ........................................................366
15.3.8 Abort Acknowledge Register (ABACK).............................................................367
15.3.9 Receive Complete Register (RXPR)....................................................................368
15.3.10 Remote Request Register (RFPR)........................................................................369
15.3.11 Interrupt Register (IRR).......................................................................................370
15.3.12 Mailbox Interrupt Mask Register (MBIMR)........................................................374
15.3.13 Interrupt Mask Register (IMR)............................................................................375
15.3.14 Receive Error Counter (REC)..............................................................................376
15.3.15 Transmit Error Counter (TEC).............................................................................376
15.3.16 Unread Message Status Register (UMSR)...........................................................377
15.3.17 Local Acceptance Filter Masks (LAFML, LAFMH)...........................................378
15.3.18 Message Control (MC0 to MC15).......................................................................380
15.3.19 Message Data (MD0 to MD15) ...........................................................................382
15.3.20 HCAN Monitor Register (HCANMON)..............................................................382
15.4 Operation ..........................................................................................................................384
15.4.1 Hardware and Software Resets............................................................................384
15.4.2 Initialization after Hardware Reset ......................................................................384
15.4.3 Message Transmission.........................................................................................390
15.4.4 Message Reception ..............................................................................................393
15.4.5 HCAN Sleep Mode..............................................................................................396
15.4.6 HCAN Halt Mode................................................................................................399
15.5 Interrupt Sources...............................................................................................................400
15.6 DTC Interface ...................................................................................................................401
15.7 CAN Bus Interface............................................................................................................402
15.8 Usage Notes......................................................................................................................402
15.8.1 Module Stop Mode Setting..................................................................................402
15.8.2 Reset ....................................................................................................................402
15.8.3 HCAN Sleep Mode..............................................................................................403
15.8.4 Interrupts..............................................................................................................403
15.8.5 Error Counters......................................................................................................403
15.8.6 Register Access....................................................................................................403
15.8.7 HCAN Medium-Speed Mode..............................................................................403
15.8.8 Register Hold in Standby Modes.........................................................................403
15.8.9 Use on Bit Manipulation Instructions..................................................................403
15.8.10 HCAN TXCR Operation......................................................................................404
Section 16 Synchronous Serial Communication Unit (SSU)............................405
16.1 Features.............................................................................................................................405
16.2 Input/Output Pins..............................................................................................................407
16.3 Register Descriptions........................................................................................................407
Rev. 1.0, 09/02 page
xvii
of
xxxvi
16.3.1 SS Control Register H (SSCRH)..........................................................................407
16.3.2 SS Control Register L (SSCRL) ..........................................................................409
16.3.3 SS Mode Register (SSMR) ..................................................................................410
16.3.4 SS Enable Register (SSER)..................................................................................411
16.3.5 SS Status Register (SSSR)...................................................................................412
16.3.6 SS Transmit Data Register 0 to 3 (SSTDR0 to SSTDR3) ...................................415
16.3.7 SS Receive Data Register 0 to 3 (SSRDR0 to SSRDR3).....................................415
16.3.8 SS Shift Register (SSTRSR)................................................................................415
16.4 Operation...........................................................................................................................416
16.4.1 Transfer Clock .....................................................................................................416
16.4.2 Relationship of Clock Phase, Polarity, and Data..................................................416
16.4.3 Relationship between Data I/O Pins and the Shift Register.................................416
16.4.4 Data Transmission and Data Reception...............................................................417
16.4.5 SCS Pin Control and Arbitration..........................................................................424
16.5 Interrupt Requests.............................................................................................................425
16.6 Usage Note........................................................................................................................426
16.6.1 Setting of Module Stop Mode..............................................................................426
Section 17 A/D Converter................................................................................. 427
17.1 Features.............................................................................................................................427
17.2 Input/Output Pins..............................................................................................................429
17.3 Register Description..........................................................................................................430
17.3.1 A/D Data Registers A to D (ADDRA to ADDRD)..............................................430
17.3.2 A/D Control/Status Register (ADCSR) ...............................................................431
17.3.3 A/D Control Register (ADCR) ............................................................................433
17.4 Operation...........................................................................................................................434
17.4.1 Single Mode.........................................................................................................434
17.4.2 Scan Mode ...........................................................................................................434
17.4.3 Input Sampling and A/D Conversion Time..........................................................435
17.4.4 External Trigger Input Timing.............................................................................437
17.5 Interrupt Source.................................................................................................................437
17.6 A/D Conversion Accuracy Definitions.............................................................................438
17.7 Usage Notes......................................................................................................................440
17.7.1 Module Stop Mode Setting..................................................................................440
17.7.2 Permissible Signal Source Impedance.................................................................440
17.7.3 Influences on Absolute Accuracy ........................................................................440
17.7.4 Range of Analog Power Supply and Other Pin Settings......................................441
17.7.5 Notes on Board Design........................................................................................441
17.7.6 Notes on Noise Countermeasures ........................................................................441
Section 18 RAM ............................................................................................... 443
Section 19 ROM ............................................................................................... 445
Rev. 1.0, 09/02, page
xviii
of
xxxvi
19.1 Features.............................................................................................................................445
19.2 Mode Transitions..............................................................................................................446
19.3 Block Configuration..........................................................................................................450
19.4 Input/Output Pins..............................................................................................................451
19.5 Register Descriptions........................................................................................................451
19.5.1 Flash Memory Control Register 1 (FLMCR1).....................................................452
19.5.2 Flash Memory Control Register 2 (FLMCR2).....................................................453
19.5.3 Erase Block Register 1 (EBR1) ...........................................................................453
19.5.4 Erase Block Register 2 (EBR2) ...........................................................................454
19.5.5 RAM Emulation Register (RAMER)...................................................................454
19.6 On-Board Programming Modes........................................................................................455
19.6.1 Boot Mode...........................................................................................................456
19.6.2 Programming/Erasing in User Program Mode.....................................................458
19.7 Flash Memory Emulation in RAM ...................................................................................459
19.8 Flash Memory Programming/Erasing...............................................................................461
19.8.1 Program/Program-Verify.....................................................................................461
19.8.2 Erase/Erase-Verify...............................................................................................463
19.8.3 Interrupt Handling when Programming/Erasing Flash Memory..........................463
19.9 Program/Erase Protection .................................................................................................465
19.9.1 Hardware Protection............................................................................................465
19.9.2 Software Protection..............................................................................................465
19.9.3 Error Protection....................................................................................................465
19.10 Programmer Mode............................................................................................................466
19.11 Power-Down States for Flash Memory.............................................................................466
Section 20 Clock Pulse Generator.....................................................................467
20.1 Register Descriptions........................................................................................................468
20.1.1 System Clock Control Register (SCKCR)...........................................................468
20.1.2 Low-Power Control Register (LPWRCR)...........................................................469
20.2 Oscillator...........................................................................................................................470
20.2.1 Connecting a Crystal Resonator...........................................................................470
20.2.2 External Clock Input............................................................................................471
20.3 PLL Circuit.......................................................................................................................473
20.4 Medium-Speed Clock Divider..........................................................................................473
20.5 Bus Master Clock Selection Circuit..................................................................................473
20.6 Usage Notes......................................................................................................................474
20.6.1 Note on Crystal Resonator...................................................................................474
20.6.2 Note on Board Design..........................................................................................474
Section 21 Power-Down Modes........................................................................477
21.1 Register Descriptions........................................................................................................480
21.1.1 Standby Control Register (SBYCR) ....................................................................480
21.1.2 Module Stop Control Registers A to C (MSTPCRA to MSTPCRC)...................482
/