Hitachi H8S/2633 F-ZTAT User manual

H8S/2633 Series

H8S/2633

HD6432633

H8S/2632

HD6432632

H8S/2631

HD6432631

H8S/2633 F-ZTAT™

HD64F2633

Hardware Manual

ADE-602-165A

Rev. 2.0

4/14/00

Hitachi, Ltd.

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s

patent, copyright, trademark, or other intellectual property rights for information contained in

this document. Hitachi bears no responsibility for problems that may arise with third party’s

rights, including intellectual property rights, in connection with use of the information

contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you

have received the latest product standards or specifications before final design, purchase or

use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.

However, contact Hitachi’s sales office before using the product in an application that

demands especially high quality and reliability or where its failure or malfunction may directly

threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear

power, combustion control, transportation, traffic, safety equipment or medical equipment for

life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi

particularly for maximum rating, operating supply voltage range, heat radiation characteristics,

installation conditions and other characteristics. Hitachi bears no responsibility for failure or

damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,

consider normally foreseeable failure rates or failure modes in semiconductor devices and

employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi

product does not cause bodily injury, fire or other consequential damage due to operation of

the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document

without written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi

semiconductor products.

Preface

The H8S/2633 Series is a series of high-performance microcontrollers with a 32-bit H8S/2600

CPU core, and a set of on-chip supporting functions required for system configuration.

The H8S/2600 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit

general registers with a 32-bit internal configuration, and a concise and optimized instruction set.

The CPU can handle a 16 Mbyte linear address space (architecturally 4 Gbytes). Programs based

on the high-level language C can also be run efficiently.

The address space is divided into eight areas. The data bus width and access states can be selected

for each of these areas, and various kinds of memory can be connected fast and easily.

Single-power-supply flash memory (F-ZTAT™*

1

), PROM (ZTAT™*

2

), and mask ROM versions

are available, providing a quick and flexible response to conditions from ramp-up through full-

scale volume production, even for applications with frequently changing specifications.

On-chip supporting functions include a 16-bit timer pulse unit (TPU), programmable pulse

generator (PPG), 8-bit timer, 14-bit PWM timer (PWM), watchdog timer (WDT), serial

communication interface (SCI, IrDA), A/D converter, D/A converter, and I/O ports. It is also

possible to incorporate an on-chip PC bus interface (IIC) as an option.

In addition, DMA controller (DMAC) and data transfer controller (DTC) are provided, enabling

high-speed data transfer without CPU intervention.

Use of the H8S/2633 Series enables easy implementation of compact, high-performance systems

capable of processing large volumes of data.

This manual describes the hardware of the H8S/2633 Series. Refer to the H8S/2600 Series and

H8S/2000 Series Programming Manual for a detailed description of the instruction set.

Note: * F-ZTAT (Flexible-ZTAT) is a trademark of Hitachi, Ltd.

Main Revisions and Additions in this Edition

Page Item

Revisions

(See Manual for Details)

2 1.1 Overview Table 1-1 Overview

Input clock frequency amended

9 1.3.2 Pin Functions in Each Operating Mode Table 1-2 Pin Functions in Each

Operating Mode amended

14 1.3.3 Pin Functions Table 1-3 Pin Functions amended

38 2.6.1 Overview Table 2-1 Instruction Classification

Notes on TAS Instruction added

39 2.6.2 Instructions and Addressing Modes Table 2-2 Combinations of

Instructions and Addressing Modes

Notes on TAS Instruction added

43, 47 2.6.3 Table of Instructions Classified by Function Table 2-3 Instructions classified by

Function

Notes on TAS Instruction added

66 2.10 Usage Note Added

68 3.2.1 Mode Control Register (MDCR) Bit 7 description amended

75 3.4 Pin Functions in Each Operating Mode Table 3-3 Pin Functions in Each

Mode amended

76 to 78 3.5 Address Map in Each Operating Mode Figure 3-1 Memory Map in Each

Operating Mode in the H8S/2633

Note 2 added

Figure 3-2 Memory Map in Each

Operating Mode in the H8S/2632

Note 2 added

Figure 3-3 Memory Map in Each

Operating Mode in the H8S/2631

Note 2 added, amended

84, 85 4.2.3 Reset Sequence Figure 4-2 Reset Sequence

(Modes 4 and 5) amended

Figure 4-3 Reset Sequence

(Modes 6 and 7) added

87 4.4 Interrupts Figure 4-4 Interrupt Sources and

Number of Interrupts amended

Page Item

Revisions

(See Manual for Details)

101 5.3.3 Interrupt Exception Handling Vector Table Table 5-4 Interrupt Sources, Vector

Addresses, and Interrupt Priorities

8-bit timer channel names amended

109 5.4.2 Interrupt Control Mode 0 Figure 5-5 Flowchart of Procedure

Up to Interrupt Acceptance in

Interrupt Control Mode 0 amended

189 7.6.1 DDS=1 Figure 7-30 DACK Output Timing

when DDS=1 (Example Showing

DRAM Access)

Note added

190 7.6.2 DDS=0 Figure 7-31 DACK Output Timing

when DDS=0 (Example Showing

DRAM Access)

Note added

202 7.10.4 Transition Timing Figure 7-39 Bus-Released State

Transition Timing amended

209, 210 8.1.3 Overview of Functions Table 8-1 Overview of DMAC

Functions

SCI transfer source names

amended

290, 291 8.7 Usage Notes DMAC Register Access during

Operation added

Figure 8-40 and figure 8-41 added

296 9.1.2 Block Diagram Figure 9-1 Block Diagram of DTC

amended

310, 311 9.3.3 DTC Vector Table Table 9-4 Interrupt Sources, DTC

Vector Addresses, and

Corresponding DTCEs

8-bit timer channel names amended

327 10.1 Overview Capacitance load value amended

328 to

331

Table 10-1 Port Functions

amended

350 to

352

10.3.3 Pin Functions Table 10-5 Port 3 Pin Functions

amended

363 10.7.1 Overview Figure 10-6 Port A Pin Functions

amended

369 10.8.1 Overview Figure 10-9 Port B Pin Functions

amended

Page Item

Revisions

(See Manual for Details)

396 10.12.3 Pin Functions Table 10-21 Port F Pin Functions

PF3 description amended

522 13.1.2 Block Diagram Figure 13-1 Block Diagram of 8-Bit

Timer amended

523 13.1.3 Pin Configuration Table 13-1 Pin Configuration

amended

563 15.1 Overview Amended

566 15.1.4 Register Configuration Table 15-2 WDT Registers

amended

570, 571 15.2.2 Timer Control/Status Register (TCSR) Bits 2 to 0 (overflow period)

amended

573 15.2.4 Pin Function Control Register (PFCR) Amended

587, 588 16.1.4 Register Configuration Table 16-2 SCI Registers

Note 3 amended

597 16.2.6 Serial Control Register (SCR) Description of bits 1 and 0 amended

646 16.3.5 IrDA Operation Figure 16-22 IrDA Transmit and

Receive Operations amended

653 to

658

16.5 Usage Notes Operation in Case of Mode

Transition added

Switching from SCK Pin Function to

Port Pin Function added

18.1.1 Features Formatless description deleted

692, 693 18.1.2 Block Diagram Description amended

Figure 18-1 Block Diagram of I

2

C

Bus Interface

Dedicated formatless clock deleted

694 18.1.3 Input/Output Pins Table 18-1 I

2

C Bus Interface Pins

SYNCI pin deleted

699, 700 18.2.2 Slave Address Register (SAR) Bit 0 description amended

701 18.2.3 Second Slave Address Register (SARX) Bit 0 description amended

703 18.2.4 I

2

C Bus Mode Register (ICMR) Description of bits 5 to 3

ø = 25 MHz added to transfer rates

705, 708,

709

18.2.5 I

2

C Bus Control Register (ICCR) Bit 7 description added

Bit 1 description amended

Page Item

Revisions

(See Manual for Details)

717 18.2.8 DDC Switch Register (DDCSWR) Description of bits 7 to 4 amended

Bits 3 to 0 amended and Note 2

added

Description of CLR3-0 added

719 18.3.1 I

2

C Bus Data Format Description amended

Figure 18-3 I

2

C Bus Data Formats

(I

2

C Bus Formats)

Formatless description deleted

720 to

722

18.3.2 Master Transmit Operation Description amended

722 to

724

18.3.3 Master Receive Operation Description amended

Figure 18-8 Example of Master

Receive Mode Operation Timing

(MLS = WAIT = ACKB = 0)

amended

731, 732 18.3.9 Sample Flowcharts Figure 18-14 Flowchart for Master

Transmit Mode (Example) amended

Figure 18-15 Flowchart for Master

Receive Mode (Example) amended

734 to

736

18.3.10 Initialization of Internal State Added

736, 737,

739, 740

18.4 Usage Notes Table 18-6 I

2

C Bus Timing (SCL

and SDA Output) amended

Table 18-7 Permissible SCL Rise

Time (t

Sr

) Values ø = 25 MHz added

to time indication

Table 18-8 I

2

C Bus Timing (with

Maximum Influence of t

Sr

/t

Sf

)

amended

740 to

743

Note on ICDR Read at End of

Master Reception added

Notes on Start Condition Issuance

for Retransmission added

Notes on I

2

C Bus Interface Stop

Condition Instruction Issuance

added

745 19.1.1 Features Conversion time amended

753 19.2.3 A/D Control Register (ADCR) Bit 3 and 2 (conversion time)

amended

Page Item

Revisions

(See Manual for Details)

760 19.4.3 Input Sampling and A/D Conversion Time Conversion time amended

761 Table 19-4 A/D Conversion Time

(Single Mode) amended

766 19.6 Usage Notes Permissible Signal Source

Impedance amended

771 20.1.4 Register Configuration Table 20-2 D/A Converter

Registers amended

778 21.2.1 System Control Register (SYSCR) Description of bit 0

Note added

779 21.4 Usage Notes Reserved Areas amended

781 22.1 Features Programming/Erasing amended

792, 793 22.5.2 Flash Memory Control Register 2

(FLMCR2)

Amended

797, 798 22.5.7 Serial Control Register X (SCRX) Amended

801 22.6.1 Boot Mode Automatic SCI Bit Rate Adjustment

Bit rate amended

803, 804 22.6.2 User Program Mode Description amended

805 to

812

22.7 Programming/Erasing Flash Memory Completely revised

821 22.11.1 Socket Adapter Pin Correspondence

Diagram

Figure 22-17 Socket Adapter Pin

Correspondence Diagram amended

822 22.11.2 Programmer Mode Operation Table 22-11 Settings for Various

Operating Modes In Programmer

Mode amended

834 to

838

22.13 Flash Memory Programming and Erasing

Precautions

Added

839 22.14 Note on Switching from F-ZTAT Version to

Mask ROM Version

Added

842 23.2.1 System Clock Control Register (SCKCR) Description amended

843, 844 23.2.2 Low-Power Control Register (LPWRCR) Amended

844 23.3 Oscillator Amended

Page Item

Revisions

(See Manual for Details)

844, 845 23.3.1 Connecting a Crystal Resonator Table 23-2 Damping Resistance

Value

25 MHz added

Crystal Resonator amended

845, 846 Table 23-3 Crystal Resonator

Parameters

25 MHz added

Figure 23-5 Points for Attention

when Using PLL Oscillation Circuit

amended

848 23.3.2 External Clock Input External Clock

Description amended

Table 23-4 External Clock Input

Conditions amended

849 23.4 PLL Circuit Amended

854 24.1 Overview Table 24-1 LSI Internal States in

Each Mode

WDT module stop mode description

amended

860, 861 24.2.2 System Clock Control Register (SCKCR) Description amended

871 24.6.3 Setting Oscillation Stabilization Time after

Clearing Software Standby Mode

Table 24-5 Oscillation Stabilization

Time Settings

25 MHz added

25.2 Power supply voltage and operating

frequency range

Deleted

Following item numbers amended

880 to

887

25.2 DC Characteristics Amended

888 25.3 AC Characteristics Figure 25-1 Output Load Circuit

amended

889 25.3.1 Clock Timing Table 25-5 Clock Timing amended

893, 894,

901

25.3.3 Bus Timing Table 25-7 Bus Timing amended

Figure 25-15 External Bus Request

Output Timing added

902 25.3.4 DMAC Timing Table 25-8 DMAC Timing amended

Page Item

Revisions

(See Manual for Details)

906 to

908

25.3.5 Timing of On-Chip Supporting Modules Table 25-9 Timing of On-Chip

Supporting Modules

Note added

Figure 25-21 PPG Output Timing

amended

914 25.4 A/D Conversion Characteristics Table 25-11 A/D Conversion

Characteristics

Conditions amended

915 25.5 D/A Conversion Characteristics Table 25-12 D/A Conversion

Characteristics

Conditions amended

916 25.6 Flash Memory Characteristics Added

925, 927,

942

A.1 Instruction List Table A-1 Instruction Set

Notes on TAS Instruction added

MULXU and MULXS instruction

execution states amended

956, 957 A.2 Instruction Codes Table A-2 Instruction Codes

Notes on TAS Instruction added

974, 975 A.4 Number of States Required for Instruction

Execution

Table A-5 Number of Cycles in

Instruction Execution

Notes on TAS Instruction added

988, 989 A.5 Bus States During Instruction Execution Table A-6 Instruction Execution

Cycles

Notes on TAS Instruction added

996 to

1005

B.1 Addresses Completely revised

1006 to

1103

B.2 Functions Completely revised

i

Contents

Section 1 Overview............................................................................................................ 1

1.1 Overview............................................................................................................................ 1

1.2 Internal Block Diagram...................................................................................................... 6

1.3 Pin Description................................................................................................................... 7

1.3.1 Pin Arrangement................................................................................................... 7

1.3.2 Pin Functions in Each Operating Mode................................................................ 9

1.3.3 Pin Functions........................................................................................................ 14

Section 2 CPU..................................................................................................................... 21

2.1 Overview............................................................................................................................ 21

2.1.1 Features................................................................................................................. 21

2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU................................... 22

2.1.3 Differences from H8/300 CPU ............................................................................. 23

2.1.4 Differences from H8/300H CPU.......................................................................... 23

2.2 CPU Operating Modes....................................................................................................... 24

2.3 Address Space.................................................................................................................... 29

2.4 Register Configuration.......................................................................................................30

2.4.1 Overview............................................................................................................... 30

2.4.2 General Registers.................................................................................................. 31

2.4.3 Control Registers.................................................................................................. 32

2.4.4 Initial Register Values .......................................................................................... 34

2.5 Data Formats...................................................................................................................... 35

2.5.1 General Register Data Formats............................................................................. 35

2.5.2 Memory Data Formats.......................................................................................... 37

2.6 Instruction Set.................................................................................................................... 38

2.6.1 Overview............................................................................................................... 38

2.6.2 Instructions and Addressing Modes...................................................................... 39

2.6.3 Table of Instructions Classified by Function....................................................... 41

2.6.4 Basic Instruction Formats..................................................................................... 48

2.7 Addressing Modes and Effective Address Calculation...................................................... 50

2.7.1 Addressing Mode.................................................................................................. 50

2.7.2 Effective Address Calculation.............................................................................. 53

2.8 Processing States................................................................................................................ 57

2.8.1 Overview............................................................................................................... 57

2.8.2 Reset State ............................................................................................................ 58

2.8.3 Exception-Handling State..................................................................................... 59

2.8.4 Program Execution State ...................................................................................... 62

2.8.5 Bus-Released State................................................................................................ 62

2.8.6 Power-Down State................................................................................................ 62

2.9 Basic Timing...................................................................................................................... 63

ii

2.9.1 Overview............................................................................................................... 63

2.9.2 On-Chip Memory (ROM, RAM).......................................................................... 63

2.9.3 On-Chip Supporting Module Access Timing....................................................... 65

2.9.4 External Address Space Access Timing............................................................... 66

2.10 Usage Note......................................................................................................................... 66

2.10.1 TAS Instruction .................................................................................................... 66

Section 3 MCU Operating Modes................................................................................. 67

3.1 Overview............................................................................................................................ 67

3.1.1 Operating Mode Selection.................................................................................... 67

3.1.2 Register Configuration.......................................................................................... 68

3.2 Register Descriptions......................................................................................................... 68

3.2.1 Mode Control Register (MDCR).......................................................................... 68

3.2.2 System Control Register (SYSCR)....................................................................... 69

3.2.3 Pin Function Control Register (PFCR)................................................................. 71

3.3 Operating Mode Descriptions............................................................................................ 74

3.3.1 Mode 4.................................................................................................................. 74

3.3.2 Mode 5 ................................................................................................................. 74

3.3.3 Mode 6.................................................................................................................. 74

3.3.4 Mode 7.................................................................................................................. 74

3.4 Pin Functions in Each Operating Mode............................................................................. 75

3.5 Address Map in Each Operating Mode.............................................................................. 75

Section 4 Exception Handling........................................................................................ 79

4.1 Overview............................................................................................................................ 79

4.1.1 Exception Handling Types and Priority................................................................ 79

4.1.2 Exception Handling Operation ............................................................................. 80

4.1.3 Exception Vector Table........................................................................................ 80

4.2 Reset................................................................................................................................... 82

4.2.1 Overview............................................................................................................... 82

4.2.2 Types of Reset ...................................................................................................... 82

4.2.3 Reset Sequence ..................................................................................................... 83

4.2.4 Interrupts after Reset............................................................................................. 85

4.2.5 State of On-Chip Supporting Modules after Reset Release.................................. 85

4.3 Traces................................................................................................................................. 86

4.4 Interrupts............................................................................................................................ 87

4.5 Trap Instruction.................................................................................................................. 88

4.6 Stack Status after Exception Handling .............................................................................. 89

4.7 Notes on Use of the Stack.................................................................................................. 90

Section 5 Interrupt Controller......................................................................................... 91

5.1 Overview............................................................................................................................ 91

5.1.1 Features................................................................................................................. 91

5.1.2 Block Diagram...................................................................................................... 92

iii

5.1.3 Pin Configuration.................................................................................................. 93

5.1.4 Register Configuration.......................................................................................... 93

5.2 Register Descriptions......................................................................................................... 94

5.2.1 System Control Register (SYSCR)....................................................................... 94

5.2.2 Interrupt Priority Registers A to L, O (IPRA to IPRL, IPRO) ............................. 95

5.2.3 IRQ Enable Register (IER)................................................................................... 96

5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ..................................... 97

5.2.5 IRQ Status Register (ISR) .................................................................................... 98

5.3 Interrupt Sources................................................................................................................ 99

5.3.1 External Interrupts................................................................................................ 99

5.3.2 Internal Interrupts.................................................................................................. 100

5.3.3 Interrupt Exception Handling Vector Table ......................................................... 100

5.4 Interrupt Operation............................................................................................................. 105

5.4.1 Interrupt Control Modes and Interrupt Operation ................................................ 105

5.4.2 Interrupt Control Mode 0...................................................................................... 108

5.4.3 Interrupt Control Mode 2...................................................................................... 110

5.4.4 Interrupt Exception Handling Sequence............................................................... 112

5.4.5 Interrupt Response Times..................................................................................... 113

5.5 Usage Notes ....................................................................................................................... 114

5.5.1 Contention between Interrupt Generation and Disabling ..................................... 114

5.5.2 Instructions that Disable Interrupts....................................................................... 115

5.5.3 Times when Interrupts are Disabled .................................................................... 115

5.5.4 Interrupts during Execution of EEPMOV Instruction.......................................... 116

5.6 DTC and DMAC Activation by Interrupt.......................................................................... 116

5.6.1 Overview............................................................................................................... 116

5.6.2 Block Diagram...................................................................................................... 116

5.6.3 Operation .............................................................................................................. 117

Section 6 PC Break Controller (PBC).......................................................................... 119

6.1 Overview............................................................................................................................ 119

6.1.1 Features................................................................................................................. 119

6.1.2 Block Diagram...................................................................................................... 120

6.1.3 Register Configuration.......................................................................................... 121

6.2 Register Descriptions......................................................................................................... 121

6.2.1 Break Address Register A (BARA)...................................................................... 121

6.2.2 Break Address Register B (BARB)...................................................................... 122

6.2.3 Break Control Register A (BCRA)....................................................................... 122

6.2.4 Break Control Register B (BCRB) ....................................................................... 124

6.2.5 Module Stop Control Register C (MSTPCRC).................................................... 124

6.3 Operation............................................................................................................................ 125

6.3.1 PC Break Interrupt Due to Instruction Fetch........................................................ 125

6.3.2 PC Break Interrupt Due to Data Access ............................................................... 125

6.3.3 Notes on PC Break Interrupt Handling................................................................. 126

iv

6.3.4 Operation in Transitions to Power-Down Modes................................................. 126

6.3.5 PC Break Operation in Continuous Data Transfer ............................................... 127

6.3.6 When Instruction Execution is Delayed by One State.......................................... 128

6.3.7 Additional Notes................................................................................................... 129

Section 7 Bus Controller.................................................................................................. 131

7.1 Overview............................................................................................................................ 131

7.1.1 Features................................................................................................................. 131

7.1.2 Block Diagram...................................................................................................... 133

7.1.3 Pin Configuration.................................................................................................. 134

7.1.4 Register Configuration.......................................................................................... 135

7.2 Register Descriptions......................................................................................................... 136

7.2.1 Bus Width Control Register (ABWCR) ............................................................... 136

7.2.2 Access State Control Register (ASTCR).............................................................. 137

7.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 138

7.2.4 Bus Control Register H (BCRH).......................................................................... 142

7.2.5 Bus Control Register L (BCRL)........................................................................... 144

7.2.6 Pin Function Control Register (PFCR)................................................................. 146

7.2.7 Memory Control Register (MCR) ........................................................................ 149

7.2.8 DRAM Control Register (DRAMCR).................................................................. 151

7.2.9 Refresh Timer Counter (RTCNT) ........................................................................ 153

7.2.10 Refresh Time Constant Register (RTCOR).......................................................... 153

7.3 Overview of Bus Control................................................................................................... 154

7.3.1 Area Partitioning................................................................................................... 154

7.3.2 Bus Specifications ................................................................................................ 155

7.3.3 Memory Interfaces................................................................................................ 156

7.3.4 Interface Specifications for Each Area................................................................. 157

7.3.5 Chip Select Signals............................................................................................... 158

7.4 Basic Bus Interface............................................................................................................ 159

7.4.1 Overview............................................................................................................... 159

7.4.2 Data Size and Data Alignment.............................................................................. 159

7.4.3 Valid Strobes ........................................................................................................ 161

7.4.4 Basic Timing......................................................................................................... 162

7.4.5 Wait Control.......................................................................................................... 170

7.5 DRAM Interface ................................................................................................................ 172

7.5.1 Overview............................................................................................................... 172

7.5.2 Setting up DRAM Space ...................................................................................... 172

7.5.3 Address Multiplexing............................................................................................ 173

7.5.4 Data Bus................................................................................................................ 173

7.5.5 DRAM Interface Pins ........................................................................................... 174

7.5.6 Basic Timing......................................................................................................... 174

7.5.7 Precharge State Control........................................................................................ 176

7.5.8 Wait Control.......................................................................................................... 177

v

7.5.9 Byte Access Control ............................................................................................. 179

7.5.10 Burst Operation..................................................................................................... 181

7.5.11 Refresh Control..................................................................................................... 185

7.6 DMAC Single Address Mode and DRAM Interface......................................................... 189

7.6.1 DDS=1.................................................................................................................. 189

7.6.2 DDS=0.................................................................................................................. 190

7.7 Burst ROM Interface.......................................................................................................... 191

7.7.1 Overview............................................................................................................... 191

7.7.2 Basic Timing......................................................................................................... 191

7.7.3 Wait Control.......................................................................................................... 193

7.8 Idle Cycle........................................................................................................................... 194

7.8.1 Operation .............................................................................................................. 194

7.8.2 Pin States in Idle Cycle......................................................................................... 198

7.9 Write Data Buffer Function ............................................................................................... 199

7.10 Bus Release........................................................................................................................ 200

7.10.1 Overview............................................................................................................... 200

7.10.2 Operation .............................................................................................................. 200

7.10.3 Pin States in External Bus Released State............................................................ 201

7.10.4 Transition Timing ................................................................................................. 202

7.10.5 Notes..................................................................................................................... 203

7.11 Bus Arbitration................................................................................................................... 204

7.11.1 Overview............................................................................................................... 204

7.11.2 Operation .............................................................................................................. 204

7.11.3 Bus Transfer Timing............................................................................................. 205

7.12 Resets and the Bus Controller............................................................................................ 205

Section 8 DMA Controller.............................................................................................. 207

8.1 Overview............................................................................................................................ 207

8.1.1 Features................................................................................................................. 207

8.1.2 Block Diagram...................................................................................................... 208

8.1.3 Overview of Functions.......................................................................................... 209

8.1.4 Pin Configuration.................................................................................................. 211

8.1.5 Register Configuration.......................................................................................... 212

8.2 Register Descriptions (1) (Short Address Mode)............................................................... 213

8.2.1 Memory Address Registers (MAR)...................................................................... 214

8.2.2 I/O Address Register (IOAR) ............................................................................... 215

8.2.3 Execute Transfer Count Register (ETCR)............................................................ 215

8.2.4 DMA Control Register (DMACR) ....................................................................... 216

8.2.5 DMA Band Control Register (DMABCR)........................................................... 220

8.3 Register Descriptions (2) (Full Address Mode)................................................................. 225

8.3.1 Memory Address Register (MAR)........................................................................ 225

8.3.2 I/O Address Register (IOAR) ............................................................................... 225

8.3.3 Execute Transfer Count Register (ETCR)............................................................ 226

vi

8.3.4 DMA Control Register (DMACR) ....................................................................... 227

8.3.5 DMA Band Control Register (DMABCR)........................................................... 231

8.4 Register Descriptions (3) ................................................................................................... 236

8.4.1 DMA Write Enable Register (DMAWER)........................................................... 236

8.4.2 DMA Terminal Control Register (DMATCR)..................................................... 238

8.4.3 Module Stop Control Register (MSTPCR)........................................................... 239

8.5 Operation............................................................................................................................ 240

8.5.1 Transfer Modes..................................................................................................... 240

8.5.2 Sequential Mode ................................................................................................... 242

8.5.3 Idle Mode.............................................................................................................. 245

8.5.4 Repeat Mode......................................................................................................... 248

8.5.5 Single Address Mode............................................................................................ 252

8.5.6 Normal Mode........................................................................................................ 255

8.5.7 Block Transfer Mode............................................................................................ 258

8.5.8 DMAC Activation Sources................................................................................... 264

8.5.9 Basic DMAC Bus Cycles...................................................................................... 267

8.5.10 DMAC Bus Cycles (Dual Address Mode)............................................................ 268

8.5.11 DMAC Bus Cycles (Single Address Mode)......................................................... 276

8.5.12 Write Data Buffer Function.................................................................................. 282

8.5.13 DMAC Multi-Channel Operation......................................................................... 283

8.5.14 Relation Between External Bus Requests, Refresh Cycles, the DTC,

and the DMAC...................................................................................................... 285

8.5.15 NMI Interrupts and DMAC.................................................................................. 286

8.5.16 Forced Termination of DMAC Operation............................................................ 287

8.5.17 Clearing Full Address Mode................................................................................. 288

8.6 Interrupts............................................................................................................................ 289

8.7 Usage Notes....................................................................................................................... 290

Section 9 Data Transfer Controller (DTC)................................................................. 295

9.1 Overview............................................................................................................................ 295

9.1.1 Features................................................................................................................. 295

9.1.2 Block Diagram...................................................................................................... 296

9.1.3 Register Configuration.......................................................................................... 297

9.2 Register Descriptions......................................................................................................... 298

9.2.1 DTC Mode Register A (MRA)............................................................................. 298

9.2.2 DTC Mode Register B (MRB).............................................................................. 300

9.2.3 DTC Source Address Register (SAR) .................................................................. 301

9.2.4 DTC Destination Address Register (DAR) .......................................................... 301

9.2.5 DTC Transfer Count Register A (CRA)............................................................... 301

9.2.6 DTC Transfer Count Register B (CRB)................................................................ 302

9.2.7 DTC Enable Registers (DTCER).......................................................................... 302

9.2.8 DTC Vector Register (DTVECR) ........................................................................ 303

9.2.9 Module Stop Control Register A (MSTPCRA).................................................... 304

vii

9.3 Operation............................................................................................................................ 305

9.3.1 Overview............................................................................................................... 305

9.3.2 Activation Sources................................................................................................ 307

9.3.3 DTC Vector Table ................................................................................................ 308

9.3.4 Location of Register Information in Address Space............................................. 312

9.3.5 Normal Mode........................................................................................................ 313

9.3.6 Repeat Mode......................................................................................................... 314

9.3.7 Block Transfer Mode............................................................................................ 315

9.3.8 Chain Transfer...................................................................................................... 317

9.3.9 Operation Timing.................................................................................................. 318

9.3.10 Number of DTC Execution States........................................................................ 319

9.3.11 Procedures for Using DTC.................................................................................... 321

9.3.12 Examples of Use of the DTC................................................................................ 322

9.4 Interrupts............................................................................................................................ 325

9.5 Usage Notes........................................................................................................................ 325

Section 10 I/O Ports............................................................................................................. 327

10.1 Overview............................................................................................................................ 327

10.2 Port 1.................................................................................................................................. 332

10.2.1 Overview............................................................................................................... 332

10.2.2 Register Configuration.......................................................................................... 333

10.2.3 Pin Functions........................................................................................................ 335

10.3 Port 3.................................................................................................................................. 347

10.3.1 Overview............................................................................................................... 347

10.3.2 Register Configuration.......................................................................................... 347

10.3.3 Pin Functions........................................................................................................ 350

10.4 Port 4.................................................................................................................................. 353

10.4.1 Overview............................................................................................................... 353

10.4.2 Register Configuration.......................................................................................... 354

10.4.3 Pin Functions........................................................................................................ 354

10.5 Port 7.................................................................................................................................. 355

10.5.1 Overview............................................................................................................... 355

10.5.2 Register Configuration.......................................................................................... 356

10.5.3 Pin Functions........................................................................................................ 358

10.6 Port 9.................................................................................................................................. 361

10.6.1 Overview............................................................................................................... 361

10.6.2 Register Configuration.......................................................................................... 362

10.6.3 Pin Functions........................................................................................................ 362

10.7 Port A................................................................................................................................. 363

10.7.1 Overview............................................................................................................... 363

10.7.2 Register Configuration.......................................................................................... 364

10.7.3 Pin Functions........................................................................................................ 367

10.7.4 MOS Input Pull-Up Function................................................................................ 367

viii

10.8 Port B ................................................................................................................................. 369

10.8.1 Overview............................................................................................................... 369

10.8.2 Register Configuration.......................................................................................... 370

10.8.3 Pin Functions........................................................................................................ 373

10.8.4 MOS Input Pull-Up Function................................................................................ 374

10.9 Port C ................................................................................................................................. 375

10.9.1 Overview............................................................................................................... 375

10.9.2 Register Configuration.......................................................................................... 376

10.9.3 Pin Functions for Each Mode ............................................................................... 379

10.9.4 MOS Input Pull-Up Function................................................................................ 381

10.10 Port D................................................................................................................................. 382

10.10.1 Overview............................................................................................................... 382

10.10.2 Register Configuration.......................................................................................... 383

10.10.3 Pin Functions........................................................................................................ 385

10.10.4 MOS Input Pull-Up Function................................................................................ 386

10.11 Port E.................................................................................................................................. 387

10.11.1 Overview............................................................................................................... 387

10.11.2 Register Configuration.......................................................................................... 388

10.11.3 Pin Functions........................................................................................................ 390

10.11.4 MOS Input Pull-Up Function................................................................................ 391

10.12 Port F.................................................................................................................................. 392

10.12.1 Overview............................................................................................................... 392

10.12.2 Register Configuration.......................................................................................... 393

10.12.3 Pin Functions........................................................................................................ 395

10.13 Port G................................................................................................................................. 397

10.13.1 Overview............................................................................................................... 397

10.13.2 Register Configuration.......................................................................................... 398

10.13.3 Pin Functions........................................................................................................ 400

Section 11 16-Bit Timer Pulse Unit (TPU).................................................................. 403

11.1 Overview............................................................................................................................ 403

11.1.1 Features................................................................................................................. 403

11.1.2 Block Diagram...................................................................................................... 407

11.1.3 Pin Configuration.................................................................................................. 408

11.1.4 Register Configuration.......................................................................................... 410

11.2 Register Descriptions......................................................................................................... 412

11.2.1 Timer Control Register (TCR).............................................................................. 412

11.2.2 Timer Mode Register (TMDR)............................................................................. 417

11.2.3 Timer I/O Control Register (TIOR)...................................................................... 419

11.2.4 Timer Interrupt Enable Register (TIER)............................................................... 432

11.2.5 Timer Status Register (TSR) ................................................................................ 435

11.2.6 Timer Counter (TCNT)......................................................................................... 439

11.2.7 Timer General Register (TGR)............................................................................. 440

ix

11.2.8 Timer Start Register (TSTR)................................................................................ 441

11.2.9 Timer Synchro Register (TSYR).......................................................................... 442

11.2.10 Module Stop Control Register A (MSTPCRA).................................................... 443

11.3 Interface to Bus Master...................................................................................................... 444

11.3.1 16-Bit Registers.................................................................................................... 444

11.3.2 8-Bit Registers...................................................................................................... 444

11.4 Operation............................................................................................................................ 446

11.4.1 Overview............................................................................................................... 446

11.4.2 Basic Functions..................................................................................................... 447

11.4.3 Synchronous Operation ........................................................................................ 453

11.4.4 Buffer Operation................................................................................................... 455

11.4.5 Cascaded Operation.............................................................................................. 459

11.4.6 PWM Modes......................................................................................................... 461

11.4.7 Phase Counting Mode........................................................................................... 466

11.5 Interrupts............................................................................................................................ 473

11.5.1 Interrupt Sources and Priorities............................................................................ 473

11.5.2 DTC/DMAC Activation........................................................................................ 475

11.5.3 A/D Converter Activation..................................................................................... 475

11.6 Operation Timing............................................................................................................... 476

11.6.1 Input/Output Timing............................................................................................. 476

11.6.2 Interrupt Signal Timing ........................................................................................ 480

11.7 Usage Notes ....................................................................................................................... 484

Section 12 Programmable Pulse Generator (PPG)..................................................... 495

12.1 Overview............................................................................................................................ 495

12.1.1 Features................................................................................................................. 495

12.1.2 Block Diagram...................................................................................................... 496

12.1.3 Pin Configuration.................................................................................................. 497

12.1.4 Registers................................................................................................................ 498

12.2 Register Descriptions......................................................................................................... 499

12.2.1 Next Data Enable Registers H and L (NDERH, NDERL) ................................... 499

12.2.2 Output Data Registers H and L (PODRH, PODRL) ............................................ 500

12.2.3 Next Data Registers H and L (NDRH, NDRL).................................................... 501

12.2.4 Notes on NDR Access.......................................................................................... 501

12.2.5 PPG Output Control Register (PCR).................................................................... 503

12.2.6 PPG Output Mode Register (PMR)...................................................................... 505

12.2.7 Port 1 Data Direction Register (P1DDR).............................................................. 508

12.2.8 Module Stop Control Register A (MSTPCRA).................................................... 508

12.3 Operation............................................................................................................................ 509

12.3.1 Overview............................................................................................................... 509

12.3.2 Output Timing ...................................................................................................... 510

12.3.3 Normal Pulse Output ............................................................................................ 511

12.3.4 Non-Overlapping Pulse Output ............................................................................ 513

x

12.3.5 Inverted Pulse Output ........................................................................................... 516

12.3.6 Pulse Output Triggered by Input Capture............................................................. 517

12.4 Usage Notes ...................................................................................................................... 518

Section 13 8-Bit Timers (TMR)....................................................................................... 521

13.1 Overview............................................................................................................................ 521

13.1.1 Features................................................................................................................. 521

13.1.2 Block Diagram...................................................................................................... 522

13.1.3 Pin Configuration.................................................................................................. 523

13.1.4 Register Configuration.......................................................................................... 524

13.2 Register Descriptions......................................................................................................... 525

13.2.1 Timer Counters 0 to 3 (TCNT0 to TCNT3).......................................................... 525

13.2.2 Time Constant Registers A0 to A3 (TCORA0 to TCORA3)............................... 525

13.2.3 Time Constant Registers B0 to B3 (TCORB0 to TCORB3)................................ 526

13.2.4 Timer Control Registers 0 to 3 (TCR0 to TCR3)................................................. 526

13.2.5 Timer Control/Status Registers 0 to 3 (TCSR0 to TCSR3).................................. 529

13.2.6 Module Stop Control Register A (MSTPCRA).................................................... 532

13.3 Operation............................................................................................................................ 533

13.3.1 TCNT Incrementation Timing.............................................................................. 533

13.3.2 Compare Match Timing........................................................................................ 534

13.3.3 Timing of External RESET on TCNT.................................................................. 536

13.3.4 Timing of Overflow Flag (OVF) Setting.............................................................. 536

13.3.5 Operation with Cascaded Connection .................................................................. 537

13.4 Interrupts............................................................................................................................ 538

13.4.1 Interrupt Sources and DTC Activation................................................................. 538

13.4.2 A/D Converter Activation..................................................................................... 538

13.5 Sample Application............................................................................................................ 539

13.6 Usage Notes ....................................................................................................................... 540

13.6.1 Contention between TCNT Write and Clear........................................................ 540

13.6.2 Contention between TCNT Write and Increment................................................. 541

13.6.3 Contention between TCOR Write and Compare Match....................................... 542

13.6.4 Contention between Compare Matches A and B.................................................. 543

13.6.5 Switching of Internal Clocks and TCNT Operation............................................ 543

13.6.6 Interrupts and Module Stop Mode........................................................................ 545

Section 14 14-Bit PWM D/A............................................................................................ 547

14.1 Overview............................................................................................................................ 547

14.1.1 Features................................................................................................................. 547

14.1.2 Block Diagram...................................................................................................... 548

14.1.3 Pin Configuration.................................................................................................. 549

14.1.4 Register Configuration.......................................................................................... 549

14.2 Register Descriptions......................................................................................................... 550

14.2.1 PWM D/A Counter (DACNT).............................................................................. 550

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Hitachi H8S/2633 F-ZTAT User manual

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