NXP LPC550x/S0x User guide

UM11424

LPC55S0x/LPC550x User manual

Rev. 1.0 — 20 October 2020 User manual

Document information

Info Content

Keywords LPC55S06JBD64, LPC55S06JHI48, LPC55S04JBD64, LPC55S04JHI48,

LPC5506JBD64, LPC5506JHI48, LPC5504JBD64, LPC5504JHI48,

LPC5502JBD64, LPC5502JHI48, ARM Cortex-M33 core, 32-bit

microcontroller, SCTimer/PWM, PLU, TrustZone, CASPER, I2C, AES,

PUF, SHA, CRC, RNG, 16-bit ADC, CAN-FD

Abstract LPC55S0x/LPC550x

User Manual

User manual Rev. 1.0 — 20 October 2020 2 of 1015

Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

NXP Semiconductors

UM11424

LPC55S0x/LPC550x User manual

Revision history

Rev Date Description

1.0 20201020 Initial version.

User manual Rev. 1.0 — 20 October 2020 3 of 1015

1.1 Introduction

The LPC55S0x/LPC550x is an Arm Cortex®-M33 based micro-controller for embedded

applications and includes the following features:

• Up to 96 kB of on-chip SRAM.

• Up to 256 kB on-chip flash.

• CAN-FD.

• Five general-purpose timers.

• SCTimer/PWM.

• RTC/alarm timer.

• 24-bit Multi-Rate Timer (MRT).

• Windowed Watchdog Timer (WWDT).

• Code Watchdog

• High speed SPI (50MHz).

• Eight flexible serial communication peripherals (each of which can be a USART, SPI,

I2C, or I2s interface).

• 16-bit 2.0 Msamples/sec ADC capable of simultaneous conversions.

• Temperature sensor.

The Arm Cortex M33 provides a security foundation, offering isolation to protect valuable

IP and data with TrustZone® technology. It simplifies the design and software

development of digital signal control systems with the integrated Digital Signal Processing

(DSP) instructions. To support security requirements, the LPC55S0x/LPC550x also offers

support for HASH, AES, RSA, UUID, dynamic encrypt and decrypt, debug authentication,

and TBSA compliance.

1.2 Features

• ARM Cortex-M33 core (CPU0, r0p4):

– Running at a frequency of up to 96 MHz.

– TrustZone, Floating Point Unit (FPU) and Memory Protection Unit (MPU).

– ARM Cortex M33 built-in Nested Vectored Interrupt Controller (NVIC).

– Non-maskable Interrupt (NMI) input with a selection of sources.

– Serial Wire Debug with eight breakpoints and four watch points. Includes Serial

Wire Output for enhanced debug capabilities.

– System tick timer.

• CASPER crypto co-processor is provided to enable hardware acceleration for various

functions required for asymmetric cryptographic algorithms, such as Elliptic Curve

Cryptography (ECC).

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Chapter 1: LPC55S0x/LPC550x Introductory Information

• On-chip memory:

– Up to 256 kB on-chip flash program memory with flash accelerator and 512 byte

page erase and write.

– Up to 96 kB total SRAM consisting of 16 kB SRAM on Code Bus, 64 kB SRAM on

System Bus (64 kB is contiguous), and additional 16 kB SRAM on System Bus.

• PRINCE module for real-time encryption of data being written to on-chip flash and

decryption of encrypted flash data during read operations to allow asset protection,

such as securing application code, and enabling secure flash update.

• On-chip ROM bootloader supports:

– Booting of images from on-chip flash.

– Supports CRC32 image integrity checking.

– Supports flash programming through In System Programming (ISP) commands

over the following interfaces: UART interface (Flexcomm 0) with auto baud, SPI

slave interfaces (Flexcomm 3 or 9) using mode 3 (CPOL = 1 and CPHA = 1), and

I2C slave interface (Flexcomm 1).

– ROM API functions: Flash programming API, Power control API, and Secure

firmware update API using the NXP Secure Boot file format, version 2.0 (SB2

files).

– Supports booting of images from PRINCE encrypted flash regions.

– Supports NXP Debug Authentication Protocol version 1.0 (RSA-2048) and 1.1

(RSA-4096).

– Supports setting a sealed part to Fault Analysis mode through Debug

authentication.

• Secure Boot support:

– Uses RSASSA-PKCS1-v1_5 signature of SHA256 digest as cryptographic

signature verification.

– Supports RSA-2048 bit public keys (2048 bit modulus, 32-bit exponent).

– Supports RSA-4096 bit public keys (4096 bit modulus, 32-bit exponent).

– Uses x509 certificate format to validate image public keys.

– Supports up to four revocable Root of Trust (RoT) or Certificate Authority keys,

Root of Trust (RoT) establishment by storing the SHA-256 hash digest of the

hashes of four RoT public keys in Protected Flash Region (PFR).

– Supports anti-rollback feature using image key revocation and supports up to 16

Image key certificates revocations using Serial Number field in x509 certificate.

• Serial interfaces:

– Flexcomm Interface contains up to nine serial peripherals (Flexcomm Interface 0-7

and Flexcomm Interface 8). Each Flexcomm Interface (except Flexcomm 8, which

is dedicated for high-speed SPI) can be selected by software to be a USART, SPI,

I

2

C, and I

2

S interface. Each Flexcomm Interface includes a FIFO that supports

USART, SPI, and I

2

S. A variety of clocking options are available to each Flexcomm

Interface, including a shared fractional baud-rate generator, and time-out feature.

Flexcomm interfaces 0 to 7 each provide one channel pair of I

2

S.

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Chapter 1: LPC55S0x/LPC550x Introductory Information

– I

2

C-bus interfaces support Fast-mode and Fast-mode Plus with data rates of up to

1Mbit/s and with multiple address recognition and monitor mode. Two sets of true

I

2

C pads also support high-speed mode (3.4 Mbit/s) as a slave.

• Digital peripherals:

– DMA0 controller with 23 channels and up to 22 programmable triggers, able to

access all memories and DMA-capable peripherals.

– DMA1 controller with 10 channels and up to 15 programmable triggers, able to

access all memories and DMA-capable peripherals.

– CRC engine block can calculate a CRC on supplied data using one of three

standard polynomials with DMA support.

– Up to 45 General-Purpose Input/Output (GPIO) pins.

– GPIO registers are located on the AHB for fast access. The DMA supports GPIO

ports.

– Up to eight GPIOs can be selected as Pin Interrupts (PINT), triggered by rising,

falling or both input edges.

– Two GPIO grouped interrupts (GINT) enable an interrupt based on a logical

(AND/OR) combination of input states.

– I/O pin configuration with support for up to 16 function options.

– Programmable Logic Unit (PLU) to create small combinatorial and/or sequential

logic networks including state machines.

• Security features:

– ARM TrustZone enabled.

– AES-256 encryption/decryption engine with keys fed directly from PUF or a

software supplied key.

– Secure Hash Algorithm (SHA2) module supports secure boot with dedicated DMA

controller.

– Physical Unclonable Function (PUF) using dedicated SRAM for silicon fingerprint.

PUF can generate, store, and reconstruct key sizes from 64-bits to 4096-bits.

Includes hardware for key extraction.

– True Random Number Generator (TRNG).

– 128-bit unique device serial number for identification (UUID).

– Secure GPIO.

– Code Watchdog for detecting code flow integrity.

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Chapter 1: LPC55S0x/LPC550x Introductory Information

• Timers:

– Five 32-bit standard general purpose asynchronous timers/counters, which

support up to four capture inputs and four compare outputs, PWM mode, and

external count input. Specific timer events can be selected to generate DMA

requests.

– One SCTimer/PWM with eight input and ten output functions (including 16 capture

and match registers). Inputs and outputs can be routed to or from external pins and

internally to or from selected peripherals. Internally, the SCTimer/PWM supports 16

captures/matches, 16 events, and 32 states.

– 32-bit Real-time Clock (RTC) with 1s resolution running in the always-on power

domain. Another timer in the RTC can be used for wake-up from all low power

modes including deep-power down, with 1ms resolution. The RTC is clocked by

the 32 kHz FRO or 32.768 kHz external crystal.

– Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation at

up to four programmable, fixed rates.

– Windowed Watchdog Timer (WWDT) with FRO 1 MHz as clock source.

– The Micro-Tick Timer running from the watchdog oscillator can be used to wake-up

the device from sleep and deep-sleep modes. Includes four capture registers with

pin inputs.

– 42-bit free running OS Timer as continuous time-base for the system, available in

any reduced power modes. It runs on 32kHz clock source, allowing a count period

of more than four years.

• Analog peripherals

– 16-bit ADC with five differential channel pair (or 10 single-ended channels), and

with multiple internal and external trigger inputs and sample rates of up to 2.0

MSamples/sec.The ADC supports simultaneous conversions on two ADC input

channels belonging to a differential pair.

– Integrated temperature sensor connected to the ADC.

– Comparator with five input pins and external or internal reference voltage.

• Clock generation

– Internal Free Running Oscillator (FRO). This oscillator provides a selectable 96

MHz output, and a 12 MHz output (divided down from the selected higher

frequency) that can be used as a system clock. The FRO is trimmed to +/- 1%

accuracy over the entire voltage and 0 C to 85 C. The FRO is trimmed to +/- 2%

accuracy over the entire voltage and -40 C to 105 C.

– 32 kHz FRO. The FRO is trimmed to +/- 2% accuracy over the entire voltage and

temperature range.

– Internal low power oscillator (FRO 1 MHz) trimmed to +/- 15% accuracy over the

entire voltage and temperature range.

– High-speed crystal oscillator with an operating frequency of 12 MHz to 32 MHz.

Option for external clock input (bypass mode) for clock frequencies of up to 25

MHz.

– Crystal oscillator with 32.768 kHz operating frequency.

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Chapter 1: LPC55S0x/LPC550x Introductory Information

– PLL0 and PLL1 allows CPU operation up to the maximum CPU rate without the

need for a high-frequency external clock. PLL0 and PLL1 can run from the internal

FRO 12 MHz output, the external oscillator, internal FRO 1 MHz output, or the

32.768 kHz RTC oscillator.

– Clock output function with divider to monitor internal clocks.

– Frequency measurement unit for measuring the frequency of any on-chip or

off-chip clock signal.

– Each crystal oscillator has one embedded capacitor bank which can be used as an

integrated load capacitor. Using APIs, the capacitor banks on each crystal pin can

tune the frequency for crystals with a Capacitive Load (CL) which conserves board

space and reduces costs.

• Power-saving modes and wake-up:

– Integrated PMU (Power Management Unit) to minimize power consumption.

– Reduced power modes: Sleep, deep-sleep with RAM retention, power-down with

RAM retention and CPU0 retention, and deep power-down with RAM retention.

– Configurable wake-up options from peripherals interrupts.

– The Micro-Tick Timer running from the watchdog oscillator, and the Real-Time

Clock (RTC) running from the 32.768 kHz clock, can be used to wake-up the

device from sleep and deep-sleep modes.

– Power-On Reset (POR).

– Brown-Out Detectors (BOD) for VBAT_DCDC and internal CORE voltage with

separate thresholds for forced reset.

• Operating from internal DC-DC converter.

• Single power supply 1.8 V to 3.6 V.

• JTAG boundary scan supported.

• Operating temperature range 40 °C to +105 °C.

• Available in HTQFP64 and HVQFN48 packages.

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Chapter 1: LPC55S0x/LPC550x Introductory Information

1.3 Block diagram

Fig 1. LPC55S0x/LPC550x block diagram

Multilayer

AHB Matrix

Coprocessor interface with

math function

JTAG

boundary scan

Serial Wire

Debug

CRC

engine

SRAM2

16 KB

Code

SRAMX

16 KB

SRAM1

16 KB

SCTimer / PWM

HS GPIO

CLKINCRYSTAL CLKOUT

System

Clocks,

Power control,

DC-DC Converter,

LDOs,

system functions

PoR

PLL

BoD

FRO

MPU

Debug

Interface

ISP-AP

registers

FPU

RST_nVDD

Lx

ROM

SRAM3

16 KB

CASPER

Registers

System Functions

APB

bridge 0

2x 32-bit timer (CTIMER0, 1)

GPIO Pin Interrupts

I/O configuration

PUF KEY

Hash-AES

registers

Temp sensor

ADC:

2Ms/s, 16b, 8-diff ch.

APB

bridge 1

PMU registers

Flash Controller registers

3x 32-bit timer (CTIMER2,3,4)

In AO Power Domain

Real Time Clock,

Alarm & Wakeup

RTC time capture

32 kHz

clk (FRO/

XTAL)

WD_Osc

(FRO1M)

Windowed Watchdog

MicroTick Timer

Analog Comparator

GPIO group interrupts

Peripheral input muxes

Multi-rate Timer

PLU

HS LSPI

ANA Ctrl

Casper co-processors

Arm

Cortex-M33

AIPS Bridge

SRAM0

32 KB

PUF Key

Wrapper

DMA0

registers

Flexcomm 0-4 [1]

Flexcomm 5-7 [1]

DMA1

registers

RNG

OS_Event_Timer

Secure

HS GPIO

Secure GPIO Pin Interrupts

Flash

256 KB

Flash

interface

PRINCE

190307

DMA0

DMA1

CAN

interface

CAN

FD

Hash-

AES

Frequency Measurement Unit

CAN FD

registers

Code

WatchDog

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Chapter 1: LPC55S0x/LPC550x Introductory Information

1.4 Architectural overview

The Arm Cortex M33 includes two AHB-Lite buses, one system bus and one code bus.

The Code AHB (C-AHB) interface is used for any instruction fetch and data access to the

Code region of the ARMv8-M memory map ([0x00000000 - 0x1FFFFFFF]). The System

AHB (S-AHB) interface is used for instruction fetch and data access to all other regions of

the ARMv8-M memory map ([0x20000000 - 0xFFFFFFFF]).

The LPC55S0x/LPC550x uses a multi-layer AHB matrix to connect the Arm Cortex M33

buses and other bus masters to peripherals in a flexible manner that optimizes

performance by allowing peripherals that are on different slave ports of the matrix to be

accessed simultaneously by different bus masters.

1.5 Arm Cortex-M33 TrustZone

The Arm Cortex-M33 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption. The Arm Cortex M33 offers many new

features, including a Thumb-2 instruction set, low interrupt latency, hardware multiply and

divide, interruptable/continuable multiple load and store instructions, automatic state save

and restore for interrupts, tightly integrated interrupt controller with wake-up interrupt

controller, and multiple core buses capable of simultaneous accesses.

A 3-stage pipeline is employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The Arm Cortex-M33 provides a security foundation, offering isolation to protect valuable

IP and data with TrustZone technology. It simplifies the design and software development

of digital signal control systems with the integrated digital signal processing (DSP)

instructions.

1.6 Arm Cortex-M33 integrated Floating Point Unit (FPU)

The FPU fully supports single-precision add, subtract, multiply, divide, multiply and

accumulate, and square root operations. It also provides conversions between fixed-point

and floating-point data formats, and floating-point constant instructions.

The FPU provides floating-point computation functionality that is compliant with the

ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic, referred to

as the IEEE 754 standard.

1.7 On-chip Static RAM

The LPC55S0x/LPC550x supports 96 KB SRAM with separate bus master access for

higher throughput and individual power control for low-power operation.

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Chapter 1: LPC55S0x/LPC550x Introductory Information

1.8 Ordering information

1.8.1 Ordering options

Note:

Table 1. Ordering information

Type number Package

Name Description Version

LPC55S06JBD64 HTQFP64 plastic low profile quad flat package; 64 leads; body 10  10  0.5mm

pitch

SOT 855-5

LPC55S06JHI48 HVQFN48 plastic thermal enhanced very thin quad flat package; no leads; 48

terminals; body 7 x7 x 0.85 mm

SOT619-28

LPC55S04JBD64 HTQFP64 plastic low profile quad flat package; 64 leads; body 10  10  0.5mm

pitch

SOT 855-5

LPC55S04JHI48 HVQFN48 plastic thermal enhanced very thin quad flat package; no leads; 48

terminals; body 7 x7 x 0.85 mm

SOT619-28

LPC5506JBD64 HTQFP64 plastic low profile quad flat package; 64 leads; body 10  10  0.5mm

pitch

SOT 855-5

LPC5506JHI48 HVQFN48 plastic thermal enhanced very thin quad flat package; no leads; 48

terminals; body 7 x7 x 0.85 mm

SOT619-28

LPC5504JBD64 HTQFP64 plastic low profile quad flat package; 64 leads; body 10  10  0.5mm

pitch

SOT 855-5

LPC5504JHI48 HVQFN48 plastic thermal enhanced very thin quad flat package; no leads; 48

terminals; body 7 x7 x 0.85 mm

SOT619-28

LPC5502JBD64 HTQFP64 plastic low profile quad flat package; 64 leads; body 10  10  0.5mm

pitch

SOT 855-5

LPC5502JHI48 HVQFN48 plastic thermal enhanced very thin quad flat package; no leads; 48

terminals; body 7 x7 x 0.85 mm

SOT619-28

Table 2. Ordering options

Type number

Flash/KB

Total SRAM/KB

Secure boot

TrustZone

PUF Controller

HASH-AES

RNG

CASPER

PRINCE

CAN FD

GPIO

ADC Channels

LPC55S06JBD64 256 96 yes yes yes yes yes yes yes CAN FD 45 9

LPC55S06JHI48 256 96 yes yes yes yes yes yes yes CAN FD 30 7

LPC55S04JBD64 128 80 yes yes yes yes yes yes yes CAN FD 45 9

LPC55S04JHI48 128 80 yes yes yes yes yes yes yes CAN FD 30 7

LPC5506JBD64 256 96 - - - - yes - - CAN2.0 45 9

LPC5506JHI48 256 96 - - - - yes - - CAN2.0 30 7

LPC5504JBD64 128 80 - - - - yes - - CAN2.0 45 9

LPC5504JHI48 128 80 - - - - yes - - CAN2.0 30 7

LPC5502JBD64 64 48 - - - - yes - - CAN2.0 45 9

LPC5502JHI48 64 48 - - - - yes - - CAN2.0 30 7

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Chapter 1: LPC55S0x/LPC550x Introductory Information

HTQFP64: up to 8 Flexcomm interfaces (UART up to 8, I2C up to 8, I2S up to 8 and SPI

up to 6) + 1 HS SPI.

HVQFN48: up to 7 Flexcomm interfaces (UART up to 7, I2C up to 7, I2S up to 4 and SPI

up to 3) + 1 HS SPI.

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2.1 General description

2.1.1 AHB multilayer matrix

The LPC55S0x/LPC550x uses a multi-layer AHB matrix to connect the CPU buses and

other bus masters to peripherals in a flexible manner that optimizes performance by

allowing peripherals that are on different slave ports of the matrix to be accessed

simultaneously by different bus masters. The device block diagram in

Figure 1 shows

details of the available matrix connections.

2.1.2 Memory Protection Unit (MPU)

CPU0 has a memory protection unit (MPU) that provides fine grain memory control,

enabling applications to implement security privilege levels, separating code, data and

stack on a task-by-task basis. Such requirements are critical in many embedded

applications.

The MPU register interface is located on the CPU private peripheral bus.

2.1.3 TrustZone and system mapping on this device

The implementation of ARM TrustZone for CPU0 involves using address bit 28 to divide

the address space into potential secure and non-secure regions. Address bit 28 is not

decoded in memory access hardware, so each physical location appears in two places on

whatever bus they are located on. Other hardware determines which kinds of accesses

(including non-secure callable) are actually allowed for any particular address.

Tabl e 3 shows the overall mapping of the code and data buses for secure and non-secure

accesses to various device resources.

Remark: In the peripheral description chapters of this manual, only the native

(non-secure) base address is noted, secure base addresses can be found in this chapter

or created by setting bit 28 in the address as needed.

[1] The size shown for peripheral spaces indicates the space allocated in the memory map, not the actual

space used by the peripheral or memory.

[2] Selected areas of secure regions may be marked as non-secure callable.

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Table 3. TrustZone and system general mapping

Start address End address TrustZone, CPU0 CPU bus CM-33 usage

0x0000 0000 0x0FFF FFFF Non-secure Code Flash memory, Boot ROM, SRAM X.

0x1000 0000 0x1FFF FFFF Secure Code Flash memory, Boot ROM, SRAM X.

0x2000 0000 0x2FFF FFFF Non-secure Data SRAM 0, SRAM 1, SRAM 2, SRAM 3.

0x3000 0000 0x3FFF FFFF Secure Data SRAM 0, SRAM 1, SRAM 2, SRAM 3.

0x4000 0000 0x4FFF FFFF Non-secure Data AHB and APB peripherals.

0x5000 0000 0x5FFF FFFF Secure Data AHB and APB peripherals.

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Chapter 2: LPC55S0x/LPC550x Memory Map

2.1.4 Links to specific memory map descriptions and tables:

• Section 2.1.5 “Memory map overview”

• Section 2.1.6 “APB peripherals”

• Section 2.1.7 “AHB peripherals”

2.1.5 Memory map overview

Tabl e 4 provides a more detailed memory map as seen by the 2 Cortex-M33. The purpose

of the four address spaces for the shared RAMs is outlined at the beginning of this

chapter. The details of which shared RAM regions are on which AHB matrix slave ports

can be seen here.

[1] Gaps between AHB matrix slave ports are not shown.

Table 4. Memory map overview

AHB

port

Non-secure

start address

Non-secure

end address

Secure start

address

Secure end

address

Function

[1]

0 0x0000 0000 0x0003 FFFF 0x1000 0000 0x1003 FFFF Flash memory, on CM33 code bus. The last 17 pages

(12KB) are reserved on the 256 KB flash devices

resulting in 244 KB internal flash memory.

0x0300 0000 0x0301 FFFF 0x1300 0000 0x1301 FFFF Boot ROM, on CM33 code bus.

1 0x0400 0000 0x0400 3FFF 0x1400 0000 0x1400 3FFF SRAM X on CM33 code bus, 32 KB. SRAMX_0

(0x1400 0000 to 0x1400 0FFF) and SRAMX_1

(0x1400 1000 to 0x1400 1FFF) are used for Casper

(total 8 KB). If CPU retention used in power-down

mode, SRAMX_2 (0x1400 2000 to 0x1400 25FF) is

used (total 1.5 KB) by default in power API and this is

user configurable within SRAMX_2 and SRAMX_3.

2 0x2000 0000 0x2000 7FFF 0x3000 0000 0x3000 7FFF SRAM 0 on CM33 data bus, 32 KB.

3 0x2000 8000 0x2000 BFFF 0x3000 8000 0x3000 BFFF SRAM 1 on CM33 data bus, 16 KB.

4 0x2000 C000 0x2000 FFFF 0x3000 C000 0x3000 FFFF SRAM 2 on CM33 data bus, 16 KB.

5 0x2001 0000 0x2001 3FFF 0x3001 0000 0x3001 3FFF SRAM 3, 16 KB.

6 0x4000 0000 0x4001 FFFF 0x5000 0000 0x5001 FFFF AHB to APB bridge 0. See

Section 2.1.6.

0x4002 0000 0x4003 FFFF 0x5002 0000 0x5003 FFFF AHB to APB bridge 1. See

Section 2.1.6.

7 0x4008 0000 0x4008 FFFF 0x5008 0000 0x5008 FFFF AHB peripherals. See

Section 2.1.7.

8 0x4009 0000 0x4009 FFFF 0x5009 0000 0x5009 FFFF AHB peripherals. See

Section 2.1.7.

9 0x400A 0000 0x400A FFFF 0x500A 0000 0x500A FFFF AHB peripherals. See

Section 2.1.7.

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Chapter 2: LPC55S0x/LPC550x Memory Map

2.1.6 APB peripherals

Tabl e 5 provides details of the addresses for APB peripherals. APB peripherals have both

secure and non-secure access.

Table 5. APB peripherals memory map

APB

bridge

Non-secure

base address

Secure

base address

Peripheral

0 0x4000 0000 0x5000 0000 Syscon.

0x4000 1000 0x5000 1000 Pin function selection and pin control setup (IOCON).

0x4000 2000 0x5000 2000 Group GPIO input interrupt 0 (GINT0).

0x4000 3000 0x5000 3000 Group GPIO input interrupt 1 (GINT1).

0x4000 4000 0x5000 4000 Pin interrupt and pattern match (PINT).

0x4000 5000 0x5000 5000 Secure pin interrupt and pattern match.

0x4000 6000 0x5000 6000 Input multiplexing 0 and frequency measure (INPUTMUX).

0x4000 7000 0x5000 7000 Reserved.

0x4000 8000 0x5000 8000 Standard counter/timer 0 (CTimer0).

0x4000 9000 0x5000 9000 Standard counter/timer 1 (CTimer1).

0x4000 C000 0x5000 C000 Windowed watchdog timer 0 (WWDT0).

0x4000 D000 0x5000 D000 Multi-Rate timer (MRT).

0x4000 E000 0x5000 E000 Micro-Tick timer (Utick).

0x4001 3000 0x5001 3000 Analog controls.

0x4001 5000 0x5001 5000 Reserved.

1 0x4002 3000 0x5002 3000 I

2

S signal sharing (Sysctl).

0x4002 8000 0x5002 8000 Standard counter/timer 2 (Timer2).

0x4002 9000 0x5002 9000 Standard counter/timer 3 (Timer3).

0x4002 A000 0x5002 A000 Standard counter/timer 4 (Timer4).

0x4002 C000 0x5002 C000 RTC & Wake-up timer.

0x4002 D000 0x5002 D000 OS_Event Timer.

0x4003 4000 0x5003 4000 Flash controller.

0x4003 5000 0x5003 5000 PRINCE dynamic encrypt/decrypt.

0x4003 8000 0x5003 8000 Reserved.

0x4003 A000 0x5003 A000 True Random Number Generator.

0x4003 B000 0x5003 B000 Physical Unclonable Function (PUF).

0x4003 D000 0x5003 D000 Programmable Logic Unit (PLU).

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Chapter 2: LPC55S0x/LPC550x Memory Map

2.1.7 AHB peripherals

Tabl e 6 provides details of the addresses for AHB peripherals. AHB peripherals have both

secure and non-secure access.

Table 6. AHB peripheral memory map

AHB port Non-secure

base address

Secure

base address

Peripheral

7 0x4008 2000 0x5008 2000 DMA0 registers.

0x4008 4000 0x5008 4000 Reserved.

0x4008 5000 0x5008 5000 SCTimer/PWM.

0x4008 6000 0x5008 6000 Flexcomm Interface 0.

0x4008 7000 0x5008 7000 Flexcomm Interface 1.

0x4008 8000 0x5008 8000 Flexcomm Interface 2.

0x4008 9000 0x5008 9000 Flexcomm Interface 3.

0x4008 A000 0x5008 A000 Flexcomm Interface 4.

0x4008 C000 0x5008 C000 High-Speed GPIO.

8 0x4009 4000 0x5009 4000 Reserved.

0x4009 5000 0x5009 5000 CRC Engine.

0x4009 6000 0x5009 6000 Flexcomm Interface 5.

0x4009 7000 0x5009 7000 Flexcomm Interface 6.

0x4009 8000 0x5009 8000 Flexcomm Interface 7.

0x4009 D000 0x5009 C000 Debug Mailbox (DM-AP).

0x4009 C000 0x5009 D000 CAN0.

0x4009 F000 0x5009 F000 High Speed SPI (SPI8).

9 0x400A 0000 0x500A 0000 ADC0.

0x400A 1000 0x500A 1000 Code Watchdog (CDOG).

0x400A 2000 0x500A 2000 Reserved.

0x400A 3000 0x500A 3000 Reserved.

0x400A 4000 0x500A 4000 Hash-AES registers.

0x400A 5000 0x500A 5000 Casper.

0x400A 7000 0x500A 7000 DMA1 registers.

0x400A 8000 0x500A 8000 Secure HS GPIO.

0x400A C000 0x500A C000 Security control registers.

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Chapter 2: LPC55S0x/LPC550x Memory Map

2.1.8 RAM configuration

Tabl e 7 describes the RAM configuration for the LPC55S0x/LPC550x.

Table 7. RAM Configuration

RAM Total RAM-X (KB) RAM0 (KB) RAM1 (KB) RAM2 (KB) RAM3 (KB)

96 KB devices 16 32 16 16 16

80 KB devices 16 32 16 16 (for 80k; it is

RAMx+RAM0+RAM

1+RAM2)

- (for 80k; it is

RAMx+RAM0+RAM

1+RAM2)

48 KB devices 16 32 - - -

User manual Rev. 1.0 — 20 October 2020 17 of 1015

3.1 How to read this chapter

Available interrupt sources may vary with specific LPC55xx device types.

3.2 Features

• Nested Vectored Interrupt Controller (NVIC) is an integral part of the CPU.

• A tightly coupled interrupt controller provides low interrupt latency.

• Controls system exceptions and peripheral interrupts.

• The NVIC for the Cortex-M33 supports:

– 64 vectored interrupt slots

.

– Eight programmable interrupt priority levels with hardware priority level masking.

– Vector Table Offset Register VTOR.

– Software interrupt generation.

– Support for NMI from any interrupt, see

Section 21.4.3 “GPIO grouped interrupt

port enable registers”.

3.3 General description

The tight coupling of the NVIC to the CPU allows for low interrupt latency and the efficient

processing of late arriving interrupts.

3.3.1 Interrupt sources

Tabl e 8 lists the interrupt sources for each peripheral function. Each peripheral device can

have one or more interrupt lines to the Vectored Interrupt Controller. Each line may

represent more than one interrupt source. The interrupt number does not imply any

interrupt priority when interrupts are not given the same priority. As an example, in the

case where two interrupts are given the same priority, the interrupt numbers shown in the

table are relevant.

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Chapter 3: LPC55S0x/LPC550x Nested Vectored Interrupt

Controller (NVIC)

Rev. 1.0 — 20 October 2020 User manual

Table 8. Connection of interrupt sources to the NVIC

Interrupt Name Interrupt description Flags

0 WDT_BOD_IRQn Device specific interrupts. Windowed watchdog timer,

Brownout detect, Flash interrupt.

1 DMA0_IRQn DMA0 controller. Interrupt A and interrupt B, error

interrupt.

2 GINT0_IRQn GPIO group 0. Enabled pin interrupts.

3 GINT1_IRQn GPIO group 1. Enabled pin interrupts.

4 PIN_INT0_IRQn Pin interrupt 0 or pattern match engine slice 0. PSTAT - pin interrupt status.

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Chapter 3: LPC55S0x/LPC550x Nested Vectored Interrupt Controller

5 PIN_INT1_IRQn Pin interrupt 1 or pattern match engine slice 1. PSTAT - pin interrupt status.

6 PIN_INT2_IRQn Pin interrupt 2 or pattern match engine slice 2. PSTAT - pin interrupt status.

7 PIN_INT3_IRQn Pin interrupt 3 or pattern match engine slice 3. PSTAT - pin interrupt status.

8 UTICK0_IRQn Micro-tick timer. INTR.

9 MRT0_IRQn Multi-rate timer. Global MRT interrupts: GFLAG0,

1, 2, 3.

10 CTIMER0_IRQn Standard counter/timer CTIMER0. Match and capture interrupts.

11 CTIMER1_IRQn Standard counter/timer CTIMER1. Match and capture interrupts.

12 SCT0_IRQn SCTimer/PWM. EVFLAG SCT event.

13 CTIMER3_IRQn Standard counter/timer CTIMER3 Match and capture interrupts.

14 FLEXCOMM0_IRQn Flexcomm Interface 0 (USART, SPI, I

2

C, I

2

S,

FLEXCOMM).

See enable read and set register

of this module.

15 FLEXCOMM1_IRQn Flexcomm Interface 1 (USART, SPI, I

2

C, I

2

S,

FLEXCOMM).

Same as Flexcomm0.

16 FLEXCOMM2_IRQn Flexcomm Interface 2 (USART, SPI, I

2

C, I

2

S,

FLEXCOMM).

Same as Flexcomm0.

17 FLEXCOMM3_IRQn Flexcomm Interface 3 (USART, SPI, I

2

C, I

2

S,

FLEXCOMM).

Same as Flexcomm0.

18 FLEXCOMM4_IRQn Flexcomm Interface 4 (USART, SPI, I

2

C, I

2

S,

FLEXCOMM).

Same as Flexcomm0.

19 FLEXCOMM5_IRQn Flexcomm Interface 5 (USART, SPI,I

2

C, I

2

S,

FLEXCOMM).

Same as Flexcomm0.

20 FLEXCOMM6_IRQn Flexcomm Interface 6 (USART, SPI, I

2

C, I

2

S,

FLEXCOMM).

Same as Flexcomm0.

21 FLEXCOMM7_IRQn Flexcomm Interface 7 (USART, SPI, I

2

C, I

2

S,

FLEXCOMM).

Same as Flexcomm0.

22 ADC0_IRQn ADC0. See enable read and set register

of this module.

23 Reserved39_IRQn Reserved interrupt. -

24 ACMP_IRQn ACMP interrupts. See enable read and set register

of this module.

25 Reserved41_IRQn Reserved interrupt. -

26 Reserved42_IRQn Reserved interrupt. -

27 Reserved43_IRQn Reserved interrupt. -

28 Reserved44_IRQn Reserved interrupt. -

29 RTC_IRQn RTC alarm and wake-up interrupts. See enable read and set register

of this module.

30 Reserved46_IRQn Reserved interrupt. -

31 WAKEUP_IRQn Wakeup for low power mode (Power Down) use

when wakeupio is enabled during power down.

See WAKEIOCAUSE register in

power management chapter.

32 PIN_INT4_IRQn Pin interrupt 4 or pattern match engine slice 4 int. PSTAT - pin interrupt status.

33 PIN_INT5_IRQn Pin interrupt 5 or pattern match engine slice 5 int. PSTAT - pin interrupt status.

34 PIN_INT6_IRQn Pin interrupt 6 or pattern match engine slice 6 int. PSTAT - pin interrupt status.

35 PIN_INT7_IRQn Pin interrupt 7 or pattern match engine slice 7 int. PSTAT - pin interrupt status.

Table 8. Connection of interrupt sources to the NVIC

Interrupt Name Interrupt description Flags

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36 CTIMER2_IRQn Standard counter/timer CTIMER2. Match and capture interrupts.

37 CTIMER4_IRQn Standard counter/timer CTIMER4. Match and capture interrupts.

38 OS_EVENT_IRQn OS_EVENT_TIMER and OS_EVENT_WAKEUP

interrupts.

-

39 Reserved55_IRQn Reserved interrupt. -

40 Reserved56_IRQn Reserved interrupt. -

41 Reserved57_IRQn Reserved interrupt. -

42 Reserved58_IRQn Reserved interrupt. -

43 CAN0_IRQ0_IRQn CAN Interrupt 0. CAN Interrupts.

44 CAN0_IRQ1_IRQn CAN Interrupt 1. CAN Interrupts.

45 Reserved. Reserved. -

46 Reserved. Reserved. -

47 Reserved. Reserved. -

48 Reserved. Reserved. -

49 SEC_HYPERVISOR_CA

LL_IRQn

SEC_HYPERVISOR_CALL interrupt HF interrupts.

50 SEC_GPIO_INT0_IRQ0_I

RQn

Secure GPIO function is available on P0(0-31)

and 2x Pin Interrupt outputs are available to

NVIC.

SGPIO 0 interrupts.

51 SEC_GPIO_INT1_IRQ0_I

RQn

Secure GPIO function is available on P0(0-31)

and 2x Pin Interrupt outputs are available to

NVIC.

SGPIO 1 interrupts.

52 PLU_IRQn Programmable Logic Unit. PLU interrupts.

53 SEC_VIO_IRQn Secure violation interrupt. Secure violation interrupts.

54 HASHCRYPT_IRQn SHA interrupt. Hash interrupts.

55 CASPER CASPER Crypto co-processor interrupt. Casper interrupts.

56 PUF PUF Controller Interrupt. PUF interrupts.

57 Reserved - -

58 SDMA1 Secure DMA (DMA1) controller. Secure DMA interrupts.

59 HS_SPI HS_SPI. HS_SPI.

60 CDOG CDOG Interrupt. CDOG Interrupts.

Table 8. Connection of interrupt sources to the NVIC

Interrupt Name Interrupt description Flags

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Chapter 3: LPC55S0x/LPC550x Nested Vectored Interrupt Controller

3.4 Register description

The NVIC registers are located on the ARM private peripheral bus.

Table 9. Register overview: NVIC (base address = 0xe000e100)

Name Access Offset Description Reset

value

Section

ISER0 R/W 0x100 Interrupt set enable register 0. This register allows enabling

interrupts and reading back the interrupt enables for peripheral

functions.

0

3.4.1

ISER1 R/W 0x104 Interrupt set enable register 1. See ISER0 description. 0 3.4.2

ICER0 R/W 0x180 Interrupt clear enable register 0. This register allows disabling

interrupts and reading back the interrupt enables for peripheral

functions.

0 3.4.3

ICER1 R/W 0x184 Interrupt clear enable register 1. See ISER0 description. 0 3.4.4

ISPR0 R/W 0x200 Interrupt set pending register 0. This register allows changing

the interrupt state to pending and reading back the interrupt

pending state for peripheral functions.

0 3.4.5

ISPR1 R/W 0x204 Interrupt set pending register 1. See ISPR0 description. 0 3.4.6

ICPR0 R/W 0x280 Interrupt clear pending register 0. This register allows changing

the interrupt state to not pending and reading back the interrupt

pending state for peripheral functions.

0 3.4.7

ICPR1 R/W 0x284 Interrupt clear pending register 1. See ICPR0 description. 0 3.4.8

IABR0 RO 0x300 Interrupt active bit register 0. This register allows reading the

current interrupt active state for specific peripheral functions.

0 3.4.9

IABR1 RO 0x304 Interrupt active bit register 1. See IABR0 description. 0 3.4.10

IPR0 R/W 0x400 Interrupt priority register 0. This register contains the 3-bit

priority fields for interrupts 0 to 3.

0 3.4.11

IPR1 R/W 0x404 Interrupt priority register 1. This register contains the 3-bit

priority fields for interrupts 4 to 7.

0 3.4.12

IPR2 R/W 0x408 Interrupt priority register2. This register contains the 3-bit

priority fields for interrupts 8 to 11.

0 3.4.13

IPR3 R/W 0x40C Interrupt priority register 3. This register contains the 3-bit

priority fields for interrupts 12 to 15.

0 3.4.14

IPR4 R/W 0x410 Interrupt priority register 4. This register contains the 3-bit

priority fields for interrupts 16 to 19.

0 3.4.15

IPR5 R/W 0x414 Interrupt priority register 5. This register contains the 3-bit

priority fields for interrupts 20 to 23.

0 3.4.16

IPR6 R/W 0x418 Interrupt priority register 6. This register contains the 3-bit

priority fields for interrupts 24 to 27.

0 3.4.17

IPR7 R/W 0x41C Interrupt priority register 7. This register contains the 3-bit

priority fields for interrupts 28 to 31.

0 3.4.18

IPR8 R/W 0x420 Interrupt priority register 8. This register contains the 3-bit

priority fields for interrupts 32 to 35.

0 3.4.19

IPR9 R/W 0x424 Interrupt priority register 9. This register contains the 3-bit

priority fields for interrupts 36 to 39.

0 3.4.20

IPR10 R/W 0x428 Interrupt priority register 10. This register contains the 3-bit

priority fields for interrupts 40 to 43.

0 3.4.21

NXP LPC550x/S0x User guide

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