KL43 Sub-Family Reference Manual
Supports: MKL43Z128VLH4, MKL43Z256VLH4, MKL43Z128VMP4,
MKL43Z256VMP4
Document Number: KL43P64M48SF6RM
Rev. 5.1, 07/2016
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Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................39
1.1.1 Purpose...........................................................................................................................................................39
1.1.2 Audience........................................................................................................................................................ 39
1.2 Conventions.................................................................................................................................................................. 39
1.2.1 Numbering systems........................................................................................................................................39
1.2.2 Typographic notation..................................................................................................................................... 40
1.2.3 Special terms..................................................................................................................................................40
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................41
2.1.1 Sub-family introduction................................................................................................................................. 41
2.2 Module functional categories........................................................................................................................................42
2.2.1 ARM Cortex-M0+ core modules................................................................................................................... 43
2.2.2 System modules............................................................................................................................................. 43
2.2.3 Memories and memory interfaces..................................................................................................................44
2.2.4 Clocks.............................................................................................................................................................44
2.2.5 Security and integrity modules...................................................................................................................... 45
2.2.6 Analog modules............................................................................................................................................. 45
2.2.7 Timer modules............................................................................................................................................... 45
2.2.8 Communication interfaces............................................................................................................................. 46
2.2.9 Human-machine interfaces............................................................................................................................ 47
2.3 Module to module interconnects...................................................................................................................................47
2.3.1 Interconnection overview...............................................................................................................................47
2.3.2 Analog reference options............................................................................................................................... 49
Chapter 3
Core Overview
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3.1 ARM Cortex-M0+ core introduction............................................................................................................................51
3.1.1 Buses, interconnects, and interfaces.............................................................................................................. 51
3.1.2 System tick timer........................................................................................................................................... 51
3.1.3 Debug facilities.............................................................................................................................................. 51
3.1.4 Core privilege levels...................................................................................................................................... 52
3.2 Nested vectored interrupt controller (NVIC) ...............................................................................................................52
3.2.1 Interrupt priority levels.................................................................................................................................. 52
3.2.2 Non-maskable interrupt..................................................................................................................................52
3.2.3 Interrupt channel assignments........................................................................................................................52
3.3 AWIC introduction....................................................................................................................................................... 55
3.3.1 Wake-up sources............................................................................................................................................55
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................57
4.2 Flash memory............................................................................................................................................................... 57
4.2.1 Flash memory map.........................................................................................................................................57
4.2.2 Flash security................................................................................................................................................. 58
4.2.3 Flash modes....................................................................................................................................................58
4.2.4 Erase all flash contents...................................................................................................................................58
4.2.5 FTFA_FOPT register..................................................................................................................................... 58
4.3 SRAM........................................................................................................................................................................... 59
4.3.1 SRAM sizes....................................................................................................................................................59
4.3.2 SRAM ranges.................................................................................................................................................59
4.3.3 SRAM retention in low power modes............................................................................................................60
4.4 System Register file......................................................................................................................................................60
4.5 System memory map.....................................................................................................................................................61
4.6 Bit Manipulation Engine...............................................................................................................................................61
4.7 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................62
4.7.1 Read-after-write sequence and required serialization of memory operations................................................62
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4.7.2 Peripheral bridge (AIPS-Lite) memory map..................................................................................................63
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................67
5.2 Programming model......................................................................................................................................................67
5.3 High-level device clocking diagram............................................................................................................................. 67
5.4 Clock definitions...........................................................................................................................................................68
5.4.1 Device clock summary...................................................................................................................................69
5.5 Internal clocking requirements..................................................................................................................................... 71
5.5.1 Clock divider values after reset......................................................................................................................72
5.5.2 VLPR mode clocking.....................................................................................................................................72
5.6 Clock gating..................................................................................................................................................................73
5.7 Module clocks...............................................................................................................................................................73
5.7.1 PMC 1-kHz LPO clock..................................................................................................................................74
5.7.2 COP clocking................................................................................................................................................. 74
5.7.3 RTC clocking................................................................................................................................................. 75
5.7.4 RTC_CLKOUT and CLKOUT32K clocking................................................................................................75
5.7.5 LPTMR clocking............................................................................................................................................76
5.7.6 TPM clocking.................................................................................................................................................77
5.7.7 USB FS device only controller clocking........................................................................................................77
5.7.8 LPUART clocking......................................................................................................................................... 78
5.7.9 FlexIO clocking..............................................................................................................................................79
5.7.10 I2S/SAI clocking............................................................................................................................................80
5.7.11 SLCD clocking...............................................................................................................................................80
Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................83
6.2 Reset..............................................................................................................................................................................83
6.2.1 Power-on reset (POR).................................................................................................................................... 84
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6.2.2 System reset sources...................................................................................................................................... 84
6.2.3 MCU resets.................................................................................................................................................... 87
6.2.4 RESET pin .................................................................................................................................................... 88
6.3 Boot...............................................................................................................................................................................88
6.3.1 Boot sources...................................................................................................................................................89
6.3.2 FOPT boot options.........................................................................................................................................89
6.3.3 Boot sequence................................................................................................................................................ 91
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................93
7.2 Clocking modes............................................................................................................................................................ 93
7.2.1 Partial Stop.....................................................................................................................................................93
7.2.2 DMA Wakeup................................................................................................................................................94
7.2.3 Compute Operation........................................................................................................................................95
7.2.4 Peripheral Doze..............................................................................................................................................96
7.2.5 Clock gating................................................................................................................................................... 97
7.3 Power modes.................................................................................................................................................................97
7.4 Entering and exiting power modes............................................................................................................................... 99
7.5 Module operation in low-power modes........................................................................................................................ 100
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................105
8.1.1 Flash security................................................................................................................................................. 105
8.1.2 Security interactions with other modules.......................................................................................................105
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................107
9.2 Debug port pin descriptions..........................................................................................................................................107
9.3 SWD status and control registers..................................................................................................................................108
9.3.1 MDM-AP Control Register............................................................................................................................109
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9.3.2 MDM-AP Status Register.............................................................................................................................. 110
9.4 Debug resets..................................................................................................................................................................112
9.5 Micro Trace Buffer (MTB)...........................................................................................................................................112
9.6 Debug in low-power modes..........................................................................................................................................113
9.7 Debug and security....................................................................................................................................................... 114
Chapter 10
Pinouts and Packaging
10.1 Introduction...................................................................................................................................................................115
10.2 Signal multiplexing integration.................................................................................................................................... 115
10.2.1 Clock gating................................................................................................................................................... 116
10.2.2 Signal multiplexing constraints......................................................................................................................116
10.3 KL43 Signal Multiplexing and Pin Assignments......................................................................................................... 116
10.4 KL43 Family Pinouts....................................................................................................................................................119
10.5 Module Signal Description Tables................................................................................................................................121
10.5.1 Core modules................................................................................................................................................. 121
10.5.2 System modules............................................................................................................................................. 121
10.5.3 Clock modules................................................................................................................................................122
10.5.4 Analog............................................................................................................................................................122
10.5.5 Timer Modules...............................................................................................................................................123
10.5.6 Communication interfaces............................................................................................................................. 124
10.5.7 Human-machine interfaces (HMI).................................................................................................................127
Chapter 11
Port Control and Interrupts (PORT)
11.1 Chip-specific PORT information..................................................................................................................................129
11.2 Port control and interrupt summary.............................................................................................................................. 130
11.3 Introduction...................................................................................................................................................................131
11.4 Overview.......................................................................................................................................................................131
11.4.1 Features.......................................................................................................................................................... 131
11.4.2 Modes of operation........................................................................................................................................ 132
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11.5 External signal description............................................................................................................................................133
11.6 Detailed signal description............................................................................................................................................133
11.7 Memory map and register definition.............................................................................................................................133
11.7.1
Pin Control Register n (PORTx_PCRn).........................................................................................................139
11.7.2
Global Pin Control Low Register (PORTx_GPCLR)....................................................................................142
11.7.3
Global Pin Control High Register (PORTx_GPCHR)...................................................................................142
11.7.4
Interrupt Status Flag Register (PORTx_ISFR).............................................................................................. 143
11.8 Functional description...................................................................................................................................................143
11.8.1 Pin control......................................................................................................................................................143
11.8.2 Global pin control.......................................................................................................................................... 144
11.8.3 External interrupts..........................................................................................................................................144
Chapter 12
System Integration Module (SIM)
12.1 Chip-specific SIM information.....................................................................................................................................147
12.1.1 COP clocks.....................................................................................................................................................147
12.2 Introduction...................................................................................................................................................................147
12.2.1 Features.......................................................................................................................................................... 147
12.3 Memory map and register definition.............................................................................................................................148
12.3.1 System Options Register 1 (SIM_SOPT1).................................................................................................... 149
12.3.2 SOPT1 Configuration Register (SIM_SOPT1CFG)......................................................................................150
12.3.3 System Options Register 2 (SIM_SOPT2).................................................................................................... 152
12.3.4 System Options Register 4 (SIM_SOPT4).................................................................................................... 154
12.3.5 System Options Register 5 (SIM_SOPT5).................................................................................................... 155
12.3.6 System Options Register 7 (SIM_SOPT7).................................................................................................... 157
12.3.7 System Device Identification Register (SIM_SDID).....................................................................................158
12.3.8 System Clock Gating Control Register 4 (SIM_SCGC4)..............................................................................160
12.3.9 System Clock Gating Control Register 5 (SIM_SCGC5)..............................................................................162
12.3.10 System Clock Gating Control Register 6 (SIM_SCGC6)..............................................................................164
12.3.11 System Clock Gating Control Register 7 (SIM_SCGC7)..............................................................................166
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12.3.12 System Clock Divider Register 1 (SIM_CLKDIV1).....................................................................................166
12.3.13 Flash Configuration Register 1 (SIM_FCFG1)............................................................................................. 168
12.3.14 Flash Configuration Register 2 (SIM_FCFG2)............................................................................................. 169
12.3.15 Unique Identification Register Mid-High (SIM_UIDMH)............................................................................170
12.3.16 Unique Identification Register Mid Low (SIM_UIDML)............................................................................. 171
12.3.17 Unique Identification Register Low (SIM_UIDL)........................................................................................ 171
12.3.18 COP Control Register (SIM_COPC)............................................................................................................. 172
12.3.19 Service COP (SIM_SRVCOP).......................................................................................................................173
12.4 Functional description...................................................................................................................................................173
12.4.1 COP watchdog operation............................................................................................................................... 174
Chapter 13
Kinetis ROM Bootloader
13.1 Chip-Specific Information............................................................................................................................................ 177
13.2 Introduction...................................................................................................................................................................177
13.3 Functional Description..................................................................................................................................................179
13.3.1 Memory Maps................................................................................................................................................179
13.3.2 The Kinetis Bootloader Configuration Area (BCA)......................................................................................180
13.3.3 Start-up Process..............................................................................................................................................181
13.3.4 Clock Configuration.......................................................................................................................................183
13.3.5 Bootloader Entry Point...................................................................................................................................184
13.3.6 Bootloader Protocol....................................................................................................................................... 185
13.3.7 Bootloader Packet Types............................................................................................................................... 190
13.3.8 Bootloader Command API.............................................................................................................................197
13.3.9 Bootloader Exit state......................................................................................................................................212
13.4 Peripherals Supported................................................................................................................................................... 213
13.4.1 I2C Peripheral................................................................................................................................................ 213
13.4.2 SPI Peripheral................................................................................................................................................ 215
13.4.3 USB peripheral...............................................................................................................................................217
13.5 Get/SetProperty Command Properties..........................................................................................................................221
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13.5.1 Property Definitions.......................................................................................................................................222
13.6 Kinetis Bootloader Status Error Codes.........................................................................................................................224
13.7 Bootloader errata...........................................................................................................................................................225
Chapter 14
System Mode Controller (SMC)
14.1 Chip-specific SMC information....................................................................................................................................227
14.2 Introduction...................................................................................................................................................................227
14.3 Modes of operation....................................................................................................................................................... 227
14.4 Memory map and register descriptions.........................................................................................................................229
14.4.1 Power Mode Protection register (SMC_PMPROT).......................................................................................230
14.4.2 Power Mode Control register (SMC_PMCTRL)...........................................................................................231
14.4.3 Stop Control Register (SMC_STOPCTRL)...................................................................................................232
14.4.4 Power Mode Status register (SMC_PMSTAT)............................................................................................. 234
14.5 Functional description...................................................................................................................................................234
14.5.1 Power mode transitions..................................................................................................................................234
14.5.2 Power mode entry/exit sequencing................................................................................................................ 237
14.5.3 Run modes......................................................................................................................................................239
14.5.4 Wait modes.................................................................................................................................................... 241
14.5.5 Stop modes.....................................................................................................................................................242
14.5.6 Debug in low power modes........................................................................................................................... 245
Chapter 15
Power Management Controller (PMC)
15.1 Introduction...................................................................................................................................................................247
15.2 Features.........................................................................................................................................................................247
15.3 Low-voltage detect (LVD) system................................................................................................................................247
15.3.1 LVD reset operation.......................................................................................................................................248
15.3.2 LVD interrupt operation.................................................................................................................................248
15.3.3 Low-voltage warning (LVW) interrupt operation......................................................................................... 248
15.4 I/O retention..................................................................................................................................................................249
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15.5 Memory map and register descriptions.........................................................................................................................249
15.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1).......................................................... 250
15.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2).......................................................... 251
15.5.3 Regulator Status And Control register (PMC_REGSC)................................................................................252
Chapter 16
Miscellaneous Control Module (MCM)
16.1 Introduction...................................................................................................................................................................255
16.1.1 Features.......................................................................................................................................................... 255
16.2 Memory map/register descriptions............................................................................................................................... 255
16.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)..................................................................256
16.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC).............................................................. 256
16.2.3 Platform Control Register (MCM_PLACR)..................................................................................................257
16.2.4 Compute Operation Control Register (MCM_CPO)..................................................................................... 260
Chapter 17
Crossbar Switch Lite (AXBS-Lite)
17.1 Chip-specific AXBS-Lite information..........................................................................................................................263
17.1.1 Crossbar-light switch master assignments..................................................................................................... 263
17.1.2 Crossbar switch slave assignments................................................................................................................ 263
17.2 Introduction...................................................................................................................................................................263
17.2.1 Features.......................................................................................................................................................... 264
17.3 Memory Map / Register Definition...............................................................................................................................264
17.4 Functional Description..................................................................................................................................................264
17.4.1 General operation...........................................................................................................................................264
17.4.2 Arbitration......................................................................................................................................................265
17.5 Initialization/application information........................................................................................................................... 267
Chapter 18
Low-Leakage Wakeup Unit (LLWU)
18.1 LLWU interrupt............................................................................................................................................................ 269
18.1.1 Wake-up Sources........................................................................................................................................... 269
18.2 Introduction...................................................................................................................................................................270
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18.2.1 Features.......................................................................................................................................................... 270
18.2.2 Modes of operation........................................................................................................................................ 271
18.2.3 Block diagram................................................................................................................................................272
18.3 LLWU signal descriptions............................................................................................................................................ 273
18.4 Memory map/register definition................................................................................................................................... 273
18.4.1 LLWU Pin Enable 1 register (LLWU_PE1)..................................................................................................274
18.4.2 LLWU Pin Enable 2 register (LLWU_PE2)..................................................................................................275
18.4.3 LLWU Pin Enable 3 register (LLWU_PE3)..................................................................................................276
18.4.4 LLWU Pin Enable 4 register (LLWU_PE4)..................................................................................................277
18.4.5 LLWU Module Enable register (LLWU_ME).............................................................................................. 278
18.4.6 LLWU Flag 1 register (LLWU_F1)...............................................................................................................280
18.4.7 LLWU Flag 2 register (LLWU_F2)...............................................................................................................282
18.4.8 LLWU Flag 3 register (LLWU_F3)...............................................................................................................283
18.4.9 LLWU Pin Filter 1 register (LLWU_FILT1)................................................................................................ 285
18.4.10 LLWU Pin Filter 2 register (LLWU_FILT2)................................................................................................ 286
18.5 Functional description...................................................................................................................................................287
18.5.1 LLS mode.......................................................................................................................................................288
18.5.2 VLLS modes.................................................................................................................................................. 288
18.5.3 Initialization................................................................................................................................................... 288
Chapter 19
Peripheral Bridge (AIPS-Lite)
19.1 Chip-specific AIPS-Lite information............................................................................................................................289
19.1.1 Number of peripheral bridges........................................................................................................................ 289
19.1.2 Memory maps................................................................................................................................................ 289
19.2 Introduction...................................................................................................................................................................289
19.2.1 Features.......................................................................................................................................................... 289
19.2.2 General operation...........................................................................................................................................290
19.3 Memory map/register definition................................................................................................................................... 290
19.3.1 Master Privilege Register A (AIPS_MPRA)................................................................................................. 290
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19.3.2
Peripheral Access Control Register (AIPS_PACRn).....................................................................................292
19.3.3
Peripheral Access Control Register (AIPS_n)............................................................................................... 0
19.4 Functional description...................................................................................................................................................297
19.4.1 Access support............................................................................................................................................... 297
Chapter 20
Direct Memory Access Multiplexer (DMAMUX)
20.1 Chip-specific DMAMUX information......................................................................................................................... 299
20.1.1 DMA MUX Request Sources........................................................................................................................ 299
20.1.2 DMA transfers via PIT trigger.......................................................................................................................301
20.2 Introduction...................................................................................................................................................................301
20.2.1 Overview........................................................................................................................................................301
20.2.2 Features.......................................................................................................................................................... 302
20.2.3 Modes of operation........................................................................................................................................ 302
20.3 External signal description............................................................................................................................................303
20.4 Memory map/register definition................................................................................................................................... 303
20.4.1
Channel Configuration register (DMAMUXx_CHCFGn)............................................................................ 303
20.5 Functional description...................................................................................................................................................304
20.5.1 DMA channels with periodic triggering capability........................................................................................305
20.5.2 DMA channels with no triggering capability.................................................................................................307
20.5.3 Always-enabled DMA sources...................................................................................................................... 307
20.6 Initialization/application information........................................................................................................................... 309
20.6.1 Reset...............................................................................................................................................................309
20.6.2 Enabling and configuring sources..................................................................................................................309
Chapter 21
DMA Controller Module
21.1 Introduction...................................................................................................................................................................313
21.1.1 Overview........................................................................................................................................................313
21.1.2 Features.......................................................................................................................................................... 314
21.2 DMA Transfer Overview..............................................................................................................................................315
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21.3 Memory Map/Register Definition.................................................................................................................................316
21.3.1
Source Address Register (DMA_SARn)....................................................................................................... 317
21.3.2
Destination Address Register (DMA_DARn)............................................................................................... 318
21.3.3
DMA Status Register / Byte Count Register (DMA_DSR_BCRn)...............................................................319
21.3.4
DMA Control Register (DMA_DCRn)..........................................................................................................321
21.4 Functional Description..................................................................................................................................................325
21.4.1 Transfer requests (Cycle-Steal and Continuous modes)................................................................................325
21.4.2 Channel initialization and startup.................................................................................................................. 326
21.4.3 Dual-Address Data Transfer Mode................................................................................................................327
21.4.4 Advanced Data Transfer Controls: Auto-Alignment.....................................................................................328
21.4.5 Termination....................................................................................................................................................329
Chapter 22
Reset Control Module (RCM)
22.1 Introduction...................................................................................................................................................................331
22.2 Reset memory map and register descriptions............................................................................................................... 331
22.2.1 System Reset Status Register 0 (RCM_SRS0).............................................................................................. 332
22.2.2 System Reset Status Register 1 (RCM_SRS1).............................................................................................. 333
22.2.3 Reset Pin Filter Control register (RCM_RPFC)............................................................................................ 334
22.2.4 Reset Pin Filter Width register (RCM_RPFW)............................................................................................. 335
22.2.5 Force Mode Register (RCM_FM)..................................................................................................................337
22.2.6 Mode Register (RCM_MR)........................................................................................................................... 337
22.2.7 Sticky System Reset Status Register 0 (RCM_SSRS0).................................................................................338
22.2.8 Sticky System Reset Status Register 1 (RCM_SSRS1).................................................................................339
Chapter 23
Analog-to-Digital Converter (ADC)
23.1 Chip-specific ADC information....................................................................................................................................341
23.1.1 ADC instantiation information.......................................................................................................................341
23.1.2 DMA Support on ADC.................................................................................................................................. 341
23.1.3 ADC0 connections/channel assignment.........................................................................................................342
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23.1.4 ADC analog supply and reference connections............................................................................................. 343
23.1.5 Alternate clock............................................................................................................................................... 343
23.2 Introduction...................................................................................................................................................................344
23.2.1 Features.......................................................................................................................................................... 344
23.2.2 Block diagram................................................................................................................................................345
23.3 ADC signal descriptions............................................................................................................................................... 346
23.3.1 Analog Power (VDDA)................................................................................................................................. 346
23.3.2 Analog Ground (VSSA).................................................................................................................................346
23.3.3 Voltage Reference Select...............................................................................................................................346
23.3.4 Analog Channel Inputs (ADx)....................................................................................................................... 347
23.3.5 Differential Analog Channel Inputs (DADx).................................................................................................347
23.4 Memory map and register definitions...........................................................................................................................347
23.4.1
ADC Status and Control Registers 1 (ADCx_SC1n).....................................................................................349
23.4.2
ADC Configuration Register 1 (ADCx_CFG1).............................................................................................352
23.4.3
ADC Configuration Register 2 (ADCx_CFG2).............................................................................................353
23.4.4
ADC Data Result Register (ADCx_Rn).........................................................................................................354
23.4.5
Compare Value Registers (ADCx_CVn)....................................................................................................... 356
23.4.6
Status and Control Register 2 (ADCx_SC2)..................................................................................................357
23.4.7
Status and Control Register 3 (ADCx_SC3)..................................................................................................359
23.4.8
ADC Offset Correction Register (ADCx_OFS).............................................................................................360
23.4.9
ADC Plus-Side Gain Register (ADCx_PG)...................................................................................................361
23.4.10
ADC Minus-Side Gain Register (ADCx_MG).............................................................................................. 361
23.4.11
ADC Plus-Side General Calibration Value Register (ADCx_CLPD)........................................................... 362
23.4.12
ADC Plus-Side General Calibration Value Register (ADCx_CLPS)............................................................363
23.4.13
ADC Plus-Side General Calibration Value Register (ADCx_CLP4)............................................................ 363
23.4.14
ADC Plus-Side General Calibration Value Register (ADCx_CLP3)............................................................ 364
23.4.15
ADC Plus-Side General Calibration Value Register (ADCx_CLP2)............................................................ 364
23.4.16
ADC Plus-Side General Calibration Value Register (ADCx_CLP1)............................................................ 365
23.4.17
ADC Plus-Side General Calibration Value Register (ADCx_CLP0)............................................................ 365
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23.4.18
ADC Minus-Side General Calibration Value Register (ADCx_CLMD).......................................................366
23.4.19
ADC Minus-Side General Calibration Value Register (ADCx_CLMS)....................................................... 366
23.4.20
ADC Minus-Side General Calibration Value Register (ADCx_CLM4)....................................................... 367
23.4.21
ADC Minus-Side General Calibration Value Register (ADCx_CLM3)....................................................... 367
23.4.22
ADC Minus-Side General Calibration Value Register (ADCx_CLM2)....................................................... 368
23.4.23
ADC Minus-Side General Calibration Value Register (ADCx_CLM1)....................................................... 368
23.4.24
ADC Minus-Side General Calibration Value Register (ADCx_CLM0)....................................................... 369
23.5 Functional description...................................................................................................................................................369
23.5.1 Clock select and divide control......................................................................................................................370
23.5.2 Voltage reference selection............................................................................................................................371
23.5.3 Hardware trigger and channel selects............................................................................................................ 371
23.5.4 Conversion control.........................................................................................................................................372
23.5.5 Automatic compare function..........................................................................................................................380
23.5.6 Calibration function....................................................................................................................................... 381
23.5.7 User-defined offset function.......................................................................................................................... 383
23.5.8 Temperature sensor........................................................................................................................................384
23.5.9 MCU wait mode operation.............................................................................................................................385
23.5.10 MCU Normal Stop mode operation...............................................................................................................385
23.5.11 MCU Low-Power Stop mode operation........................................................................................................ 386
23.6 Initialization information.............................................................................................................................................. 387
23.6.1 ADC module initialization example.............................................................................................................. 387
23.7 Application information................................................................................................................................................389
23.7.1 External pins and routing............................................................................................................................... 389
23.7.2 Sources of error..............................................................................................................................................391
Chapter 24
Comparator (CMP)
24.1 Chip-specific CMP information....................................................................................................................................397
24.1.1 CMP instantiation information.......................................................................................................................397
24.1.2 CMP input connections..................................................................................................................................397
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24.1.3 CMP external references................................................................................................................................398
24.1.4 CMP trigger mode..........................................................................................................................................398
24.2 Introduction...................................................................................................................................................................399
24.2.1 CMP features..................................................................................................................................................399
24.2.2 6-bit DAC key features.................................................................................................................................. 400
24.2.3 ANMUX key features.................................................................................................................................... 400
24.2.4 CMP, DAC and ANMUX diagram................................................................................................................400
24.2.5 CMP block diagram....................................................................................................................................... 401
24.3 Memory map/register definitions..................................................................................................................................403
24.3.1
CMP Control Register 0 (CMPx_CR0)......................................................................................................... 403
24.3.2
CMP Control Register 1 (CMPx_CR1)......................................................................................................... 404
24.3.3
CMP Filter Period Register (CMPx_FPR).....................................................................................................405
24.3.4
CMP Status and Control Register (CMPx_SCR)...........................................................................................406
24.3.5
DAC Control Register (CMPx_DACCR)......................................................................................................407
24.3.6
MUX Control Register (CMPx_MUXCR).................................................................................................... 407
24.4 Functional description...................................................................................................................................................408
24.4.1 CMP functional modes...................................................................................................................................409
24.4.2 Power modes..................................................................................................................................................412
24.4.3 Startup and operation..................................................................................................................................... 413
24.4.4 Low-pass filter............................................................................................................................................... 414
24.5 CMP interrupts..............................................................................................................................................................416
24.6 DMA support................................................................................................................................................................ 416
24.7 CMP Asynchronous DMA support...............................................................................................................................416
24.8 Digital-to-analog converter...........................................................................................................................................417
24.9 DAC functional description.......................................................................................................................................... 417
24.9.1 Voltage reference source select......................................................................................................................417
24.10 DAC resets....................................................................................................................................................................418
24.11 DAC clocks...................................................................................................................................................................418
24.12 DAC interrupts..............................................................................................................................................................418
KL43 Sub-Family Reference Manual, Rev. 5.1, 07/2016
NXP Semiconductors 17
Section number Title Page
24.13 CMP Trigger Mode.......................................................................................................................................................418
Chapter 25
12-bit Digital-to-Analog Converter (DAC)
25.1 Introduction...................................................................................................................................................................419
25.2 Features.........................................................................................................................................................................419
25.3 Block diagram...............................................................................................................................................................419
25.4 Memory map/register definition................................................................................................................................... 420
25.4.1
DAC Data Low Register (DACx_DATnL)................................................................................................... 421
25.4.2
DAC Data High Register (DACx_DATnH).................................................................................................. 421
25.4.3
DAC Status Register (DACx_SR)................................................................................................................. 422
25.4.4
DAC Control Register (DACx_C0)............................................................................................................... 423
25.4.5
DAC Control Register 1 (DACx_C1)............................................................................................................ 424
25.4.6
DAC Control Register 2 (DACx_C2)............................................................................................................ 424
25.5 Functional description...................................................................................................................................................425
25.5.1 DAC data buffer operation.............................................................................................................................425
25.5.2 DMA operation.............................................................................................................................................. 427
25.5.3 Resets............................................................................................................................................................. 427
25.5.4 Low-Power mode operation...........................................................................................................................427
Chapter 26
Voltage Reference (VREFV1)
26.1 Introduction...................................................................................................................................................................429
26.1.1 Overview........................................................................................................................................................430
26.1.2 Features.......................................................................................................................................................... 430
26.1.3 Modes of Operation....................................................................................................................................... 430
26.1.4 VREF Signal Descriptions.............................................................................................................................431
26.2 Memory Map and Register Definition..........................................................................................................................431
26.2.1 VREF Trim Register (VREF_TRM)..............................................................................................................432
26.2.2 VREF Status and Control Register (VREF_SC)............................................................................................433
26.3 Functional Description..................................................................................................................................................434
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18 NXP Semiconductors
Section number Title Page
26.3.1 Voltage Reference Disabled, SC[VREFEN] = 0........................................................................................... 434
26.3.2 Voltage Reference Enabled, SC[VREFEN] = 1............................................................................................ 434
26.4 Internal voltage regulator..............................................................................................................................................436
26.5 Initialization/Application Information..........................................................................................................................436
Chapter 27
Multipurpose Clock Generator Lite (MCG_Lite)
27.1 Introduction ..................................................................................................................................................................439
27.1.1 Features ......................................................................................................................................................... 439
27.1.2 Block diagram ...............................................................................................................................................440
27.2 Memory map and register definition.............................................................................................................................440
27.2.1 MCG Control Register 1 (MCG_C1).............................................................................................................441
27.2.2 MCG Control Register 2 (MCG_C2).............................................................................................................442
27.2.3 MCG Status Register (MCG_S).................................................................................................................... 443
27.2.4 MCG Status and Control Register (MCG_SC)..............................................................................................443
27.2.5 MCG Miscellaneous Control Register (MCG_MC)......................................................................................444
27.3 Functional description...................................................................................................................................................445
27.3.1 Clock mode switching ...................................................................................................................................445
27.3.2 LIRC divider 1 .............................................................................................................................................. 446
27.3.3 LIRC divider 2 .............................................................................................................................................. 446
27.3.4 Enable LIRC in Stop mode ........................................................................................................................... 446
27.3.5 MCG-Lite in Low-power mode .................................................................................................................... 446
27.3.6 HIRC USB recovery ..................................................................................................................................... 447
Chapter 28
Oscillator (OSC)
28.1 Chip-specific OSC information.................................................................................................................................... 449
28.1.1 OSC modes of operation with MCG_Lite and RTC......................................................................................449
28.2 Introduction...................................................................................................................................................................449
28.3 Features and Modes...................................................................................................................................................... 449
28.4 Block Diagram..............................................................................................................................................................450
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NXP Semiconductors 19
Section number Title Page
28.5 OSC Signal Descriptions.............................................................................................................................................. 451
28.6 External Crystal / Resonator Connections.................................................................................................................... 451
28.7 External Clock Connections......................................................................................................................................... 453
28.8 Memory Map/Register Definitions...............................................................................................................................453
28.8.1 OSC Memory Map/Register Definition.........................................................................................................454
28.9 Functional Description..................................................................................................................................................455
28.9.1 OSC module states.........................................................................................................................................455
28.9.2 OSC module modes....................................................................................................................................... 457
28.9.3 Counter...........................................................................................................................................................459
28.9.4 Reference clock pin requirements..................................................................................................................459
28.10 Reset..............................................................................................................................................................................459
28.11 Low power modes operation.........................................................................................................................................460
28.12 Interrupts.......................................................................................................................................................................460
Chapter 29
Timer/PWM Module (TPM)
29.1 Chip-specific TPM information....................................................................................................................................461
29.1.1 TPM instantiation information.......................................................................................................................461
29.1.2 Clock options................................................................................................................................................. 462
29.1.3 Trigger options...............................................................................................................................................462
29.1.4 Global timebase..............................................................................................................................................463
29.1.5 TPM interrupts............................................................................................................................................... 463
29.2 Introduction...................................................................................................................................................................464
29.2.1 TPM Philosophy............................................................................................................................................ 464
29.2.2 Features.......................................................................................................................................................... 464
29.2.3 Modes of operation........................................................................................................................................ 465
29.2.4 Block diagram................................................................................................................................................465
29.3 TPM Signal Descriptions..............................................................................................................................................466
29.3.1 TPM_EXTCLK — TPM External Clock...................................................................................................... 466
29.3.2 TPM_CHn — TPM Channel (n) I/O Pin.......................................................................................................467
KL43 Sub-Family Reference Manual, Rev. 5.1, 07/2016
20 NXP Semiconductors
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