Broadcom BCM56990 Hardware Designlines User guide

Brand: Broadcom

Model: BCM56990 Hardware Designlines

Type: User guide

Broadcom 56990-DG102

January 28, 2020

BCM56990

Hardware Design Guidelines

Design Guide

Broadcom, the pulse logo, Connecting everything, Avago Technologies, Avago, the A logo, BroadSync, LinkEye, StrataDNX,

and StrataXGS are among the trademarks of Broadcom and/or its affiliates in the United States, certain other countries, and/

or the EU.

The term “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. For more information, please visit www.broadcom.com.

Broadcom reserves the right to make changes without further notice to any products or data herein to improve reliability,

function, or design. Information furnished by Broadcom is believed to be accurate and reliable. However, Broadcom does

not assume any liability arising out of the application or use of this information, nor the application or use of any product or

circuit described herein, neither does it convey any license under its patent rights nor the rights of others.

BCM56990 Design Guide Hardware Design Guidelines

Broadcom 56990-DG102

BCM56990 Design Guide Hardware Design Guidelines

Table of Contents

Chapter 1: Introduction ......................................................................................................................5

Chapter 2: High-Speed SerDes Cores .............................................................................................. 6

2.1 Blackhawk7 Core (Front-Panel Ports).....................................................................................................................7

2.1.1 Blackhawk7 PLL ...............................................................................................................................................8

2.1.2 Polarity Inversion ..............................................................................................................................................9

2.1.3 Lane Swapping .................................................................................................................................................9

2.1.4 Blackhawk7 Lane and Port Restrictions ...........................................................................................................9

2.1.5 Port Bandwidth Distribution...............................................................................................................................9

2.2 Merlin Core (Management Port).............................................................................................................................10

2.3 PCIe SerDes (CPU Interface)..................................................................................................................................10

2.3.1 PCIe Gen3-Specific Information .....................................................................................................................11

2.3.2 PCIe Routing and AC Coupling ......................................................................................................................11

2.3.3 Active State Power Management....................................................................................................................11

2.3.4 PCIe Reset......................................................................................................................................................11

Chapter 3: Clock Requirements ...................................................................................................... 12

3.1 Time Sync and BroadSync Reference Clock Information...................................................................................13

3.1.1 Mini OCXO Requirements ..............................................................................................................................14

3.1.2 OCXO Power Supply and Voltage ..................................................................................................................14

3.1.3 Mini OCXO PCB Layout Guidelines................................................................................................................15

3.1.4 Alternative Mini OCXO PCB Layout................................................................................................................16

3.1.5 OCXO Temperature Sensitivity.......................................................................................................................16

3.1.6 Environmental Protection Cover .....................................................................................................................17

Chapter 4: Power Supply Filtering Information .............................................................................18

4.1 Analog Filter Requirements...................................................................................................................................19

Chapter 5: Power Supply Information ............................................................................................20

5.1 Power-up Sequence................................................................................................................................................20

5.2 Power-down Requirements....................................................................................................................................21

5.3 Power Distribution Network Requirements..........................................................................................................21

5.4 Failsafe Requirements............................................................................................................................................22

5.5 Adaptive Voltage Scaling.......................................................................................................................................22

Chapter 6: Socket and Heatsink Information .................................................................................24

Chapter 7: PCB Layout Guidelines ................................................................................................. 25

7.1 50G PCB Layout Guidelines...................................................................................................................................25

7.2 25G PCB Layout Guidelines...................................................................................................................................25

7.3 10G PCB Layout Guidelines...................................................................................................................................27

7.4 PCIe PCB Layout Guidelines .................................................................................................................................28

Broadcom 56990-DG102

BCM56990 Design Guide Hardware Design Guidelines

7.5 Escaping the Pad Field...........................................................................................................................................28

7.6 High-Speed Clock Layout Guidelines ...................................................................................................................28

7.7 Impedance-Matched Symmetrical Via Structure..................................................................................................29

Chapter 8: Guidelines for Unused Pins ..........................................................................................30

8.1 Unused Blackhawk7 and Merlin Core Pins...........................................................................................................31

Chapter 9: Blackhawk7 Modeling and Simulations ....................................................................... 32

9.1 Blackhawk7 IBIS-AMI Model ..................................................................................................................................32

9.1.1 PAM4 ..............................................................................................................................................................32

Chapter 10: Debug and Bring-up Recommendations ...................................................................33

Related Documents .......................................................................................................................... 34

Revision History ...............................................................................................................................35

56990-DG102; January 28, 2020................................................................................................................................... 35

56990-DG101; November 1, 2019................................................................................................................................. 35

56990-DG100; July 29, 2019 ......................................................................................................................................... 35

Broadcom 56990-DG102

BCM56990 Design Guide Hardware Design Guidelines

Chapter 1: Introduction

This document describes the hardware design guidelines for the BCM56990 family of devices. It describes the requirements

for the high-speed external I/O interface used on these devices, provides a diagram of how each high-speed interface must

be connected, and describes routing examples when applicable.

For a complete and detailed functional description of each interface within the devices, refer to the latest BCM56990 data

sheet (56990-DS1xx).

NOTE: This is the advance version of the hardware design guidelines for the BCM56990 family of devices. The content (for

example, pad names) is subject to change.

Broadcom 56990-DG102

BCM56990 Design Guide Hardware Design Guidelines

Chapter 2: High-Speed SerDes Cores

The BCM56990 device family incorporates three different SerDes cores:

 Blackhawk7 (BH) SerDes core (front-panel ports)

 Merlin SerDes core (management ports)

 PCIe SerDes core (CPU interface)

The Blackhawk7 core supports PAM4 modes up to 56G and NRZ modes up to 26G (in a single lane). There are 64 instances

of the Blackhawk7 core that are divided equally among 16 data pipelines (4 Blackhawk7 cores per data pipeline). These

Blackhawk7 cores are used for front-panel ports.

There is a single instance of the Merlin core that supports up to two management ports.

Figure 1: Blackhawk7 SerDes Core Block Diagram

The Blackhawk7 interfaces require controlled impedance trace routing. The device has an on-chip termination on its receiver

inputs, eliminating the need for external resistors in typical applications.

The Blackhawk7 and Merlin cores also have on-die AC capacitors in the receive path. Consequently, external AC-coupling

capacitors are not required in most cases. This on-die AC-coupling cannot be bypassed.

External capacitors may also be required in the receiver path (Blackhawk7 and Merlin7 cores). For inputs with a higher Vcm

voltage than the maximum (0.7V), an external AC capacitor is still needed, and it should be 100 nF. If an external capacitor

is required, use a 100-nF capacitor with a 0201 footprint to minimize reflections.

AC coupling is required in the transmit path from the Blackhawk7 or Merlin core to the link-partner receiver. This is achieved

through an external capacitor on the PCB or an on-chip capacitor in the remote receiver.

quad -2

quad-0 quad-3

ITM0

ITM1

pipe-7

quad-1

BH(28-31)

pipe-6

BH(24-27)

pipe-5

BH(20-23)

pipe-4

BH(16-19)

LPBK

pipe-8

BH(32-35)

pipe-9

BH(36-39)

pipe-10

BH(40-43)

pipe-11

BH(44-47)

MGMT

LPBK

pipe-3

BH(12-15)

LPBK

pipe-2

BH(8-11)

MGMT

pipe-1

BH(4-7)

LPBK

pipe-0

BH(0-3)

CPU

pipe-12

BH(48-51)

pipe-13

BH(52-55)

LPBK

pipe-14

BH(56-59)

pipe-15

BH(60-63)

LPBK

Broadcom 56990-DG102

BCM56990 Design Guide Hardware Design Guidelines

NOTE:

 Refer to the BCM56990 data sheet for a complete list of supported speeds and any restrictions regarding

Blackhawk7 and Merlin core configurations.

 Half-duplex operation is not supported at any speed.

 If there are any discrepancies between this document and the latest data sheet, the data sheet information

takes precedence.

2.1 Blackhawk7 Core (Front-Panel Ports)

The following figure illustrates the SerDes block in the device. It is comprised of eight SerDes lanes and the supporting digital

logic.

Figure 2: SerDes Block Diagram

The Blackhawk7 core supports 1-lane, 2-lane, 4-lane, and 8-lane modes of operation. Refer to the data sheet for a complete

list of supported port speeds. For convenience, some example port speed modes are shown in the following table.

Refer to the data sheet for any port or speed restrictions. If there is a conflict, the data sheet information takes precedence.

Table 1: Speed Mode Examples

Interface Number of Lanes Mode Lane Baud Rate VCO Frequency

10G-SFI 1 NRZ 10.3125G 20.6250G (OSx2)

25G-KR, CR 1 NRZ 25.78125G 25.78125G

50G-KR2, CR2 2 NRZ 25.78125G 25.78125G

50G with RS-544 FEC 1 PAM4 53.125G 26.5625G

40G-KR4, CR4 4 NRZ 10.3125G 20.6250G (OSx2)

100G-KR4, CR4 4 NRZ 25.78125G 25.78125G

200G with RS-544 FEC 4 PAM4 53.125G 26.5625G

400G with RS-544 FEC 8 PAM4 53.125G 26.5625G

SerDes 8-lane

PMD

PLL

Auto-

Negotiation

FEC

PRBS

Equalization

PCS

MAC

Interface

Line Interface

Broadcom 56990-DG102

BCM56990 Design Guide Hardware Design Guidelines

A typical connection diagram is shown in the following figure. This is applicable for 1-lane, 2-lane, 4-lane, and 8-lane modes.

In most cases, a direct connection can be made without the need for any external components.

Figure 3: Typical Blackhawk Connection Diagram

2.1.1 Blackhawk7 PLL

The Blackhawk7 SerDes cores have a single PLL to support up to four ports.

Some limitations may occur if a port speed cannot be derived from the single PLL frequency. The following table shows some

PAM4 modes and their frequency requirement. For example, a 50G PAM4 port with RS-544 FEC requires a frequency of

26.5625G, but another 50G PAM4 port with RS-528 FEC requires a frequency of 25.78125G. These two ports could not

coexist in the same Blackhawk7 core at the same time. Refer to the latest BCM56990 data sheet for a complete list of

supported speeds and frequency requirements.

Table 2: PAM4 Mode Frequency Requirement

Interface Number of Lanes Mode VCO Frequency

50G with FEC (RS-544) 1 PAM4 26.5625G

50G with FEC (RS-528) 1 PAM4 25.78125G

100G with FEC (RS-544) 2 PAM4 26.5625G

100G with FEC (RS-528) 2 PAM4 25.78125G

200G with FEC (RS-544) 4 PAM4 26.5625G

200G with FEC (NONE) 4 PAM4 25.78125G

BCM56990

Lane‐0

Lane‐1

Channel

Lane‐7

Broadcom 56990-DG102

BCM56990 Design Guide Hardware Design Guidelines

2.1.2 Polarity Inversion

The Blackhawk7 and Merlin cores support Tx and Rx polarity inversion. The polarity of the P and N taps of each pair can be

individually inverted. The configuration is software controlled through dedicated registers or bits on an individual-pair basis.

2.1.3 Lane Swapping

The Blackhawk7 and Merlin cores support lane-swap capabilities. This feature is typically needed to ease the layout

requirements.

The lane-swap capability is restricted to Rx lanes in the receive path and Tx lanes in the transmit path. Lane swapping across

Tx and Rx lanes is not supported (that is, a Rx lane cannot be swapped with a Tx lane).

Lane swapping affects PMD loopback modes in the following ways.

 PMD remote loopback is not supported with lane swaps.

 PMD local loopback is supported with lane swaps; however, all of the lane-swap configurations must be removed for

the port-under test before putting it into loopback mode. When the PMD loopback test is complete, the lane-swap

configuration must be reapplied for normal operation. This affects all ports within a Blackhawk7 core.

2.1.4 Blackhawk7 Lane and Port Restrictions

 Ports must be aligned to the Blackhawk7 core boundaries. This means that a single port cannot span multiple

Blackhawk7 cores. A 4-lane port (that is, 40G-CR4) cannot have two lanes in Blackhawk7 core 0 and two lanes in

Blackhawk7 core 1.

 Up to four ports are supported in a single Blackhawk7 core.

2.1.5 Port Bandwidth Distribution

To optimize switch performance, distribute the port usage and bandwidth evenly across the 16 data pipelines and the two

ingress traffic managers (ITM0 and ITM1). For additional information, refer to the MMU and Port Numbering sections in the

Theory of Operations (56990-PG1xx).

Broadcom 56990-DG102

BCM56990 Design Guide Hardware Design Guidelines

2.2 Merlin Core (Management Port)

The following figure illustrates the Merlin SerDes block in the device. It is composed of single quad SerDes PMD blocks (four

lanes) and the supporting digital logic.

Figure 4: Merlin SerDes Core Block Diagram

Up to two management ports are supported in the device by this quad-core SerDes module. The management ports have

limited capability. Refer to the data sheet for a complete list of supported port speeds and any lane restrictions that may exist.

2.3 PCIe SerDes (CPU Interface)

The BCM56990 is a x4 PCIe Gen3-capable device. The PCIe interface provided by the switch conforms to the PCIe

version 3.0 specification. The device supports up to four lanes of PCIe (8 Gb/s in each direction).

A 2-lane (x2) PCIe interface is supported using lanes 0 and 1 and a 1-lane (x1) interface is supported using lane 0. The

protocols and electrical requirements of the PCIe specifications are strictly implemented. The PCIe interface consists of a

serial point-to-point interface that propagates data through differential pairs.

Figure 5: PCIe Interface Connection

Series AC-coupling capacitors are required in the data path. The PCIe specification (version 3.1) recommends capacitor

values in the range of 176 nF to 265 nF, with 220 nF as the typical value. The PCIe specification (version 2.0) recommends

typical capacitor values in the range of 75 nF to 200 nF. All PCIe differential pairs must be routed as a closely coupled pair

with a differential impedance of 100Ω. The AC-coupling capacitors should be placed as close to the transmitter buffer as

practical. This ensures that the DC bias levels of the transmitted signal do not adversely affect the receiver.

On-chip 100Ω differential termination resistors are provided, and external termination resistors are not required. Minimize

the number of vias in the trace path. Vias must always match in number on each differential pair and be co-located whenever

possible.

SerDes Lane-0

PMD

SerDes Lane-1

PMD

SerDes Lane-2

PMD

SerDes Lane-3

PMD

PCS

Auto-Negotiation

FEC

Equalization

PRBS

MAC Interface

Line Interface

BCM56900

Channel

Host

Broadcom 56990-DG102

BCM56990 Design Guide Hardware Design Guidelines

2.3.1 PCIe Gen3-Specific Information

PCIe Gen3 supports speeds of 8 Gb/s, so follow the routing guidelines for 10 Gb/s. See Section 7.3, 10G PCB Layout

Guidelines.

PCIe Gen3 requires microcode to be loaded into the PCIe SerDes during initialization. This is achieved by using mHost0 to

fetch the microcode from an EEPROM and push it into the PCIe SerDes.

The QSPI flash memory is connected to the QSPI interface and must be strapped such that the device downloads from this

memory. The firmware configures the PCIe interface into a functionally compliant Gen3 mode. The Gen3 strap settings are

as follows:

 BOOT_DEV[2:0] = 3’b000

 MHOST0_BOOT_DEV = 1’b1

 PCIe_FORCE_GENTYPE[1:0] = 2’b00

 QSPI flash memory is programmed with Broadcom-provided firmware

 QSPI flash memory is connected to the IPROC_QSPI interface

All designs should include an EEPROM device connected using the IPROC_QSPI interface for PCIe Gen1, Gen2, and Gen3

operation.

2.3.2 PCIe Routing and AC Coupling

The PCI Express Base Specification Revision 1.0a, Section 4.3.1.2, dictates that AC coupling be placed as close to the

transmitter buffer as practical. This ensures that the DC bias levels of the transmitted signal do not adversely affect the

receiver.

2.3.3 Active State Power Management

Disable Active State Power Management (ASPM) for normal operation.

2.3.4 PCIe Reset

The device supports the following three reset modes per PCIe standards:

 Cold reset: Apply the fundamental reset mechanism by toggling the PERST# signal following the application of power to

the component.

 Warm reset: Apply the fundamental reset mechanism by toggling the PERST# signal without the removal and

application of power to the component. The timing requirements must be similar to that of cold reset, except that there

are no changes in power events.

 Hot reset: An inband mechanism where a reset is propagated across the link by software. The inband mechanism

forces a link into the electrical idle state and goes through a hot reset.

When the switch device operates as an End Point (EP), the Root Complex (RC/CPU) issues either a warm reset or hot reset.

Regardless of any reset mode, it is a requirement to connect the PERST# signal directly from the switch to the CPU.

NOTE: Although the PCIe standards do not require toggling the PERST# signal during hot reset, it is a Broadcom

requirement to support the hot-swap requirements. Failure to toggle PERST# will not reset the PCIe core within

the switch.

All power-up and reset sequences must adhere to the timing diagram specified in the data sheet. Refer to the data sheet for

timing on VDD, SYS_RST, PERST#, PCIe_CLOCK, and CORE_CLK.

Broadcom 56990-DG102

BCM56990 Design Guide Hardware Design Guidelines

Chapter 3: Clock Requirements

Several clock and PLL sources are required by the BCM56990. Refer to the BCM56990 data sheet for the clock input

electrical requirements.

Table 3: Reference Clock Summary

Clock Name Clock Requirement Description

CORE_PLL_FREF Input Type = Differential

Frequency = 50 MHz

Provides clock signal for the digital core.

AC Coupling: Needs external 0.01-μF capacitors.

Termination: On-chip 100Ω differential.

BS_PLL[1:0]_FREF Input Type = Differential

Frequency = 50 MHz

BroadSync

reference clock input.

AC Coupling: Needs external 0.01-μF capacitors.

Termination: On-chip 100Ω differential.

TS_PLL_FREF Input Type = Differential

Frequency = 50 MHz

Time Sync reference clock input.

AC Coupling: Needs external 0.01-μF capacitors.

Termination: On-chip 100Ω differential.

IPROC_PLL_FREF Input Type = Differential

Frequency = 50MHz

IPROC reference clock.

AC Coupling: Needs external 0.01-μF capacitors

Termination: On-chip 100Ω differential

TSC_MGMT_REFLCLK Input Type = Differential

Frequency = 156.25 MHz

SerDes reference clock input for management ports using Merlin core.

AC Coupling: Needs external 0.01-μF capacitors.

Termination: On-chip 100Ω differential.

TSC_REFCLK Input Type = Differential

Frequency = 156.25 MHz

SerDes reference clock input for front-panel ports using Blackhawk core.

AC Coupling: Needs external 0.01-μF capacitors.

Termination: On-chip 100Ω differential.

PCIe_REFCLK Input Type = Differential

Frequency = 100 MHz

PCIe SerDes reference clock input.

AC-Coupling: Requires an external 10-nF AC-coupling capacitor on the board.

Termination: External 100Ω differential required.

Broadcom 56990-DG102

BCM56990 Design Guide Hardware Design Guidelines

A typical reference clock connection diagram is shown in the following figure.

Figure 6: CORE_PLL_FREF Connection

For example components of the oscillators and clock buffers for any of the reference clocks, refer to the schematic file for

the SVK.

NOTE: The Blackhawk7 and TSC-Merlin differential reference clocks are critical high-speed signals with fast rise and fall

times. Good PCB layout practices are required for these signals, including the use of back-drilling vias to minimize

reflections due to via stubs.

3.1 Time Sync and BroadSync Reference Clock Information

The following figure shows clock input circuit examples for the time sync (TS) and BroadSync (BS) reference clocks. These

reference clocks have an internal termination and require external series AC-coupling capacitors (0.01 μF) on the board.

Because they have internal DC biasing, they do not require external biasing resistors.

For unused TS_PLL_REFCLK and BS_PLL_REFCLK inputs, each leg of the differential pair can be connected to GND

through a 0.01-μF capacitor.

Figure 7: TS_PLL and BS_PLL Reference Clock Connection

ENA

VDD

SEL

IN+

CORE_PLL_FREF_P

50 MHz

0.01 uF

CORE_PLL_FREF_N

clock_buffer

IN-

TS_PLL_REFCLK_P

TS_PLL_REFCLK_N

BS_PLL_REFCLK_P

BS_PLL_REFCLK_N

TCXO/OCXO

Broadcom 56990-DG102

BCM56990 Design Guide Hardware Design Guidelines

3.1.1 Mini OCXO Requirements

Use either the Rakon M5860LF (12.8-MHz DIL Mercury mini OCXO) or the Rakon STP2920LF (12.8-MHz 25 mm × 22 mm

OCXO) as sources for TS_PLL_REFCLK and BS_PLL_REFCLK. The M5860LF and STP2920LF have been tested by

Broadcom in the IEEE 1588 clock-recovery application.

The output behavior of the OCXO can be altered by external conditions such as temperature variation, reference voltage,

or electrical noise. The following recommendations minimize the external influences as much as possible, given that there

are other devices and signals that can create disturbances.

NOTE: The propagation delay of the buffers for frame sync and 4-kHz outputs must be less than 1 ns.

3.1.2 OCXO Power Supply and Voltage

The power supply rail for the OCXO must be isolated from the power rails of all other devices. The recommended circuit is

shown in the following figure.

When a 3.3V supply is shared with other devices, filtering is critical to minimize noise and load variation.

Use a dedicated step-down linear supply using a 5V-to-12V input supply, rather than inductor isolation from an existing 3.3V

supply rail. Use good RF design practices when designing the circuit board, and place the OCXO close to the destination

clock input to minimize noise injection across the long trace length.

The OCXO can have an initial voltage anywhere within the typical operating voltage range of ±5% of the 3.3V supply.

However, deviation from the initial voltage level during normal operation will adversely affect the stability of the output

frequency. For example, the M5860LF and the STP2920LF both specify an operating voltage range of 3.3V ± 5%. If the

operating voltage changes by ±2%, then the output frequency will typically change by ±10 ppb.

Figure 8: Recommended Isolation Circuit

Shield1

C33

0. 1 µF

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dedicatedtotheminiOCXO .

EFCDAC

Broadcom 56990-DG102

BCM56990 Design Guide Hardware Design Guidelines

3.1.3 Mini OCXO PCB Layout Guidelines

Placement of the OCXO device must be as far away as possible from noise sources. For example, avoid placement near

fans, clock runs, other power supply rails, and devices that emit high temperatures.

The layout example in the following figure illustrates how the OCXO must be isolated from the surrounding circuits.

Figure 9: OCXO Component Placement on PCB

Broadcom 56990-DG102

BCM56990 Design Guide Hardware Design Guidelines

3.1.4 Alternative Mini OCXO PCB Layout

An alternative layout can be used to isolate the OCXO from the balance of the circuits. The OCXO must be separated from

all noise sources. A ground moat (on all layers) must be created around the OCXO. In addition, void the ground connection

only on the layer where the clock output path exists. No signal, power, or ground must go over the moat area on any layer.

The following figure illustrates this approach.

Figure 10: Alternative PCB Layout

3.1.5 OCXO Temperature Sensitivity

Temperature variation is a major factor that can impact the output frequency of the OCXO, resulting in phase and frequency

variations (wander). Generally, the OCXO must be placed where minimal temperature variation is anticipated. Place the

OCXO in one of the following locations:

 Away from air vents and fans.

 Where airflow is low.

 In a location where the OCXO is fitted with an environmental cover to help isolate it from external influences (see

Section 3.1.6, Environmental Protection Cover).

NOTE: Ensure the internal temperature of the cover does not exceed the maximum operating temperature of the OCXO.

OCXO

Groundmoat

aroundthedevice

throughalllayers

Output

GND

Grou nd plane

Power

Output

Broadcom 56990-DG102

BCM56990 Design Guide Hardware Design Guidelines

3.1.6 Environmental Protection Cover

To shield the OCXO from potential thermal variations and changes to airflow, use a metal cover to enclose the device. The

cover must be connected to the ground plane to avoid any electrical charge buildup.

A mechanical drawing of a recommended cover is shown in the following figure.

Figure 11: Recommended Environmental Protection Cover

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anysubsequentamendments .

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hand ling.

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Broadcom 56990-DG102

BCM56990 Design Guide Hardware Design Guidelines

Chapter 4: Power Supply Filtering Information

Individual bypass or decoupling capacitors are recommended on each VDD pin whenever possible. These capacitors must

be placed as close to the power pins as is practical. This is achieved by using 0402 placed in the pad field of the device.

Filter circuits are required for analog supplies. These filter circuits are used to attenuate noise on the power supply at

frequencies where analog circuits are most sensitive. The power supply requirements are listed in the following table.

The overall noise ripple must not exceed the values listed in the table. The filter must have adequate noise suppression such

that a frequency from 50 kHz to 20 MHz meets the maximum allowable noise swing as described in the table. The DCR of

the ferrite should be selected to minimize the voltage drop associated with the filter circuit. The voltage drop due to any filter

components must be considered such that the voltage specification (as measured at the device pins) is not exceeded. This

implies that the power supply provided by the system must be rated better than the tolerance specified in the data sheet to

compensate for the voltage drop across any filter circuit. The current rating of the ferrite bead should be at least two times

the expected current for the supply.

Table 4: Power Supply Filtering Information

Pin Name Typical Voltage Comments

Digital Core Power

VDDC Refer to the data sheet. Digital core voltage. Adjust this voltage based on the AVS output status. A filter is

not required.

Analog Power

TRVDD0P75 0.75V Blackhawk core transmitter/receiver voltage.

Noise < 10 mVp-p.

TVDDH 1.2V Blackhawk core transmitter voltage. A power supply filter circuit is required.

Noise < 10 mVp-p.

TSC_PLLVDD0 0.75V Blackhawk core PLL voltage. Power supply filter circuit is required.

Noise < 3 mVp-p.

TSC_MGMT_RTVDD 0.75V TSC (management) core transmitter/receiver voltage. Power supply filter circuit is

required.

Noise < 10 mVp-p.

TSC_MGMT_PVDD 0.75V TSC (management) core PLL voltage. Power supply filter circuit is required.

Noise < 3 mVp-p,.

PCIe_RTVDD 0.75V PCIe transmitter/receiver voltage. Power supply filter circuit is required.

Noise < 10 mVp-p.

PCIe_PVDD 0.75V PCIe PLL voltage. Power supply filter circuit is required.

Noise < 3 mVp-p.

CORE_PLL_AVDD1P8 1.8V Core PLL voltage. Power supply filter circuit is required.

Noise < 30 mVp-p.

BS[1:0]_PLL_AVDD1P8 1.8V BroadSync PLL voltage. Power supply filter circuit is required.

Noise < 30 mVp-p.

TS_PLL_AVDD1P8 1.8V Time Sync PLL voltage. Power supply filter circuit is required.

Noise < 30 mVp-p.

IPROC_PLL_AVDD1P8 1.8V iProc PLL voltage. Power supply filter circuit is required.

Noise < 30 mVp-p.

VTMON*_AVDD1P8 1.8V VT Monitor PLL voltage. Power supply filter circuit is required.

Noise < 30 mVp-p.

Broadcom 56990-DG102

BCM56990 Design Guide Hardware Design Guidelines

For the Blackhawk pad pattern, where the TRVDD and TVDD1P2 are located between the differential signals, use the

following suggestions to control the crosstalk resonance.

 The TRVDD decoupling capacitor should be 0402 or 0201 type and should be soldered on the bottom side of the

TRVDD and TVDD1P2 LGA via.

 The TRVDD and TVDD1P2 plane should be on the lower layers.

4.1 Analog Filter Requirements

For the Blackhawk7 SerDes core, the PLL power supply filtering recommendation is to have at most eight PLLs sharing one

filter. There is one PLL per Blackhawk core. With 64 Blackhawk instances in the device, there will be a total of eight PLL

filters.

The inductance (L) measured from the ferrite-bead (FB) filter side to the PVDD pad must be < 100 pH. The decoupling

capacitor (C2) should be 1 μF (0402) with low equivalent series inductance (ESL) and low equivalent series resistance

(ESR).

Figure 12: Analog Filter Requirements

The frequency response of the Blackhawk PVDD filter should have a (–3 dB) cut-off frequency < 10 kHz. The frequency

response of the Blackhawk TRVDD filter should have a (–3 dB) cut-off frequency < 100 kHz.

Refer to the SVK schematics for examples of filtering components.

BCM56990

PVDD

L < 100 pH

C1 C2

Broadcom 56990-DG102

BCM56990 Design Guide Hardware Design Guidelines

Chapter 5: Power Supply Information

This section contains the following additional information related to the supply design requirements for the device:

 Power sequencing requirements

 Failsafe requirements

 Adaptive Voltage Scaling (AVS)

 Chip power module

5.1 Power-up Sequence

The device has both power-up and power-down sequencing requirements. Consult the latest version of the BCM56990 data

sheet (56990-DS1xx) for information on these requirements.

To meet the power sequencing requirements, it is mandatory that each of the different supply rails is sourced from an

independent supply. Each supply must be capable of being independently sequenced. An example is shown in the following

figure.

NOTE: It is a design requirement that the 1.2V I/O supply is separate from the 1.2V analog supply to meet the power

sequencing requirements. The same requirement is also true of the 1.8V I/O and 1.8V analog supplies.

Figure 13: Power Sequencing System Design

Refer to the latest BCM56990 data sheet for power-up sequence requirements.

BCM56990

1.8V Supply

RUN

Power

Sequencing

Logic

Core Supply

RUN

0.75V Supply

RUN

1.2V Supply

RUN

1.2V Supply

RUN

1.8V Supply

RUN

Filter

Networks

Filter

Networks

Filter

Networks

Analog 0.75V

Domain

Core Voltage

Domain

1.2V I/O

Domain

Analog 1.2V

Domain

1.8V I/O

Domain

Analog 1.8V

Domain

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Broadcom BCM56990 Hardware Designlines User guide

Broadcom BCM56990 Hardware Designlines User guide

Broadcom BCM56990 Hardware Designlines User guide

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