Broadcom NetXtreme/NetLink BCM5718 Series User guide

Type
User guide
5718-PG108-R
5300 California Avenue Irvine, CA 92617 Phone: 949-926-5000 Fax: 949-926-5203 January 29, 2016
Programmer’s Guide
BCM5718
NetXtreme
®
/NetLink
®
BCM5718 Family
Programmer’s Guide
Broadcom Corporation
5300 California Avenue
Irvine, CA 92617
© 2016 by Broadcom Corporation
All rights reserved
Printed in the U.S.A.
Broadcom
®
, the pulse logo, Connecting everything
®
, the Connecting everything logo, NetLink
®
,
NetXtreme II
®
, NetXtreme
®
, and NetXtreme
®
I are among the trademarks of Broadcom Corporation and/or its
affiliates in the United States, certain other countries and/or the EU. Any other trademarks or trade names
mentioned are the property of their respective owners.
Revision History
Revision Date Change Description
5718-PG-108-R 01/29/16 Updated:
“Other Considerations Relating to Producer Ring Setup” on page 90
“RCB Setup Pseudo Code” on page 91
“Summary of Register Settings to Support Jumbo Frames” on page 129
“Receive MTU Size Register (offset: 0x43C)” on page 316
“BM Hardware Diagnostic 2 Register (offset: 0x4450)” on page 431
5718-PG-107-R 07/17/13 Updated:
“Send Rings” on page 106
“Initialization Procedure” on page 140
Table 49: “GPIO Usage for Power Management for Broadcom Drivers,”
on page 192
Table 101: “Multiple Send Ring Mail Boxes,” on page 357
“Send BD Ring Host Producer Index Register (offset: 0x5900)” on
page 465
“Send BD Ring NIC Producer Index Register (offset: 0x5980)” on
page 466
Table 121: “GbE Port Internal PHY Register Map,” on page 553
Table 127: “AUTONEG LINK PARTNER ABILITY,” on page 559
Added:
Table 124: “02h: PHY_Identifier_MSB_Register,” on page 558
Table 125: “03h: PHY_Identifier_LSB_Register,” on page 558
Revision HistoryBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 5718-PG108-R Page 3
5718-PG-106-R 06/25/12 Updated:
“Base Address Register 1 (offset: 0x10)” on page 275
“Base Address Register 2 (offset: 0x14)” on page 275
“Base Address Register 3 (offset: 0x18)” on page 275
“Base Address Register 4 (offset: 0x1c)” on page 276
“Mode Control Register (offset: 0x6800)” on page 475
Added:
Section 8: “IEEE1588,” on page 152
“RX TIME STAMP LSB REG [Offset 0X06B0]” on page 163
“RX TIME STAMP MSB REG [Offset 0x06B4]” on page 163
“RX PTP SEQUENCE ID REG [Offset 0X06B8]” on page 163
“RX LOCK TIMER LSB REG [Offset 0x06C0]” on page 164
“RX LOCK TIMER MSB REG [Offset 0x06C4]” on page 164
“RX PTP CONTROL REG [Offset 0X06C8]” on page 164
Section 12: “IO Virtualization (IOV),” on page 264
“Perfect Match Destination Address Registers” on page 465
“VRQ Filter Set Registers” on page 461
“VRQ Mapper Registers” on page 462
“Base Address Register 5 (offset: 0x20)” on page 276
“Base Address Register 6 (offset: 0x24)” on page 277
Revision Date Change Description
Revision HistoryBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 5718-PG108-R Page 4
5718-PG-105-R 02/24/12 Updated:
Table 3: “Family Revision Levels,” on page 48
Table 5: “Flag Fields for a Ring,” on page 70
Figure 24: “Ring Control Block,” on page 118
“Summary of Register Settings to Support Jumbo Frames” on page 126
“Initialization Procedure” on page 136
“Reading a PHY Register” on page 186
“Writing a PHY Register” on page 187
“Subsystem ID/Vendor ID Register (offset: 0x2C)” on page 251
“DMA Read/Write Control Register (Offset: 0x6c)” on page 258
“PCI State Register (offset: 0x70)” on page 259
“Receive BD Standard Producer Ring Index Register (offset: 0x268-
0x26f)” on page 281
“Transmit MAC Status Register (offset: 0x460)” on page 296
“Receive MAC Mode Register (offset: 0x468)” on page 297
“Statistics Registers” on page 319
“H2B Statistics Registers” on page 320
“Receive Data and Receive BD Initiator Mode Register (offset: 0x2400)”
on page 341
“Link Speed 10 MB/No Link Power Mode Clock Policy Register (offset:
0x3604)” on page 356
“Link Speed 100 MB Power Mode Clock Policy Register (offset: 0x3608)
on page 357
“Link Aware Power Mode Clock Policy Register (offset: 0x3610)” on
page 359
“D0u Clock Policy Register (offset: 0x3614)” on page 360
“Link Idle Power Mode Clock Policy Register (offset: 0x3618)” on
page 360
“APE CLK Policy Register (offset: 0x361C)” on page 361
“APE Sleep State Clock Policy Register (offset: 0x3620)” on page 363
“Clock Speed Override Policy Register (offset: 0x3624)” on page 364
“Clock Status Register (offset: 0x3630)” on page 367
“Padring Control Register (offset: 0x3668)” on page 376
“Receive Coalescing Ticks Register (offset: 0x3C08)” on page 393
“Send Coalescing Ticks Register (offset: 0x3C0C)” on page 394
“Receive Max Coalesced BD Count Register (offset: 0x3C10)” on
page 395
“Send Max Coalesced BD Count Register (offset: 0x3C14)” on page 397
“Status Block Host Address Register (offset: 0x3C38)” on page 400
Revision Date Change Description
Revision HistoryBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 5718-PG108-R Page 5
“Status Block Base Address Register (offset: 0x3C44)” on page 426
“BM Hardware Diagnostic 2 Register (offset: 0x4450)” on page 436
“LSO Read DMA Mode Register (offset: 0x4800)” on page 438
“LSO Read DMA Reserved Control Register (offset: 0x4900)” on
page 445
“LSO Read DMA Flow Reserved Control Register (offset: 0x4904)” on
page 446
“LSO/Non-LSO/BD Read DMA Corruption Enable Control Register
(offset: 0x4910)” on page 446
“BD Read DMA Mode Register (Offset: 0x4A00)” on page 449
“BD READ DMA Reserved Control Register (offset: 0x4A70)” on
page 456
“BD READ DMA Flow Reserved Control Register (offset: 0x4A74)” on
page 457
“BD READ DMA Corruption Enable Control Register (offset: 0x4A78)” on
page 457
“Non_LSO Read DMA Mode Register (offset: 0x4B00)” on page 458
“Non-LSO Read DMA Reserved Control Register (offset: 0x4B74)” on
page 461
“Non-LSO Read DMA Corruption Enable Control Register (offset:
0X4B7C)” on page 462
“Write DMA Mode Register (offset: 0x4C00)” on page 464
“Low Priority Mailboxes” on page 469
“Interrupt Mailbox 0 Register (offset: 0x5800)” on page 469
“Other Interrupt Mailbox Register (offset: 0x5808–0x5818)” on page 469
“General Mailbox Registers 1-8 (offset: 0x5820–0x5824)” on page 469
“Receive BD Standard Producer Ring Index Register (offset: 0x5868)” on
page 470
“Receive BD Return Ring 0 Consumer Index Register (offset: 0x5880-
0x5887)” on page 470
“Receive BD Return Ring 0 Consumer Index Register (offset: 0x5880-
0x5887)” on page 470
“Send BD Ring Consumer Index Register (offset: 0x5900)” on page 471
“NVM Write Register (offset: 0x7008)” on page 497
“NVM Address Register (offset: 0x700C)” on page 497
“NVM Read Register (offset: 0x7010)” on page 498
“NVM Config 1 Register (offset: 0x7014)” on page 498
“NVM Access Register (offset: 0x7024)” on page 502
“00h: MII_Control_Register” on page 513
“03h: PHY_Identifier_LSB_Register” on page 515
“04h: Auto_Negot_Advertisement_Register” on page 515
“09h: 1000Base_T_Control_Register” on page 518
“10h: PHY_Extended_Control_Register” on page 522
“18h: Auxiliary Control Register (Shadow Register Selector = “000”)” on
page 526
Revision Date Change Description
Revision HistoryBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 5718-PG108-R Page 6
“18h: Miscellaneous Control Register (Shadow Register Selector =
“111”)” on page 533
“1Ch: Cabletron LED Register (Shadow Register Selector = “00h”)” on
page 538
“1Ch: Spare Control 4 Register (Shadow Register Selector = “0bh”)” on
page 547
“1Ch: External SerDes Control Register (Shadow Register Selector =
“14h”)” on page 557
“1Ch: SGMII Slave Register (Shadow Register Selector = “15h”)” on
page 559
“1Ch: Misc 1000-X Control 2 Register (Shadow Register Selector =
“16h”)” on page 561
“1Ch: Misc 1000-X Control Register (Shadow Register Selector = “17h”)”
on page 563
“1Ch: Auto-Detect SGMII/GBIC Register (Shadow Register Selector =
“18h”)” on page 564
“1Ch: Auto-Detect Medium Register (Shadow Register Selector = “1eh”)”
on page 572
“1Ch: Mode Control Register (Shadow Register Selector = “1fh”)” on
page 573
Added:
Table 1: “Register Access Methods,” on page 46
“Device Reset Procedure” on page 146
“PHY Loopback Configuration” on page 205
“PHY Configuration Auto-Negotiation (10/100/1000 Speed with Half and
Full Duplex Support)” on page 206
“MSI-X Capabilities Registers” on page 281
“PCIe Capabilities Registers” on page 282
“VRQ Flush Control Register (Offset: 0x2410)” on page 369
“VRQ Flush Timer Register (offset: 0x2414)” on page 370
“RDI B2HRX Hardware Debugging Register (offset: 0x2418)” on
page 370
“Receive BD Ring Initiator Local NIC Standard Receive BD Consumer
Index (offset: 0x2474)” on page 373
“B2HRX Byte-count Statistics Count (offset: 0x24D0)” on page 374
“B2HRX Unicast Statistics Count (offset: 0x24D4)” on page 374
“B2HRX Multicast Statistics Count (offset: 0x24D8)” on page 374
“B2HRX Broadcast Statistics Count (offset: 0x24DC))” on page 374
“B2HRX Drop Packet Count (offset: 0x24E0)” on page 374
“B2HRX Drop Packet Byte Count (offset: 0x24E4)” on page 374
“B2HRX APE Byte-count Statistics Count (offset: 0x24E8)” on page 375
“B2HRX APE Unicast Statistics Count (offset: 0x24EC)” on page 375
“B2HRX APE Multicast Statistics Count (offset: 0x24F0)” on page 375
“B2HRX APE Broadcast Statistics Count (offset: 0x24F4)” on page 375
“B2HRX APE Drop Packet Count (offset: 0x24F8)” on page 375
“B2HRX APE Drop Packet Byte Count (offset: 0x24FC)” on page 375
Revision Date Change Description
Revision HistoryBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 5718-PG108-R Page 7
“Receive Max Coalesced BD Count During Interrupt Register (offset:
0x3C18)” on page 424
“Send Max Coalesced BD Count During Interrupt Register (offset:
0x3C1C)” on page 425
“NIC Mini Receive BD Consumer Index (offset: 0x3c58)” on page 428
“Send BD Ring Producer Index Register (offset: 0x5980)” on page 471
“DMA Completion Mode Register (Offset: 0x6400)” on page 477
Figure 58: “Copper PHY Register Mapping Table,” on page 511
Figure 59: “SerDes PHY Register Map,” on page 512
“Clause 45 Registers” on page 601
“SerDes PHY Register Definitions” on page 578
“PHY 0x18 Shadow 0x1 register read Procedure” on page 527
Added PHY 0x1C Shadow 0x1 register read Procedure information to
“1Ch: Cabletron LED Register (Shadow Register Selector = “00h”)” on
page 538
Added Clause 45 register Dev3 Reg803Eh read Procedure to “Clause 45
Register Dev 3 Reg14h (20d): EEE Capability Register” on page 601
NIC Ring Addresses information to Memory map tables in
Appendix C: “Device Register and Memory Map,” on page 611
Deleted
Section 11: Host to/from BMC Pass Through
Appendix D: Appendix
Top Level MII Registers
5718-PG104-R 06/29/11 Updated:
Table 27: “Flag Field Description,” on page 113
Table 31: “Send Buffer Descriptor Flags,” on page 123
“Clock Control” on page 191
Table 47: “Ethernet Controller Power Pins,” on page 191
“Internal Memory” on page 214
“ISR Flow” on page 230
Table 82: “Interrupt-Related Registers,” on page 235
“Status Register (offset: 0x362C)” on page 391
“Clock Status Register (offset: 0x3630)” on page 393
“LSO Read DMA Mode Register (offset: 0x4800)” on page 438
“NVM Write Register (offset: 0x7008)” on page 497
Added:
Device Closing Procedure” on page 147
“TX TIME STAMP LSB REG (offset: 0x5C0)” on page 327
“TX TIME STAMP MSB REG (offset: 0x5C4)” on page 327
Revision Date Change Description
Revision HistoryBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 5718-PG108-R Page 8
5718-PG103-R 01/26/11 Updated:
Added BCM5720 to Section 1: “Introduction,” on page 49.
Added BCM5720 to “Introduction” on page 49.
Added Host to BMC to “Transmit MAC Mode Register (offset: 0x45C)” on
page 317.
Added Host to BMC to “Transmit MAC Lengths Register (offset: 0x464)”
on page 319.
Added Host to BMC to “Mode Control Register (offset: 0x6800)” on
page 477.
Added
“HTX2B Perfect Match[14] HI Reg (offset: 0x4880, 0x4888, 0x4890,
0x4898)” on page 330.
“HTX2B Perfect Match[14] LO Reg (offset: 0x4884, 0x488C, 0x4894,
0x489C)” on page 330.
“HTX2B Protocol Filter Reg (offset: 0x6D0)” on page 331.
“HTX2B Global Filter Reg (address: 0x6D4)” on page 333.
“H2B Statistics Registers” on page 346.
“HTX2B Statistics” on page 347
“B2HRX Statistics” on page 347
“RMU Registers” on page 504
“RMU_EGRESS_DA1_MATCH[1-8]_REG (offsets: 0x00B0, 0x00B8,
0x00C0, 0x00C8 … 0xE8)” on page 504
“RMU_EGRESS_DA2_MATCH[1-8]_REG (Offsets 0x00B4, 0x00BC,
0x00C4, 0xCC …0xEC)” on page 504
“RMU_EGRESS_STATUS_REG (Offset 0x0000)” on page 504
Revision Date Change Description
Revision HistoryBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 5718-PG108-R Page 9
5718-PG102-R 12/16/10 Updated:
Added BCM5719 to “Introduction” on page 39.
Added BCM5719 to “Related Documents” on page 39.
Added BCM5719 to Table 1: “BCM5718 Family Product Features,” on
page 40.
Removed PHY core column and added BCM5717 B0, BCM5718 BO,
and BCM5719 to Table 2: “Family Revision Levels,” on page 42.
Updated note in “Revision Levels” on page 42.
Added Memory Arbiter to Figure 1: “Individual Port Functional Block
Diagram,” on page 45.
Added BCM5719 to “Overview of Features” on page 46.
Added note about BCM5719 to Figure 2: “High-Level System Functional
Block Diagram,” on page 47.
Added max ring sizes to “Ring Control Block” on page 99.
Added BCM5719 toTable 6: “Defined Flags for Send Buffer Descriptors,”
on page 67.
Updated Host Ring Size to Table 7: “Receive Return Rings,” on page 70.
Corrected typo in Figure 26: “Send Driver Interface,” on page 119.
Corrected typo in Figure 27: “Receive Producer Interface,” on page 120.
Corrected typo in Figure 28: “Receive Return Interface,” on page 121.
Updated Step 36 in “Initialization Procedure” on page 137.
Added BCM5719 to “Description” on page 168.
Corrected typo in “PCI Classcode and Revision ID Register (offset:
0x08)Function 0” on page 255
Corrected typos in “Power Management Control/Status Register (offset:
0x4C) Function 0” on page 261
Added note to Enable Endian Byte Swap in “Miscellaneous Host Control
Register (offset: 0x68)” on page 264.
Updated all Indirection Table register descriptions in “RSS Registers” on
page 276.
Added BCM5717 and BCM5718 values to “CPMU Control Register
(offset: 0x3600)” on page 346.
Added BCM5719 to “Link Aware Power Mode Clock Policy Register
(offset: 0x3610)” on page 349.
Added BCM5719 to “APE CLK Policy Register (offset: 0x361C)” on
page 352.
Revision Date Change Description
Revision HistoryBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 5718-PG108-R Page 10
Updated (continued):
Added BCM5718 to “Clock Speed Override Policy Register (offset:
0x3624) for BCM5718” on page 354
Added BCM5718 to “Clock Status Register (offset: 0x3630)” on
page 358
Added Reserved for BCM5719 to “PCIE Status Register (offset:
0x3634)” on page 359
Added BCM5719 to “GPHY Control/Status Register (offset: 0x3638)” on
page 360
Updated introduction to “PCIE Idle Detection De-Bounce Control
Register (offset: 0x364C)” on page 362
Corrected typo and added BCM5719 to “DLL Lock Timer Register (offset:
0x3654)” on page 364
Updated Chip ID default value in “CHIP ID Register (offset: 0x3658)” on
page 365
Added BCM5719 to “Padring Control Register (offset: 0x3668)” on
page 367
Added BCM5719 to “Reserved (offset: 0x366C)” on page 368
Added BCM5719 to “Reserved (offset: 0x367C)” on page 373
Added BCM5719 to “Read DMA Mode Register (offset: 0x4800)” on
page 398
“LSO Read DMA Corruption Enable Control Register (offset: 0x4910)” on
page 413
Added BCM5719 to “Write DMA Mode Register (offset: 0x4C00)” on
page 443
Added BCM5719 to “MSI Mode Register (offset: 0x6000)” on page 454
Added:
“Receive BD Standard Producer Ring Index (High Priority Mailbox)
Register (offset: 0x268-0x26f)” on page 276
“TX Time Stamp LSB Reg (offset: 0x5C0)” on page 282
“TX Time Stamp MSB Reg (offset: 0x5C4)” on page 283
“RX Time Stamp LSB Reg (offset 0x06B0)” on page 308
“RX Time Stamp MSB Reg (offset 0x06B4)” on page 308
“RX PTP Sequence ID Reg (offset 0x06B8)” on page 308
“RX Lock Timer LSB Reg (offset 0x6C0)” on page 309
“RX Lock Timer MSB Reg (offset 0x06C4)” on page 309
“RX PTP Control Reg (offset: 0x6C8)” on page 310
“Clock Speed Override Policy Register (offset: 0x3624)” on page 355
“Clock Status Register (offset: 0x3630)” on page 358
“Global Mutex Request Register (offset: 0x36F0)” on page 381
“Global Mutex Grant Register (offset: 0x36F4)” on page 381
“Temperature Monitor Control Register (offset: 0x36FC)” on page 382
“BCM5719 Registers” on page 469
Removed:
“Reserved (offset: 0x378C)”
Revision Date Change Description
Revision HistoryBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 5718-PG108-R Page 11
5718-PG101-R 11/12/10 Updated:
Table 1: “BCM5718 Family Product Features,” on page 40
IP cksum description in “Receive Buffer Descriptors” on page 70
“Extended RX Buffer Descriptor (BD)” on page 110
Table title for Table 34: “Jumbo Producer Ring Host Address Low
Register (offset: 0x2444),” on page 123
Default value and description in Table 36: “Jumbo Producer Ring NIC
Address Register (offset: 0x244C),” on page 123
NIC ring address values in Table 45: “NIC Ring Addresses,” on page 126
PCI version in “Description” on page 148
“EMAC Status Register (offset: 0x404)” on page 279
“DMA Flag Register for TCP Segmentation (offset: 0xCEC)” on page 321
“Jumbo Producer Ring NIC Address Register (offset: 0x244C)” on
page 337
“Receive Producer Length/Flags Register (offset: 0x2458)” on page 337
“Receive Producer Ring NIC Address Register (offset: 0x245C)” on
page 338
“GPHY Strap Register (offset: 0x3664)” on page 366
“Read DMA Mode Register (offset: 0x4800)” on page 398
“BCM5718 Family MII Bus PHY Addressing” on page 496
Added:
Section 8: “Device Control,” on page 137
Registers 0x00 to 0x3c and 0x48 to 0x64 to “PCI Configuration
Registers” on page 254
Section 14: “Transceiver Registers,” on page 496
Removed:
References to BCM5724 throughout
Column from Table 1: “BCM5718 Family Product Features,” on page 40
Register control mode from “MDI Register Access” on page 187
MDI Control Register (offset: 0x6844)
5718-PG100-R 04/13/10 Initial release
Revision Date Change Description
Table of ContentsBCM5718 Programmer’s Guide
Broadcom
®
January 29, 2016 5718-PG108-R Page 12
Table of Contents
About This Document................................................................................................................................44
Purpose and Audience.......................................................................................................................... 44
Acronyms and Abbreviations................................................................................................................. 44
Document Conventions ......................................................................................................................... 44
References............................................................................................................................................ 45
Technical Support...................................................................................................................................... 46
Section 1: Introduction .....................................................................................................47
Product Features........................................................................................................................................ 47
Revision Levels .......................................................................................................................................... 49
Programming the Ethernet Controllers.................................................................................................... 50
Section 2: Hardware Architecture....................................................................................51
Theory of Operation................................................................................................................................... 51
Overview of Features................................................................................................................................. 52
Receive Data Path ...................................................................................................................................... 54
RX Engine ............................................................................................................................................. 54
RX FIFO ................................................................................................................................................ 54
Rules Checker....................................................................................................................................... 55
RX List Initiator ...................................................................................................................................... 55
Transmit Data Path..................................................................................................................................... 56
TX MAC................................................................................................................................................. 56
TX FIFO................................................................................................................................................. 56
DMA Read.................................................................................................................................................... 57
Read Engine.......................................................................................................................................... 57
Read FIFO............................................................................................................................................. 57
Buffer Manager...................................................................................................................................... 58
DMA Write ................................................................................................................................................... 58
Write Engine.......................................................................................................................................... 58
Write FIFO............................................................................................................................................. 58
Buffer Manager...................................................................................................................................... 59
LED Control................................................................................................................................................. 59
Memory Arbiter........................................................................................................................................... 59
Host Coalescing ......................................................................................................................................... 60
Host Coalescing Engine........................................................................................................................ 60
MSI FIFO............................................................................................................................................... 61
Status Block .......................................................................................................................................... 61
10BT/100BTx/1000BASE-T Transceiver ................................................................................................... 62
Table of ContentsBCM5718 Programmer’s Guide
Broadcom
®
January 29, 2016 5718-PG108-R Page 13
Auto-Negotiation.................................................................................................................................... 62
Automatic MDI Crossover ..................................................................................................................... 62
PHY Control................................................................................................................................................ 62
MII Block................................................................................................................................................ 62
GMII Block............................................................................................................................................. 64
MDIO Register Interface........................................................................................................................ 66
Management Data Clock................................................................................................................ 66
Management Data Input/Output..................................................................................................... 66
Management Data Interrupt ........................................................................................................... 66
Management Register Block .......................................................................................................... 66
Section 3: NVRAM Configuration.....................................................................................67
Overview...................................................................................................................................................... 67
Self-Boot...................................................................................................................................................... 68
Section 4: Common Data Structures...............................................................................69
Theory of Operation................................................................................................................................... 69
Descriptor Rings......................................................................................................................................... 69
Producer and Consumer Indices........................................................................................................... 70
Ring Control Blocks............................................................................................................................... 71
Send Ring Control Blocks .............................................................................................................. 71
Receive Ring Control Blocks.......................................................................................................... 72
Send Rings............................................................................................................................................ 73
Send Buffer Descriptors................................................................................................................. 75
Standard (Not Large Segment Offload) ................................................................................. 75
Large Segment Offload (LSO) Send BD................................................................................ 76
Receive Rings ....................................................................................................................................... 77
Receive Producer Ring .................................................................................................................. 77
Receive Return Rings .................................................................................................................... 78
Receive Buffer Descriptors ............................................................................................................ 78
Additional Ring Information for the BCM5718 Family .................................................................... 81
Status Block................................................................................................................................................ 82
Status Block Format.............................................................................................................................. 82
INTx/MSI Legacy Mode Status Block Format ............................................................................ 83
Single-Vector or INTx RSS Mode Status Block Format ............................................................. 84
Multivector RSS Mode Status Block Format .................................................................................. 85
Status Block and INT MailBox Addresses...................................................................................... 86
Section 5: Receive Data Flow...........................................................................................88
Introduction................................................................................................................................................. 88
Receive Producer Ring.............................................................................................................................. 90
Table of ContentsBCM5718 Programmer’s Guide
Broadcom
®
January 29, 2016 5718-PG108-R Page 14
Setup of Producer Rings Using RCBs................................................................................................... 90
Receive Producer Ring RCB—Register Offset 0x2450–0x245f .................................................... 90
Other Considerations Relating to Producer Ring Setup......................................................... 90
RCB Setup Pseudo Code .............................................................................................................. 91
Receive Buffer Descriptors.................................................................................................................... 91
Management of Rx Producer Rings with Mailbox Registers and Status Block ..................................... 92
Status Block ................................................................................................................................... 92
Mailbox........................................................................................................................................... 92
Receive BD Producer Ring Producer Index........................................................................... 92
Receive Return Rings ................................................................................................................................93
Management of Return Rings with Mailbox Registers and Status Block .............................................. 94
Host Buffer Allocation............................................................................................................................ 94
Receive Rules Setup and Frame Classification ....................................................................................95
Receive Rules Configuration Register ........................................................................................... 95
Receive List Placement Rules Array..............................................................................................96
Class of Service Example .............................................................................................................. 97
Checksum Calculation............................................................................................................................... 98
VLAN Tag Strip........................................................................................................................................... 98
RX Data Flow Diagram............................................................................................................................. 100
Receive Side Scaling................................................................................................................................101
Overview ............................................................................................................................................. 101
Functional Description......................................................................................................................... 101
RSS Parameters ................................................................................................................................. 102
Hash Function .............................................................................................................................. 102
Hash Type.................................................................................................................................... 102
Hash Mask ................................................................................................................................... 102
Indirection Table........................................................................................................................... 103
Secret Hash Key .......................................................................................................................... 103
RSS Initialization ................................................................................................................................. 103
RSS Rx Packet Flow ........................................................................................................................... 104
Section 6: Transmit Data Flow.......................................................................................105
Introduction............................................................................................................................................... 105
Send Rings................................................................................................................................................ 105
Ring Control Block............................................................................................................................... 107
Host-Based Send Ring........................................................................................................................ 108
Checksum Offload.................................................................................................................................... 109
Large Segment Offload............................................................................................................................ 110
QuickStart............................................................................................................................................ 110
LSO-Related Hardware Control Bits ................................................................................................... 111
Table of ContentsBCM5718 Programmer’s Guide
Broadcom
®
January 29, 2016 5718-PG108-R Page 15
Send Buffer Descriptor........................................................................................................................ 112
Host Address................................................................................................................................ 112
Length[15:0] ................................................................................................................................. 112
VLAN Tag[15:0]............................................................................................................................ 112
HdrLen[7:0] .................................................................................................................................. 112
MSS[13:0] .................................................................................................................................... 113
Flags ............................................................................................................................................ 113
LSO Limitations ................................................................................................................................... 114
Additional LSO Notes .......................................................................................................................... 114
Example TCP-segmentation-related (LSO) register values ......................................................... 115
Jumbo Frames.......................................................................................................................................... 116
Affected Data Structures ..................................................................................................................... 117
Extended RX Buffer Descriptor (BD)............................................................................................ 117
Receive Jumbo Producer Ring .................................................................................................... 120
Ring Control Blocks...................................................................................................................... 121
Receive Return Ring(s)................................................................................................................ 122
Send Buffer Descriptor................................................................................................................. 122
Status Block ................................................................................................................................. 124
Misc BD Memory.......................................................................................................................... 125
Device Driver Interface........................................................................................................................ 125
Send Interface.............................................................................................................................. 125
Receive Interface ......................................................................................................................... 126
Large Segment Offload (LSO/TSO) ............................................................................................. 128
Summary of Register Settings to Support Jumbo Frames .................................................................. 129
Scatter/Gather........................................................................................................................................... 130
VLAN Tag Insertion.................................................................................................................................. 131
TX Data Flow Diagram.............................................................................................................................. 131
Reset.......................................................................................................................................................... 134
MAC Address Setup/Configuration........................................................................................................ 135
Packet Filtering......................................................................................................................................... 135
Multicast Hash Table Setup/Configuration .......................................................................................... 135
Ethernet CRC Calculation ................................................................................................................... 136
Generating CRC.................................................................................................................................. 136
Checking CRC..................................................................................................................................... 136
Initializing the MAC Hash Registers .................................................................................................... 136
Promiscuous Mode Setup/Configuration............................................................................................. 138
Broadcast Setup/Configuration ........................................................................................................... 138
Section 7: Device Control...............................................................................................139
Initialization Procedure............................................................................................................................ 139
Table of ContentsBCM5718 Programmer’s Guide
Broadcom
®
January 29, 2016 5718-PG108-R Page 16
Device Reset Procedure .......................................................................................................................... 146
Device Closing Procedure....................................................................................................................... 147
Energy Efficient Ethernet
...................................................................................................................... 148
Section 8: IEEE1588........................................................................................................152
IEEE1588 Time Sync Introduction .......................................................................................................... 152
NetXtreme Time Sync Assist................................................................................................................... 152
Coexistence......................................................................................................................................... 152
PTP Link Delay Measurement............................................................................................................. 153
PTP Time Synchronization Messaging ............................................................................................... 153
Hardware Description .............................................................................................................................. 154
EAV Reference Clock/Counter............................................................................................................ 155
EAV Reference Corrector ........................................................................................................................ 156
Time Watchdogs ................................................................................................................................. 156
Divided EAV Reference Clock Output................................................................................................. 156
Transmit Time Stamping Service............................................................................................................ 157
Receive Time Stamp and Sequence ID Registers................................................................................. 158
Time Sync Registers................................................................................................................................160
GRC MODE REG [0x6800] ................................................................................................................. 160
EAV REF COUNT CAPTURE LSB REG [Offset 0x6900] ................................................................... 160
EAV REF COUNT CAPTURE MSB REG [Offset 0x6904] .................................................................. 160
EAV REF CLOCK CONTROL REG [Offset 0x6908]........................................................................... 161
EAV REF-COUNT SNAP-SHOT LSB[0] REG [Offset 0X6910] .......................................................... 162
EAV REF-COUNT SNAP-SHOT MSB[0] REG [Offset 0X6914] ......................................................... 162
EAV REF CORRECTOR REG [Offset 0x6928]................................................................................... 162
TX TIME STAMP LSB REG [Offset 0x05C0] ...................................................................................... 162
TX TIME STAMP MSB REG [Offset 0X05C4]..................................................................................... 163
RX TIME STAMP LSB REG [Offset 0X06B0] ..................................................................................... 163
RX TIME STAMP MSB REG [Offset 0x06B4] ..................................................................................... 163
RX PTP SEQUENCE ID REG [Offset 0X06B8] .................................................................................. 163
RX LOCK TIMER LSB REG [Offset 0x06C0]...................................................................................... 164
RX LOCK TIMER MSB REG [Offset 0x06C4]..................................................................................... 164
RX PTP CONTROL REG [Offset 0X06C8] ......................................................................................... 164
TX TIME WATCHDOG LSB[0] REG [Offset 0x6918].......................................................................... 165
TX TIME WATCHDOG MSB[0] REG [Offset 0x691C] ........................................................................ 165
TX TIME WATCHDOG LSB[1] REG [Offset 0x6920].......................................................................... 166
TX TIME WATCHDOG MSB[1] REG [Offset 0x6924]......................................................................... 166
EAV REF-COUNT SNAP-SHOT LSB[1] REG [Offset 0X6930] .......................................................... 166
EAV REF-COUNT SNAP-SHOT MSB[1] REG [Offset 0X6934] ......................................................... 167
Table of ContentsBCM5718 Programmer’s Guide
Broadcom
®
January 29, 2016 5718-PG108-R Page 17
Section 9: PCI ..................................................................................................................168
Configuration Space ................................................................................................................................168
Description .......................................................................................................................................... 168
Functional Overview............................................................................................................................ 171
PCI Configuration Space Registers ............................................................................................. 171
PCI Required Header Region ......................................................................................................171
Indirect Mode ............................................................................................................................... 172
Indirect Register Access .............................................................................................................. 173
Indirect Memory Access............................................................................................................... 175
UNDI Mailbox Access .................................................................................................................. 177
Standard Mode............................................................................................................................. 179
Memory Mapped I/O Registers ........................................................................................................... 184
PCI Command Register ............................................................................................................... 184
PCI State Register ....................................................................................................................... 184
PCI Base Address Register ......................................................................................................... 184
Bus Interface............................................................................................................................................. 186
Description .......................................................................................................................................... 186
Operational Characteristics ................................................................................................................. 187
Read/Write DMA Engines ............................................................................................................ 187
Expansion ROM........................................................................................................................................ 187
Description .......................................................................................................................................... 187
Operational Characteristics ................................................................................................................. 187
BIOS.................................................................................................................................................... 187
Preboot Execution Environment...................................................................................................188
Power Management.................................................................................................................................. 188
Description .......................................................................................................................................... 188
Operational Characteristics ................................................................................................................. 189
Device State D0 (Uninitialized) .................................................................................................... 189
Device State D0 (Active) .............................................................................................................. 190
Device State D3 (Hot) .................................................................................................................. 190
Device State D3 (Cold) ................................................................................................................ 190
Wake on LAN ...................................................................................................................................... 190
GPIO ................................................................................................................................................... 191
Power Supply in D3 State ................................................................................................................... 191
Clock Control....................................................................................................................................... 191
Device ACPI Transitions ..................................................................................................................... 192
Disable Device Through BIOS ............................................................................................................ 192
Endian Control (Byte and Word Swapping)........................................................................................... 193
Background ......................................................................................................................................... 193
Table of ContentsBCM5718 Programmer’s Guide
Broadcom
®
January 29, 2016 5718-PG108-R Page 18
Architecture ......................................................................................................................................... 194
Enable Endian Word Swap and Enable Endian Byte Swap Bits......................................................... 194
Word Swap Data and Byte Swap Data Bits ........................................................................................ 197
Word Swap Data = 0, and Byte Swap Data = 0 ........................................................................... 197
Word Swap Data = 0, and Byte Swap Data = 1 ........................................................................... 198
Word Swap Data = 1, and Byte Swap Data = 0 ........................................................................... 198
Word Swap Data = 1, and Byte Swap Data = 1 ........................................................................... 199
Word Swap Non-Frame Data and Byte Swap Non-Frame Data Bits .................................................. 200
Word Swap Non-Frame Data = 0 and Byte Swap Non-Frame Data = 0...................................... 201
Word Swap Non-Frame Data = 1 and Byte Swap Non-Frame Data = 0...................................... 201
Word Swap Non-Frame Data = 0 and Byte Swap Non-Frame Data = 1...................................... 201
Word Swap Non-Frame Data = 1 and Byte Swap Non-Frame Data = 1...................................... 202
Section 10: Ethernet Link Configuration.......................................................................203
Overview.................................................................................................................................................... 203
GMII/MII...................................................................................................................................................... 203
Configuring the Ethernet Controller for GMII and MII Modes .............................................................. 203
Link Status Change Indications........................................................................................................... 204
Configuring the GMII/MII PHY............................................................................................................. 204
Reading a PHY Register .............................................................................................................. 204
Writing a PHY Register ................................................................................................................ 204
PHY Loopback Configuration....................................................................................................... 205
External PHY Loopback....................................................................................................... 205
Internal PHY Loopback ........................................................................................................ 205
PHY Configuration Auto-Negotiation (10/100/1000 Speed with Half and Full Duplex Support) .. 206
MDI Register Access................................................................................................................................210
Operational Characteristics ................................................................................................................. 210
Access Method.................................................................................................................................... 211
Auto-Access Method .................................................................................................................... 211
Wake on LAN Mode/Low-Power.............................................................................................................. 212
Description .......................................................................................................................................... 212
Functional Overview............................................................................................................................ 213
Operational Characteristics ................................................................................................................. 214
Internal Memory ........................................................................................................................... 214
WOL Pattern Configuration Register............................................................................................ 214
WOL Streams............................................................................................................................... 215
Pattern Data Structure ................................................................................................................. 217
Firmware Mailbox......................................................................................................................... 218
PHY Auto-Negotiation .................................................................................................................. 219
Power Management ..................................................................................................................... 219
Table of ContentsBCM5718 Programmer’s Guide
Broadcom
®
January 29, 2016 5718-PG108-R Page 19
Integrated MACs .......................................................................................................................... 220
WOL Data Flow Diagram .................................................................................................................... 221
Flow Control.............................................................................................................................................. 223
Description .......................................................................................................................................... 223
Operational Characteristics ................................................................................................................. 223
Transmit MAC .............................................................................................................................. 223
Receive MAC ............................................................................................................................... 224
Statistics Block ............................................................................................................................. 225
PHY Auto-Negotiation .................................................................................................................. 226
Integrated MACs .......................................................................................................................... 226
Flow Control Initialization Pseudocode ............................................................................................... 227
Section 11: Interrupt Processing ...................................................................................229
NetXtreme Legacy Interrupt Model......................................................................................................... 229
ISR Flow.............................................................................................................................................. 230
Legacy Status TAGGING Mode................................................................................................... 231
Basic Driver Interrupt Processing Flow................................................................................................. 232
Flowchart for Servicing an Interrupt .................................................................................................... 232
Interrupt Procedure ............................................................................................................................. 233
Host Coalescing ....................................................................................................................................... 234
Description .......................................................................................................................................... 234
Operational Characteristics ................................................................................................................. 234
Registers ............................................................................................................................................. 235
MSI............................................................................................................................................................. 236
Traditional Interrupt Scheme ............................................................................................................... 236
Message Signaled Interrupt ................................................................................................................ 237
PCI Configuration Registers................................................................................................................ 238
MSI Address................................................................................................................................. 238
MSI Data ...................................................................................................................................... 238
Host Coalescing Engine...................................................................................................................... 239
Firmware ............................................................................................................................................. 239
MSI-X.......................................................................................................................................................... 240
MSI-X Plumbing........................................................................................................................................ 244
Replication of Status Blocks and INT Mailboxes................................................................................. 244
Single-Vector RSS Mode Status Block Format............................................................................ 246
Single-Vector IOV Mode Status Block Format ............................................................................. 247
Multivector RSS Mode Status Block Format ................................................................................ 248
Multivector IOV Mode Status Block Format ................................................................................. 249
MSI-X Capability Structure .................................................................................................................. 250
MSI-X Data Structures ........................................................................................................................ 251
Table of ContentsBCM5718 Programmer’s Guide
Broadcom
®
January 29, 2016 5718-PG108-R Page 20
MSI-X Cognizant Host Coalescing ...................................................................................................... 253
Legacy Host Coalescing Parameters........................................................................................... 253
Receive Coalescing Ticks Register (Offset: 0x3c08)........................................................... 253
Send Coalescing Ticks Register (Offset: 0x3c0c)................................................................ 254
Receive Max Coalesced Bd Count Register (Offset: 0x3c10) ............................................. 254
Send Max Coalesced BD Count Register (Offset: 0x3c14) ................................................. 254
Receive Max Coalesced BD Count During Interrupt Register (Offset 0x3c18).................... 255
Send Max Coalesced BD Count During Interrupt Register (Offset 0x3c1c)......................... 255
BCM5718 Family Host Coalescing Parameter Sets .................................................................... 255
MSI-X One Shot Mode ................................................................................................................. 258
Coalesce Now or Forced Update ................................................................................................. 258
Misc Coalescing Controls............................................................................................................. 258
Broadcom Tagged Status Mode (0x68[9]) ........................................................................... 258
Clear Interrupt, Mask Interrupt, Mask Mode (0x68[0], 0x68[1], 0x68[8]).............................. 259
Clear Ticks On Rx Bd Events Mode (0x3c00[9]).................................................................. 259
No Interrupt On Force Update (0x3c00[11])......................................................................... 259
No Interrupt On DMAD Force (0x3c00[12]).......................................................................... 259
Do Not Interrupt On Receives (0x6800[14])......................................................................... 259
End of Receive Stream Interrupt.................................................................................................. 260
Host Coalescing Mode Register (Offset 0x3c00)................................................................. 260
End Stream Debounce Register (Offset 0x3cd4)................................................................. 260
Other Configuration Controls.................................................................................................................. 262
Broadcom Mask Mode ........................................................................................................................ 262
Broadcom Tagged Status Mode.......................................................................................................... 262
Clear Ticks on BD Events Mode ......................................................................................................... 262
No Interrupt on Force Update.............................................................................................................. 262
No Interrupt on DMAD Force............................................................................................................... 262
Section 12: IO Virtualization (IOV) .................................................................................263
Data Structure and Register Changes for IOV....................................................................................... 264
Mail Box Register Changes................................................................................................................. 264
Receive Mail Box Register Changes................................................................................................... 264
Send Mail Box Register Changes ....................................................................................................... 264
Ring Control Block Changes ............................................................................................................... 264
VRQ Statistics ..................................................................................................................................... 264
MSI-X Vectors Changes...................................................................................................................... 265
Register Changes................................................................................................................................ 265
IOV – Receive Side................................................................................................................................... 266
IOV – Transmit Side.................................................................................................................................. 267
  • Page 1 1
  • Page 2 2
  • Page 3 3
  • Page 4 4
  • Page 5 5
  • Page 6 6
  • Page 7 7
  • Page 8 8
  • Page 9 9
  • Page 10 10
  • Page 11 11
  • Page 12 12
  • Page 13 13
  • Page 14 14
  • Page 15 15
  • Page 16 16
  • Page 17 17
  • Page 18 18
  • Page 19 19
  • Page 20 20
  • Page 21 21
  • Page 22 22
  • Page 23 23
  • Page 24 24
  • Page 25 25
  • Page 26 26
  • Page 27 27
  • Page 28 28
  • Page 29 29
  • Page 30 30
  • Page 31 31
  • Page 32 32
  • Page 33 33
  • Page 34 34
  • Page 35 35
  • Page 36 36
  • Page 37 37
  • Page 38 38
  • Page 39 39
  • Page 40 40
  • Page 41 41
  • Page 42 42
  • Page 43 43
  • Page 44 44
  • Page 45 45
  • Page 46 46
  • Page 47 47
  • Page 48 48
  • Page 49 49
  • Page 50 50
  • Page 51 51
  • Page 52 52
  • Page 53 53
  • Page 54 54
  • Page 55 55
  • Page 56 56
  • Page 57 57
  • Page 58 58
  • Page 59 59
  • Page 60 60
  • Page 61 61
  • Page 62 62
  • Page 63 63
  • Page 64 64
  • Page 65 65
  • Page 66 66
  • Page 67 67
  • Page 68 68
  • Page 69 69
  • Page 70 70
  • Page 71 71
  • Page 72 72
  • Page 73 73
  • Page 74 74
  • Page 75 75
  • Page 76 76
  • Page 77 77
  • Page 78 78
  • Page 79 79
  • Page 80 80
  • Page 81 81
  • Page 82 82
  • Page 83 83
  • Page 84 84
  • Page 85 85
  • Page 86 86
  • Page 87 87
  • Page 88 88
  • Page 89 89
  • Page 90 90
  • Page 91 91
  • Page 92 92
  • Page 93 93
  • Page 94 94
  • Page 95 95
  • Page 96 96
  • Page 97 97
  • Page 98 98
  • Page 99 99
  • Page 100 100
  • Page 101 101
  • Page 102 102
  • Page 103 103
  • Page 104 104
  • Page 105 105
  • Page 106 106
  • Page 107 107
  • Page 108 108
  • Page 109 109
  • Page 110 110
  • Page 111 111
  • Page 112 112
  • Page 113 113
  • Page 114 114
  • Page 115 115
  • Page 116 116
  • Page 117 117
  • Page 118 118
  • Page 119 119
  • Page 120 120
  • Page 121 121
  • Page 122 122
  • Page 123 123
  • Page 124 124
  • Page 125 125
  • Page 126 126
  • Page 127 127
  • Page 128 128
  • Page 129 129
  • Page 130 130
  • Page 131 131
  • Page 132 132
  • Page 133 133
  • Page 134 134
  • Page 135 135
  • Page 136 136
  • Page 137 137
  • Page 138 138
  • Page 139 139
  • Page 140 140
  • Page 141 141
  • Page 142 142
  • Page 143 143
  • Page 144 144
  • Page 145 145
  • Page 146 146
  • Page 147 147
  • Page 148 148
  • Page 149 149
  • Page 150 150
  • Page 151 151
  • Page 152 152
  • Page 153 153
  • Page 154 154
  • Page 155 155
  • Page 156 156
  • Page 157 157
  • Page 158 158
  • Page 159 159
  • Page 160 160
  • Page 161 161
  • Page 162 162
  • Page 163 163
  • Page 164 164
  • Page 165 165
  • Page 166 166
  • Page 167 167
  • Page 168 168
  • Page 169 169
  • Page 170 170
  • Page 171 171
  • Page 172 172
  • Page 173 173
  • Page 174 174
  • Page 175 175
  • Page 176 176
  • Page 177 177
  • Page 178 178
  • Page 179 179
  • Page 180 180
  • Page 181 181
  • Page 182 182
  • Page 183 183
  • Page 184 184
  • Page 185 185
  • Page 186 186
  • Page 187 187
  • Page 188 188
  • Page 189 189
  • Page 190 190
  • Page 191 191
  • Page 192 192
  • Page 193 193
  • Page 194 194
  • Page 195 195
  • Page 196 196
  • Page 197 197
  • Page 198 198
  • Page 199 199
  • Page 200 200
  • Page 201 201
  • Page 202 202
  • Page 203 203
  • Page 204 204
  • Page 205 205
  • Page 206 206
  • Page 207 207
  • Page 208 208
  • Page 209 209
  • Page 210 210
  • Page 211 211
  • Page 212 212
  • Page 213 213
  • Page 214 214
  • Page 215 215
  • Page 216 216
  • Page 217 217
  • Page 218 218
  • Page 219 219
  • Page 220 220
  • Page 221 221
  • Page 222 222
  • Page 223 223
  • Page 224 224
  • Page 225 225
  • Page 226 226
  • Page 227 227
  • Page 228 228
  • Page 229 229
  • Page 230 230
  • Page 231 231
  • Page 232 232
  • Page 233 233
  • Page 234 234
  • Page 235 235
  • Page 236 236
  • Page 237 237
  • Page 238 238
  • Page 239 239
  • Page 240 240
  • Page 241 241
  • Page 242 242
  • Page 243 243
  • Page 244 244
  • Page 245 245
  • Page 246 246
  • Page 247 247
  • Page 248 248
  • Page 249 249
  • Page 250 250
  • Page 251 251
  • Page 252 252
  • Page 253 253
  • Page 254 254
  • Page 255 255
  • Page 256 256
  • Page 257 257
  • Page 258 258
  • Page 259 259
  • Page 260 260
  • Page 261 261
  • Page 262 262
  • Page 263 263
  • Page 264 264
  • Page 265 265
  • Page 266 266
  • Page 267 267
  • Page 268 268
  • Page 269 269
  • Page 270 270
  • Page 271 271
  • Page 272 272
  • Page 273 273
  • Page 274 274
  • Page 275 275
  • Page 276 276
  • Page 277 277
  • Page 278 278
  • Page 279 279
  • Page 280 280
  • Page 281 281
  • Page 282 282
  • Page 283 283
  • Page 284 284
  • Page 285 285
  • Page 286 286
  • Page 287 287
  • Page 288 288
  • Page 289 289
  • Page 290 290
  • Page 291 291
  • Page 292 292
  • Page 293 293
  • Page 294 294
  • Page 295 295
  • Page 296 296
  • Page 297 297
  • Page 298 298
  • Page 299 299
  • Page 300 300
  • Page 301 301
  • Page 302 302
  • Page 303 303
  • Page 304 304
  • Page 305 305
  • Page 306 306
  • Page 307 307
  • Page 308 308
  • Page 309 309
  • Page 310 310
  • Page 311 311
  • Page 312 312
  • Page 313 313
  • Page 314 314
  • Page 315 315
  • Page 316 316
  • Page 317 317
  • Page 318 318
  • Page 319 319
  • Page 320 320
  • Page 321 321
  • Page 322 322
  • Page 323 323
  • Page 324 324
  • Page 325 325
  • Page 326 326
  • Page 327 327
  • Page 328 328
  • Page 329 329
  • Page 330 330
  • Page 331 331
  • Page 332 332
  • Page 333 333
  • Page 334 334
  • Page 335 335
  • Page 336 336
  • Page 337 337
  • Page 338 338
  • Page 339 339
  • Page 340 340
  • Page 341 341
  • Page 342 342
  • Page 343 343
  • Page 344 344
  • Page 345 345
  • Page 346 346
  • Page 347 347
  • Page 348 348
  • Page 349 349
  • Page 350 350
  • Page 351 351
  • Page 352 352
  • Page 353 353
  • Page 354 354
  • Page 355 355
  • Page 356 356
  • Page 357 357
  • Page 358 358
  • Page 359 359
  • Page 360 360
  • Page 361 361
  • Page 362 362
  • Page 363 363
  • Page 364 364
  • Page 365 365
  • Page 366 366
  • Page 367 367
  • Page 368 368
  • Page 369 369
  • Page 370 370
  • Page 371 371
  • Page 372 372
  • Page 373 373
  • Page 374 374
  • Page 375 375
  • Page 376 376
  • Page 377 377
  • Page 378 378
  • Page 379 379
  • Page 380 380
  • Page 381 381
  • Page 382 382
  • Page 383 383
  • Page 384 384
  • Page 385 385
  • Page 386 386
  • Page 387 387
  • Page 388 388
  • Page 389 389
  • Page 390 390
  • Page 391 391
  • Page 392 392
  • Page 393 393
  • Page 394 394
  • Page 395 395
  • Page 396 396
  • Page 397 397
  • Page 398 398
  • Page 399 399
  • Page 400 400
  • Page 401 401
  • Page 402 402
  • Page 403 403
  • Page 404 404
  • Page 405 405
  • Page 406 406
  • Page 407 407
  • Page 408 408
  • Page 409 409
  • Page 410 410
  • Page 411 411
  • Page 412 412
  • Page 413 413
  • Page 414 414
  • Page 415 415
  • Page 416 416
  • Page 417 417
  • Page 418 418
  • Page 419 419
  • Page 420 420
  • Page 421 421
  • Page 422 422
  • Page 423 423
  • Page 424 424
  • Page 425 425
  • Page 426 426
  • Page 427 427
  • Page 428 428
  • Page 429 429
  • Page 430 430
  • Page 431 431
  • Page 432 432
  • Page 433 433
  • Page 434 434
  • Page 435 435
  • Page 436 436
  • Page 437 437
  • Page 438 438
  • Page 439 439
  • Page 440 440
  • Page 441 441
  • Page 442 442
  • Page 443 443
  • Page 444 444
  • Page 445 445
  • Page 446 446
  • Page 447 447
  • Page 448 448
  • Page 449 449
  • Page 450 450
  • Page 451 451
  • Page 452 452
  • Page 453 453
  • Page 454 454
  • Page 455 455
  • Page 456 456
  • Page 457 457
  • Page 458 458
  • Page 459 459
  • Page 460 460
  • Page 461 461
  • Page 462 462
  • Page 463 463
  • Page 464 464
  • Page 465 465
  • Page 466 466
  • Page 467 467
  • Page 468 468
  • Page 469 469
  • Page 470 470
  • Page 471 471
  • Page 472 472
  • Page 473 473
  • Page 474 474
  • Page 475 475
  • Page 476 476
  • Page 477 477
  • Page 478 478
  • Page 479 479
  • Page 480 480
  • Page 481 481
  • Page 482 482
  • Page 483 483
  • Page 484 484
  • Page 485 485
  • Page 486 486
  • Page 487 487
  • Page 488 488
  • Page 489 489
  • Page 490 490
  • Page 491 491
  • Page 492 492
  • Page 493 493
  • Page 494 494
  • Page 495 495
  • Page 496 496
  • Page 497 497
  • Page 498 498
  • Page 499 499
  • Page 500 500
  • Page 501 501
  • Page 502 502
  • Page 503 503
  • Page 504 504
  • Page 505 505
  • Page 506 506
  • Page 507 507
  • Page 508 508
  • Page 509 509
  • Page 510 510
  • Page 511 511
  • Page 512 512
  • Page 513 513
  • Page 514 514
  • Page 515 515
  • Page 516 516
  • Page 517 517
  • Page 518 518
  • Page 519 519
  • Page 520 520
  • Page 521 521
  • Page 522 522
  • Page 523 523
  • Page 524 524
  • Page 525 525
  • Page 526 526
  • Page 527 527
  • Page 528 528
  • Page 529 529
  • Page 530 530
  • Page 531 531
  • Page 532 532
  • Page 533 533
  • Page 534 534
  • Page 535 535
  • Page 536 536
  • Page 537 537
  • Page 538 538
  • Page 539 539
  • Page 540 540
  • Page 541 541
  • Page 542 542
  • Page 543 543
  • Page 544 544
  • Page 545 545
  • Page 546 546
  • Page 547 547
  • Page 548 548
  • Page 549 549
  • Page 550 550
  • Page 551 551
  • Page 552 552
  • Page 553 553
  • Page 554 554
  • Page 555 555
  • Page 556 556
  • Page 557 557
  • Page 558 558
  • Page 559 559
  • Page 560 560
  • Page 561 561
  • Page 562 562
  • Page 563 563
  • Page 564 564
  • Page 565 565
  • Page 566 566
  • Page 567 567
  • Page 568 568
  • Page 569 569
  • Page 570 570
  • Page 571 571
  • Page 572 572
  • Page 573 573
  • Page 574 574
  • Page 575 575
  • Page 576 576
  • Page 577 577
  • Page 578 578
  • Page 579 579
  • Page 580 580
  • Page 581 581
  • Page 582 582
  • Page 583 583
  • Page 584 584
  • Page 585 585
  • Page 586 586
  • Page 587 587
  • Page 588 588
  • Page 589 589
  • Page 590 590
  • Page 591 591
  • Page 592 592
  • Page 593 593

Broadcom NetXtreme/NetLink BCM5718 Series User guide

Type
User guide

Ask a question and I''ll find the answer in the document

Finding information in a document is now easier with AI