LeCroy PCIE6bus Decoder Software User manual

Brand: LeCroy

Model: PCIE6bus Decoder Software

Category: Measuring, testing & control

Type: User manual

PCIE6bus D Software

Instruction Manual

PCIE6bus Decoder Software Instruction Manual

This document does not contain export controlled information.

Users are permitted to duplicate and distribute Teledyne LeCroy, Inc. documentation for internal educational purposes only.

Resale or unauthorized duplication of Teledyne LeCroy publications is strictly prohibited.

Teledyne LeCroy is a trademark of Teledyne LeCroy, Inc., Inc. Other product or brand names are trademarks or requested

trademarks of their respective holders. Information in this publication supersedes all earlier versions. Specifications are

subject to change without notice.

November, 2023

pcie6bus-d-im-eng_28nov23.pdf

Contents

Introducing the PCIE6bus D Option 1

PCIE6bus Acquisition for Decoding 2

Oscilloscope Requirements 2

Planning Inputs 2

Before Acquisition 3

PCIE6bus Input Set Up 3

PCIE6bus Equalizer Set Up 4

PCIE6bus De-embedding 8

Generating an Eye Diagram 11

Serial Decode 13

Decoding Workflow 14

Decoder Set Up 14

Correcting Poor Quality or Inverted Signals 16

Failure to Decode 17

Serial Decode Dialog 18

Reading Waveform Annotations 19

Serial Decode Result Table 20

Searching Decoded Waveforms 26

Improving Decoder Performance 27

Appendix A: Automating the Decoder 28

Configuring the Decoder 28

Accessing the Result Table 28

Reading the Structure of the Result Table 28

Modifying the Result Table 30

Technical Support 31

PCIE6bus Decoder Software Instruction Manual

About This Manual

This manual explains the basic procedures for using serial data decode software options for Teledyne LeCroy

oscilloscopes. It is assumed that you have a basic understanding of the serial data physical layer specifications, and

how to use the oscilloscope on which the option is installed. Only features specific to this product are explained in

this manual.

While some images may not exactly match what is on your oscilloscope display—or may show an example taken

from another standard—be assured that the functionality is identical. Product-specific exceptions will be noted in the

text.

Some capabilities described may only be available with the latest version of our MAUI®software. Updates are

available from the software download page at teledynelecroy.com under Oscilloscope Downloads > Firmware

Upgrades.

Introducing the PCIE6bus D Option

PCI Express®(PCIe®) is a serial interface standard now pervasive in computing systems and embedded systems.

PCIe utilizes point-to-point connections and typically consists of multiple lanes of both transmit (Tx) and receive (Rx)

datastreams, with data being "striped" across multiple datastreams to achieve higher data transmission rate.

The PCIE6bus D option applies software algorithms to extract PCIe 6.0 serial data information from physical layer

waveforms measured on your oscilloscope. When displayed on oscilloscopes or in MAUI® Studio remote

oscilloscope software, the extracted information overlays the actual physical layer waveforms, color-coded to

provide fast, intuitive understanding of the relationship between messages and other time-synchronous events.

PCIE6bus D decodes 1x1, 1x2, and 4x1 packets.

Note: If you have installed other -DME or -TDME options, the dialogs for Measure/Graph and Eye Diagram

creation will appear when the decoder is open. They may or may not appear "grayed out." We do not support

operation of the functionality for this protocol.

PCIE6bus Decoder Software Instruction Manual

PCIE6bus Acquisition for Decoding

Because the use of SDA Expert (SDAX) equalizers is necessary to achieve sufficient signal quality for decoding at

PCIe 6.0 64 GT/s, it is worthwhile considering how you will acquire signals and input them to the SDAX software in

order to decode different lane configurations.

Oscilloscope Requirements

The oscilloscope used for PCIe 6.0 must support at least 30 GHz bandwidth per channel. It is not strictly necessary

to utilize high-speed DBI channels for acquisition, depending on the fundamental frequency of the signal and the

standard channel bandwidth; you may be able to use all four 33 GHz channels on WaveMaster 8000HD

oscilloscopes or 30/36 GHz channels on LabMaster 10 Zi-A oscilloscopes. In general, however, best signal quality

will be achieved by using DBI.

Planning Inputs

No special probes or fixtures are required to acquire PCIe 6.0 signals for decoding; it is user discretion how you will

input the signals.

However, if you wish to decode bidirectional (PCIE6-1x2 upstream+downstream) traffic on any one lane, each

stream will have to be acquired as a separate differential pair, which in turn form the differential inputs of one SDAX

data "Lane". In other words, one physical lane of bidirectional traffic will equate to two logical lanes in SDAX.

If your signal permits, you can acquire both streams simultaneously over four standard channels, using each pair of

channels as the inputs to SDAX Lane1 and Lane2.

If the fundamental frequency of the signal exceeds the standard bandwidth of each channel, you will have to acquire

each stream separately over two high-bandwidth DBI channels, saving at least one acquisition to internal memory so

that it can be displayed and processed simultaneously with the other stream by the SDAX software and the decoder.

Example: You acquire one upstream lane of data on DBI channels C2B and C3B. You save these two acquired

channels to internal memories M2 and M3. When setting up inputs in SDAX software, M2 and M3 are used as

the differential inputs for Lane1 (the upstream data). You then acquire the downstream data on C2B and C3B.

These channels are then used as the differential inputs for Lane2. Lane1 and Lane2 can both be enabled

simultaneously so they are viewed together in SDAX, and the equalized Lane1 and Lane2 waveforms output

by SDAX are then selected as the two Source inputs to the PCIE6-1x2 decoder, decoding upstream and

downstream data simultaneously.

Likewise, if you wish to decode four lanes of unidirectional traffic (PCIE6-4x1), acquire four differential pairs , saving

two or three pair to memory. Use the memories as well as the last pair of "live" channels as the inputs to SDAX

Lane1-Lane4. These four lanes of equalized data output by SDAX will make the four inputs to the PCIE6-4x1decoder.

Note: SDAX data lanes are labelled Lane1 to Lane4. There is no Lane0 in SDAX. You will have to keep track

of which of your PCIe lanes are displayed by which SDAX lanes.

PCIE6bus Acquisition for Decoding

Before Acquisition

Start by confirming that your DUT(s) are able to transmit by viewing the input channel traces, and adjust the

oscilloscope vertical scale accordingly. It is not necessary to display the input channel traces in SDAX, but any pre-

processing applied to them will be reflected in the test results.

Make all other usual acquisition settings on the oscilloscope, particularly the timebase and trigger necessary to

achieve your desired test record length.

Note: Acquisitions must be at least 10 µs/div long in order for the eye diagram to process.

PCIE6bus Input Set Up

The inputs used by the PCIE6bus decoders, including all signal conditioning such as equalization, are configured

within the SDA Expert software. See the SDA Expert Software Instruction Manual for full instructions on using all the

SDAX functionality included with your decoder. The most important features are briefly described here.

1. Choose Analysis > Serial Decode.

2. Select the decoder to configure (from Decode1 to Decode4) and Protocol to decode (e.g., PCIE6-1x1).

3. Select the Setup button then the Input & Equalizer Setup button to open the SDAX dialogs. The Serial

Standard, Nominal Rate and other selections (e.g., Clock PLL) should already be set for PCIe 64 GT/s.

4. Select and Enable the first logical Lane you will configure as a decoder input, continuing to configure each

lane needed as described below.

5. When you have finished setting up the inputs, set up equalizers. Equalization is necessary for a successful

decoding of PCIe 6.0 PAM4 waveforms.

Serial Data Inputs

With the Lane you are configuring selected, open the Signal dialog. If you have navigated from the decoder dialogs,

the Nominal Rate should already be locked to 32 Gbaud, 64 GT/s.

If you are using a differential probe, or a Diff Channel already calculated from two channels by a WaveMaster

8000HD, choose 1 Input (or Diff. Probe) and select the Input1 source. If using two, single-ended inputs, choose

Input1-Input2 and enter the two channels or memories that make up that logical Lane of data.

Note: There is no need to configure a math function to calculate the difference between the two inputs.

When in Input1-Input2 mode, or when using any math or memory traces, be sure that both traces have the

same record length and sample rate.

You can choose to Upsample the input signal(s) in order to provide a higher sample density for analysis.

Levels & Thresholds

Enter the percent amplitude or absolute voltage level that marks the crossing threshold for each level in the signal.

Once there is an acquisition in buffer, touch the Find Level button to allow the software to calculate the actual levels

from the input signal. The software finds the best fit estimates of the four levels and their mean thresholds.

PCIE6bus Decoder Software Instruction Manual

To prevent false determinations due to noise, etc., enter a Hysteresis value. The default hysteresis band is 500 mDiv

(half of a division), centered on the crossing threshold. Edges that fail to transit the entire hysteresis band are not

detected.

Test Pattern

You can allow the software to Auto Detect the signal pattern sent from the DUT, use one of the Built-In patterns or

upload a custom pattern From File.

In general, Auto Detect is sufficient for identifying the pattern from the DUT. However, you may find it helps with

pattern identification to choose from the many Built-in PCIe signal patterns available, matching the speed and lane

being decoded.

In cases where the signal was connected to the oscilloscope with inverted polarity, you can use the Invert Pattern

checkbox to correct it.

PCIE6bus Equalizer Set Up

Equalizers are used to improve signal integrity by conditioning the signal in ways that counteract Inter Symbol

Interference (ISI) and other types of jitter or noise caused by channel response.

A selection of Continuous Time Linear, Feed Forward and Decision Feedback equalizers can be applied to the inputs

prior to outputting the signals to decoders for analysis. All equalizers can be trained on the input signal following a

brief acquisition for efficient equalizer set up.

Note: Equalizing is essential to correctly decode PCIe 6.0 signals, and the EQ dialogs will always be active

whether you are decoding PCIe 6.0 or a lower speed grade of PCIe.

When you have finished equalizer set up for all sources, go on to set up any required emulation/de-embedding.

CTLE

Continuous Time Linear Equalization (CTLE) is a linear filter that attenuates low-frequency signal components,

amplifies components around the Nyquist frequency, and filters off higher frequencies. When this selection is

enabled, a first-order CTLE is implemented according to the PCIe standards.

To apply CTLE to the signal:

1. Select the Linear EQ block of the SDAX flow, then on the Linear EQ dialog select a Data Path to DFE of either

From CTLE or From FFE to include the CTLE among the processors applied to the data stream.

2. Select the CTLE block, then on the CTLE Setup dialog, check Enable and enter the desired Boost in decibels.

The default Auto selection automatically sets up the reference CTLE for the speed. Once there is an

acquisition in buffer, the software will calculate the optimal number of poles and zeros needed to yield that

DC Gain value at the Nominal Rate.

The CTLE tap values are displayed on the CTLE Details dialog, but they will not be editable with Auto selected.

Select the Edit/View CTLE Setup button to view them.

3. If you are not satisfied with the results, you can use the procedure below to determine the best DC Gain

setting, or switch to Custom and make your own CTLE configuration on the CTLE Details dialog.

PCIE6bus Acquisition for Decoding

Finding Optimal Boost

The default Boost is a good starting point. If you do not see good transitions at that setting, try increasing the value

incrementally. The following method can be used to determine the efficacy of different values.

1. Display the unequalized source signal along with the equalized signal by checking Show SDAX Input on the

SDAX dialog.

2. Zoom in on both signals until you can clearly see the upper and lower transitions. It is OK if this is only a very

small section of the original acquisition.

3. Move both zoom traces onto the same grid so that they overlap, then place vertical cursors on the zooms at

both the upper and lower transition levels.

4. Go to Math > Zoom Setup > MultiZoom and add both zooms to a MultiZoom group with Same zoom position.

5. Drag the zoom traces left or right, or use the Zoom Auto-Scroll controls, until you find a section of the

acquisition where the equalized trace fails to cross the thresholds. This would cause a decoder to fail.

6. Examine the zooms and increase the Boost dB value until the entire equalized trace clears the transition

thresholds, as shown below.

Manually Tuning the CTLE

To modify the CTLE tap values applied, touch Custom and Edit/View CTLE Details to open the CTLE Details dialog.

Enter the custom settings to be used.

Continue to reacquire and modify until there is no longer any drop out of the equalized trace. Leave the Custom

button selected to use your CTLE settings.

Tip: We recommend using Auto unless you have experience configuring CTLEs and know what results your

selections will yield. The software is designed to automate as many of these selections as possible

according to the bit rate of the signal.

Note: If you later change CTLE settings, repeat Find Rate and Nominal Levels and retrain the FFE and DFE.

FFE

Feed Forward Equalization (FFE) boosts the amplitudes of symbols surrounding transitions while keeping the

transmitted power constant. In principle, FFE should be able to invert ISI if the number of symbols modified—that is,

the number of “taps”—extends over the entire length of the pulse response.

To apply FFE to the signal:

1. Select the Linear EQ block of the SDAX flow, then on the Linear EQ dialog select a Data Path to DFE of From

FFE to include the FFE among the processors applied to the data stream.

2. Select the FFE block, then on the FFE Setup dialog check Enable.

3. Make an acquisition so that there is data in the buffer on which to Train FFE.

Training FFE

The Levenberg–Marquardt method is used to train on the optimal tap values to use in the FFEfilters. The variable

that is minimized is the range of the high and low voltages near the center of the eye. Minimizing this quantity

maximizes the eye opening. Complete the following settings to configure the training algorithm.

PCIE6bus Decoder Software Instruction Manual

In # Desired Taps, enter a value that spans the number of UIs the signal takes when settling to a final value after a

transition. The training algorithm will create a filter with the number of taps entered.

Specify how many of those taps should be precursor taps in # Precursor Taps.

Note: The number of precursor taps is often around half of the total number of taps.

When Auto find levels is selected, the training algorithm will find the optimal Levels of the equalized eye as well as

the determination Thresholds to use, and these fields are disabled, although they will show the levels calculated

from the input signal. The voltage levels of the minimized locations of high and low states will tend to match the

outmost voltage levels of the unequalized eye.

To specify these levels instead, deselect Auto find levels and for each logical level in the signal, enter the:

lThe expected voltage Level corresponding the signal state (first column)

lThe voltage Threshold marking the transition to the next state (second column)

Touch the Train FFE button to begin the FFE training process.

FFE Details

While the best way to use the FFE is to train it, you can also enter the exact tap weights (if known) on the FFE Details

dialog. Touch the Edit/View FFE Setup button to display it.

Specify the # Taps Used in the FFE filter and the # Precursor Taps. If you began your setup by training the FFE, these

controls now show the values set on the FFE Setup dialog. Changing values in either place updates them

everywhere. Enter the tap coefficients on each row.

The Clear Taps button sets all the taps to 0 except for the first tap, which is set to 1. This is the pass-through state

for the FFE.

DFE

Decision Feedback Equalization (DFE) helps to account for distortion in the current symbol that is caused by the

previous symbols. It does so by feeding a sum of logic or symbol decisions back to the software. Tap0 represents

the boost applied to the post-cursor following all decisions.

Note: DFE requires a clock, which is recovered from the data following the application of the CTLE and/or

FFE. If DFE is enabled, you may have to enable CTLE and/or FFE to ensure the software can accurately

recover a clock.

PCIE6bus Acquisition for Decoding

1. Begin by touching the DFE block of the SDAX flow, then Enableon the DFE Setup dialog.

2. Optionally, select the Show EQ Out checkbox to display the signal as it appears after equalization.

3. If there is not yet an acquisition in buffer, make an acquisition on which to Train DFE.

Training DFE

As with the FFE, the DFE can automatically train using the Levenberg–Marquardt algorithm. The variable that is

minimized is the range of the high and low voltages near the center of the eye. Minimizing this quantity maximizes

the eye opening.

Complete the following settings to configure the training algorithm.

In # Taps, enter a value to span the number of UIs the signal takes when settling to a final value after a transition.

The training algorithm will create a filter with the number of taps entered.

In Max UIs for train, enter the maximum number of unit intervals to use for training. We suggest leaving this value at

1000. Higher values make the training slower, and much lower values may reduce the training accuracy.

When Auto find levels is selected, the training algorithm will find the optimal Levels of the equalized eye as well as

the determination Thresholds to use, and these fields are disabled, although they will show the levels calculated

from the input signal. The voltage levels of the minimized locations of high and low states will tend to match the

outmost voltage levels of the unequalized eye.

To specify these levels instead, deselect Auto find levels and manually enter the Target Levels & Thresholds, same

as with the FFE.

Touch the Train DFE button to begin the DFE training process.

The Clear Taps and Skew button resets all the taps to 0. This is the pass-through state for the DFE.

DFE Details

While the best way to use the DFE is to train it, you can also manually enter the exact tap weights (if known) on the

DFE Details dialog. Touch the Edit/View DFE Setup button to display it.

You will see the # Taps Used by the DFE filter. Enter the coefficients for each tap. Use Clear Taps to remove the

previous data.

DFEs are prone to burst errors (meaning, once errors are created, they run for a long time). The DFE's propensity to

create burst errors is based on the effectiveness of the DFE to aid in the accurate decoding of bits, which depends

on its ability to accurately decode bits - a case of circular logic. Depending on the strength of DFE applied, a single bit

error may lead to a long run of errors. Erasure DFE is used for this problem and improves the situation. Erasure DFE

effectively sets a band around the threshold value. When the signal falls inside the band at the time of slicing, it

indicates an uncertainty in the bit decoding. The receiver, although obliged to decode the bit, can then decide not to

apply this bit to the decision feedback, since the decoding was not certain enough. In operation, if erasure DFE is

utilized and the signal is within the voltage delta about the threshold specified, a voltage value that is the average of

the ideal +1 and -1 values is applied to the DFE delay taps, causing the bit to have no effect on decision feedback.

The Erasure DFE feature excludes certain bits within the specified Erasure Delta from the decision feedback. Use the

Erasure Delta control to set the indecision band around the DFEthreshold.

Note: As with the FFE, it is advisable to allow the software to train rather than try to manually configure the

DFE, unless you are experienced at doing so.

Clear and re-train whenever the input levels change.

PCIE6bus Decoder Software Instruction Manual

PCIE6bus De-embedding

Fixture De-embedding allows you to move the measurement reference to a point before the fixture, such as directly

to the transmitter output, by removing the effects of the fixture.

Channel Emulation / De-embedding allows you to to move the measurement reference to a different point in the

system than the probing point—either to the end of a channel by emulating the channel effects or to the start of a

channel by de-embedding the channel (similar to fixture de-embedding).

To perform either operation, touch the Emulate / De-embed block of the SDAX dialog flow to access the Emulate/De-

embed dialog, then check Enable to turn on the functionality.

When you have finished configuring any required emulation/de-embedding, go on to generate an eye diagram to

confirm the settings will yield a good eye, which usually indicates that the signal will decode properly.

Configuration

The Configuration control on the Emulate /Deembed dialog offers the following three configurations.

Emulate Channel /De-embed Fixture

This configuration de-embeds a fixture and emulates a serial data channel at the same time. It is best used when

you are using a fixture to measure at the transmitter side of the serial data channel. It first moves the measurement

reference to the output of the transmitter, and then moves the reference to the far side of a serial data channel.This

allows for emulating the effects of the serial data channel on your signal with the fixture effects removed.

De-embed Channel / De-embed Fixture

This configuration de-embeds both a fixture and a serial data channel at the same time. This is best when using a

fixture to measure at the receiver side of the serial data channel. It moves the measurement reference back to the

output of the transmitter. You then see what the serial data signal looked like at the transmitters output with the

effects of the channel and fixture removed.

De-embed Fixture Only

This configuration removes the effects of fixtures from you measurements. You can then see what the serial data

signal looks like at the transmitters output.

PCIE6bus Acquisition for Decoding

Bandwidth Limit

When de-embedding a fixture or channel, a bandwidth limit is required and must be set.

Note: When emulating a passive fixture or channel, the S-Parameter system does not have any boost, and

the bandwidth used is the highest bandwidth possible.

The Bandwidth Limit control imposes a reasonably sharp low pass filter in addition to the S-Parameter system

response. This is useful when de-embedding a lossy channel, to limit the amount of boost applied. When a channel

is de-embedded, high frequency response must be boosted to compensate for the high frequency attenuation in the

channel. However, if the signal has been attenuated into the noise floor, boosting the signal on the oscilloscope

makes it impossible to distinguish between the signal and the noise. The system boosts the noise along with the

signal. The BandwidthLimit setting can limit the overall response to the lower frequencies where signal components

are detectable above the noise. If this value is set to zero (the default) then no bandwidth limit is applied.

Auto BW allows the software to determine the limit, using a specified Max Boost and filter Order. Max Boost has the

same effect as Bandwidth Limit, but instead of setting the frequency, you set the maximum boost allowed. The

software looks at the S-Parameter responses and sets up the low-pass filter at the frequency where one of the

outputs has more boost than the specified Max Boost. The resulting bandwidth is reported to the user.

Bandwidth Limit is only required if the configuration actually includes de-embedding. If you choose the Emulate

Channel / De-embed Fixture configuration, but leave the De-embed Fixture block set to "Ideal" (pass through), the

bandwidth limit has no effect on the signal.

Upload and Map S-parameters

To emulate/de-embed a fixture or channel with loss, after choosing the configuration and setting bandwidth limits,

touch the De-embed Fixture or Emulate Channel blocks that appear in the flow. On the respective Fixture and

Channel dialogs, check Use Ideal Fixture or Use Ideal Channel. This eliminates the block from the process (it has no

effect on the signal), even if it appears in the configuration flow. No further configuration is necessary.

To emulate/de-embed a fixture or channel with loss, map the ports in the S-parameter files that define the loss

characteristics for each block where they are used.

Note: S-Parameter files should cover a frequency range up to (at least) 1/2 the oscilloscope's sample rate.

For example, if the S-Parameter file covers up to 10 GHz, the oscilloscope sample rate should be 20 GS/s.

When a fixture or channel is being emulated, there is little effect. However, if it is being de-embedded, then

the S-Parameter matrix must be inverted. S-parameters that do not have data up to half the oscilloscope's

sample rate can cause problems, particularly when de-embedding.

1. Touch Browse and navigate to the S-Parameter file representing the fixture or channel.

2. Choose the S-Parameter Format in use, either Single-Ended or Mixed Mode.

3. Assign to each Port a data column from the selected S-Parameter file. (This is useful for re-mapping from the

same S-Parameter file.)

4. Optionally, use View Response to plot the S-parameters.

PCIE6bus Decoder Software Instruction Manual

Apply Model

When you have completed the setup for each block in the configuration, touch Apply.Apply builds the system

description for the circuit and compiles it. The color indicator next to the Apply button shows the compilation status:

lGreen if everything is properly setup.

lYellow if the settings have changed and recompiling is needed.

lRed if something is wrong with either the S-Parameter file or port assignment. Choose View Response to plot

S-parameter Magnitude or Phase to help debug your issue.

Optionally, select Show Chann(el) Out to display the input signal as it appears following the emulation/de-embedding

processes, but before any other signal conditioning.

PCIE6bus Acquisition for Decoding

Generating an Eye Diagram

Use the PAM4 Eye dialog to generate eye diagrams of the equalized signals, confirming good signal quality for

decoding. To open it, touch the PAM4 Eye Meas. block of the SDAX dialog flow.

Modify your equalizer settings until you have achieved a satisfactory eye diagram, then choose the Decoder button

from the far right of the SDAX flow to return to the decoder dialogs and finish configuring the decoder.

Eye Diagram Set Up

1. On the PAM4 Eye dialog, select Enable Eye Meas.(ure) to turn on eye diagram functionality. Deselecting it will

turn off all eye diagrm views and parameters.

2. Select Show Eye to create the eye diagram for all displayed lanes.

3. Choose an Eye Scale setting that maximizes use of the vertical grid.

lNormal uses the vertical scale (V/div) of the data signal input to the Eye diagram algorithm. This

typically will be the V/div of the source when using 1 input, or the sum when using two inputs.

lAuto Fit All Lanes adjusts the vertical scales to a value and offset that places the top level at +2.5 div,

and the bottom level at -2.5 div.

lLock All Lanes sets the vertical scale of all eye diagrams to the values entered in the adjacent VerOffset

and Ver Scale entry fields.

Note: All eye diagrams generated for all lanes will share the same eye scale and style.

4. Optionally, enter a Delta X value in thousandths of a UI (mUI) to shift the horizontal position of the eye

diagram on the grid.

5. Choose an Eye Style:

With color-graded persistence , pixels are given a color based on the pixel's relative population and

the selected Eye Saturation. The color palette ranges from violet (lowest) to red (highest).

With analog persistence , the color used mimics the relative intensity that would be seen on an

analog oscilloscope.

6. Use the Eye Saturation slider to adjust the color grading or intensity. Slide to the left to reduce the threshold

required to reach saturation.

7. The Upsample factor increases the number of sample points used to compose the eye diagram. Optionally,

increase the value from 1 to a higher number (e.g., 5) to fill in gaps.

Note: Gaps can occur when the bitrate is extremely close to a submultiple of the sampling rate, such

that the sampling of the waveform does not move throughout the entire unit interval. Gaps can also

occur when using a record length that does not sample a sufficiently large number of unit intervals.

Using record lengths of ≥ 1 million points is recommended in order to acquire tens of thousands, if

not hundreds of thousands, of unit intervals.

PCIE6bus Decoder Software Instruction Manual

Eye Views

Show Eye displays the eye diagram of the input signal.

Show Levels visually annotates the measured voltage values of the 0, 1, 2 and 3 levels on the eye diagram.

Show IsoBER superimposes an extrapolated eye contour at a single BER onto each of the three eye openings. The

measurement locations of the eye heights and widths are annotated on these contours. Enter the BER value for

which you would like to show contours in the IsoBER plot.

Eye Descriptor Box

The Eye diagram descriptor box shows the V/div, Time/div, and total number of UIs represented

by the eye. If vertical cursors are placed on the eye, cursor readout values appear in subsequent

lines.

Serial Decode

The methods described here at a high level are used by all Teledyne LeCroy serial decoders, differing only slightly for

signals with an embedded clock and separate clock and data signals.

Bit-level Decoding

The first software algorithm examines the embedded clock based on a default or user- specified vertical threshold

level. Once the clock signal is extracted, the algorithm examines the traffic to determine whether a data bit is high or

low. The default High and Low levels are automatically determined from a measurement of the amplitude of the

signals acquired by the oscilloscope. Alternatively, they can be manually set by the user. The algorithm intelligently

applies a hysteresis to the rising and falling edge of the serial data signal to minimize the chance of perturbations or

ringing on the edge affecting the data bit decoding.

Note: Although the decoding algorithm is based on a clock extraction software algorithm using a vertical

level, the results returned are the same as those from a traditional protocol analyzer using sampling point-

based decode.

Logical Decoding

After determining individual data bit values, another algorithm performs a decoding of the serial data message after

separation of the underlying data bits into logical groups specific to the protocol (Header/ID, Address Labels, Data

Length Codes, Data, CRC, Parity Bits, Start Bits, Stop Bits, Delimiters, Idle Segments, etc.).

Message Decoding

Finally, another algorithm applies a color overlay with annotations to the decoded waveform to mark the transitions

in the signal. Decoded message data is displayed in tabular form below the grid. Various compaction schemes are

utilized to show the data for the duration of the acquisition, from as little as one serial data message acquisition to

many thousands. In the case of long acquisitions, only the most important information is highlighted, whereas with

the shortest acquisition, all information is displayed with additional highlighting of the complete message frame.

User Interaction

Your interaction with the software in many ways mirrors the order of the algorithms. You will:

lAssign a protocol/encoding scheme and data sources to one of the four decoder panels on the Serial Data and

Decode Setup dialogs. Each decoder can utilize different protocols or data sources, or have other variations,

giving you maximum flexibility to compare different signals or view the same signal from multiple perspectives.

lComplete the remaining subdialogs required by the protocol/encoding scheme. Once there is an acquisition in

buffer, you will see a result table and an annotation overlay on the waveform trace showing the decoded data.

lWork with the annotated waveform, result table and other functionality to analyze the decoding.

PCIE6bus Decoder Software Instruction Manual

Decoding Workflow

We recommend the following workflow for effective decoding:

1. Set up the decoder using the lowest level decoding mode available, but do not yet enable it.

2. Acquire at least one complete transmission reasonably well centered on screen in both directions, with

generous idle segments on both sides.

Note: See Failure to Decode for more information about the required acquisition settings.

3. Stop acquisition, then enable the decoder. It will operate on the acquisition in buffer.

4. Use the various decoder tools to verify that transitions are being correctly decoded. Tune the decoder

settings as needed to produce a satisfactory decoding.

5. Once you are correctly decoding in one mode, continue making small acquisitions of five to eight

transmissions and run the decoder in higher level modes.

6. Finally, run the decoder on acquisitions of the desired length.

When you are satisfied the decoder is working properly, you can disable/enable the decoder as desired without

having to repeat this tuning process, provided the basic signal characteristics do not change.

Decoder Set Up

Use Decode Setup and its subdialogs to configure decoders.

1. Choose Analysis > Serial Decode from the oscilloscope menu bar.

2. On the Serial Decode dialog, enable the decoder by checking On next to the decoder number. This may be

done any time, although we recommend having an acquisition in buffer before enabling the decoder.

3. Click the Setup button at the end of the row to open the Decode Setup dialog.

4. Select the Protocol to be decoded and the inputs (sources). This selection drives the other fields that appear.

5. Define the level of decoding on the subdialogs to the right of the Decode Setup dialog.

Note: The PCIE6bus decoders are integrated with SDA Expert to provide equalizer and eye diagram

capabilities. Following decoder selection, you set up the actual inputs within SDAX. Decoding is performed

on the equalized output of SDAX.

Serial Decode

Inputs and Equalization

Select Input & Equalizer Setup to open SDA Expert and be sure to:

1. Choose the correct Lane number to configure and Serial Standard to decode.

2. Define inputs.

3. Make equalization and emulation/de-embedding settings.

4. Generate an eye diagram to confirm the signal quality is sufficient for decoding.

5. Use the Decoder button at the far right of the SDAX framework dialog to return to the decoder dialogs.

6. On Decode Setup, for each SDAX Lane that is to be used as a decoder source, select the correct SDAEqDig

equalized waveform.

Note: When you open the Source Selector popup, first choose Category SDA and Subcategory

corresponding to the SDAX Lane (L1-L4), then choose the SDAEqDig Source waveform. Note that

you will need to configure a different SDAX Lane for each PCIe 6.0 data lane or bidirectional stream

to be decoded, and for each Lane you will need to input a different SDAEqDig waveform.

PCIe Decoder Subdialog

The subdialog should already show the locked 64 Gbit/s signal Bit Rate.

If the signal utilizes precoding, check Precoded.

PCIE6bus Decoder Software Instruction Manual

Correcting Poor Quality or Inverted Signals

It is important to provide a high-quality signal when using a Serial Decode package; this is true for PCI Express

decoders as well as all other types. If bits cannot be interpreted correctly, the decoding will be bad. Follow these

guidelines to ensure good signal quality:

lDo not capture in the middle of the bus (at the PCIE connector) as reflections may seriously degrade the signal.

lEqualize at higher speeds. Signals traversing a significant length of printed circuit board material above 5 GT/s

may warrant some equalization, depending on the quality of the probe and where it was connected. Above

8 GT/s, equalization is most definitely required.

lUse correct polarity signal. An oscilloscope cannot automatically determine if the signal is inverted and

compensate like real receivers do. Therefore, the decoder tries to parse the signal supplied – it has no choice

because the acquisition may begin long after link initialization. Therefore it is important to give the decoder a

signal with correct polarity. If the decode table shows many UNRECOGNIZED and single bytes of IDL (basically

junk), then the signal probably needs to be inverted. Use the Invert checkbox on the input channel dialog.

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LeCroy PCIE6bus Decoder Software User manual

Brand: LeCroy

Model: PCIE6bus Decoder Software

Category: Measuring, testing & control

Type: User manual

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LeCroy PCIE6bus Decoder Software User manual

LeCroy PCIE6bus Decoder Software User manual

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