MC9S08PA16 Reference Manual
Supports: MC9S08PA16(A) and MC9S08PA8(A)
Document Number: MC9S08PA16RM
Rev 2, 08/2014
MC9S08PA16 Reference Manual, Rev. 2, 08/2014
2 Freescale Semiconductor, Inc.
Contents
Section number Title Page
Chapter 1
Device Overview
1.1 Introduction.....................................................................................................................................................................31
1.2 MCU block diagram....................................................................................................................................................... 32
1.3 System clock distribution................................................................................................................................................33
Chapter 2
Pins and connections
2.1 Device pin assignment.................................................................................................................................................... 37
2.2 Pin functions................................................................................................................................................................... 39
2.2.1 Power (VDD, VSS)..........................................................................................................................................39
2.2.2 Analog power supply and reference pins (VDDA/VREFH and VSSA/VREFL)............................................40
2.2.3 Oscillator (XTAL, EXTAL)............................................................................................................................ 40
2.2.4 External reset pin (RESET)..............................................................................................................................41
2.2.5 Background/mode select (BKGD/MS)............................................................................................................ 41
2.2.6 Port A input/output (I/O) pins (PTA–PTA0)................................................................................................... 42
2.2.7 Port B input/output (I/O) pins (PTB7–PTB0)..................................................................................................43
2.2.8 Port C input/output (I/O) pins (PTC–PTC0)....................................................................................................43
2.2.9 Port D input/output (I/O) pins (PTD7–PTD0)................................................................................................. 43
2.2.10 Port E input/Output (I/O) pins (PTE4–PTE0)..................................................................................................43
2.2.11 True open drain pins (PTA3–PTA2)................................................................................................................43
2.2.12 High current drive pins (PTB4, PTB5, PTD0, PTD1).....................................................................................44
2.2.13 Peripheral pinouts............................................................................................................................................ 44
Chapter 3
Power management
3.1 Introduction.....................................................................................................................................................................47
3.2 Features...........................................................................................................................................................................47
3.2.1 Run mode......................................................................................................................................................... 47
3.2.2 Wait mode........................................................................................................................................................48
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3.2.3 Stop3 mode...................................................................................................................................................... 48
3.2.4 Active BDM enabled in stop3 mode................................................................................................................48
3.2.5 LVD enabled in stop mode.............................................................................................................................. 49
3.2.6 Power modes behaviors................................................................................................................................... 49
3.3 Low voltage detect (LVD) system..................................................................................................................................50
3.3.1 Power-on reset (POR) operation......................................................................................................................51
3.3.2 LVD reset operation.........................................................................................................................................51
3.3.3 Low-voltage warning (LVW).......................................................................................................................... 51
3.4 Bandgap reference.......................................................................................................................................................... 52
3.5 Power management control bits and registers................................................................................................................ 52
3.5.1 System Power Management Status and Control 1 Register (PMC_SPMSC1)................................................52
3.5.2 System Power Management Status and Control 2 Register (PMC_SPMSC2)................................................54
Chapter 4
Memory map
4.1 Memory map...................................................................................................................................................................55
4.2 Reset and interrupt vector assignments...........................................................................................................................56
4.3 Register addresses and bit assignments.......................................................................................................................... 57
4.4 Random-access memory (RAM).................................................................................................................................... 67
4.5 Flash and EEPROM........................................................................................................................................................68
4.5.1 Overview..........................................................................................................................................................68
4.5.2 Function descriptions....................................................................................................................................... 70
4.5.2.1 Modes of operation........................................................................................................................ 70
4.5.2.2 Flash and EEPROM memory map.................................................................................................70
4.5.2.3 Flash and EEPROM initialization after system reset.....................................................................71
4.5.2.4 Flash and EEPROM command operations.....................................................................................71
4.5.2.5 Flash and EEPROM interrupts.......................................................................................................76
4.5.2.6 Protection....................................................................................................................................... 77
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4.5.2.7 Security.......................................................................................................................................... 80
4.5.2.8 Flash and EEPROM commands.....................................................................................................82
4.5.2.9 Flash and EEPROM command summary...................................................................................... 84
4.6 Flash and EEPROM registers descriptions.....................................................................................................................98
4.6.1 Flash Clock Divider Register (NVM_FCLKDIV)...........................................................................................98
4.6.2 Flash Security Register (NVM_FSEC)............................................................................................................99
4.6.3 Flash CCOB Index Register (NVM_FCCOBIX)............................................................................................ 100
4.6.4 Flash Configuration Register (NVM_FCNFG)............................................................................................... 100
4.6.5 Flash Error Configuration Register (NVM_FERCNFG).................................................................................101
4.6.6 Flash Status Register (NVM_FSTAT).............................................................................................................102
4.6.7 Flash Error Status Register (NVM_FERSTAT).............................................................................................. 103
4.6.8 Flash Protection Register (NVM_FPROT)......................................................................................................104
4.6.9 EEPROM Protection Register (NVM_EEPROT)............................................................................................105
4.6.10 Flash Common Command Object Register:High (NVM_FCCOBHI)............................................................106
4.6.11 Flash Common Command Object Register: Low (NVM_FCCOBLO)...........................................................107
4.6.12 Flash Option Register (NVM_FOPT)..............................................................................................................107
Chapter 5
Interrupt
5.1 Interrupts.........................................................................................................................................................................109
5.1.1 Interrupt stack frame........................................................................................................................................ 110
5.1.2 Interrupt vectors, sources, and local masks......................................................................................................111
5.1.3 Hardware nested interrupt................................................................................................................................114
5.1.3.1 Interrupt priority level register.......................................................................................................115
5.1.3.2 Interrupt priority level comparator set........................................................................................... 116
5.1.3.3 Interrupt priority mask update and restore mechanism..................................................................116
5.1.3.4 Integration and application of the IPC........................................................................................... 117
5.2 IRQ..................................................................................................................................................................................117
5.2.1 Features............................................................................................................................................................ 118
5.2.1.1 Pin configuration options...............................................................................................................118
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5.2.1.2 Edge and level sensitivity.............................................................................................................. 119
5.3 Interrupt pin request register...........................................................................................................................................119
5.3.1 Interrupt Pin Request Status and Control Register (IRQ_SC).........................................................................120
5.4 Interrupt priority control register.................................................................................................................................... 121
5.4.1 IPC Status and Control Register (IPC_SC)......................................................................................................122
5.4.2 Interrupt Priority Mask Pseudo Stack Register (IPC_IPMPS)........................................................................ 123
5.4.3 Interrupt Level Setting Registers n (IPC_ILRSn)............................................................................................123
Chapter 6
System control
6.1 System device identification (SDID)..............................................................................................................................125
6.2 Universally unique identification (UUID)......................................................................................................................125
6.3 Reset and system initialization........................................................................................................................................125
6.4 System options................................................................................................................................................................126
6.4.1 BKGD pin enable.............................................................................................................................................126
6.4.2 RESET pin enable............................................................................................................................................126
6.4.3 SCI0 pin reassignment..................................................................................................................................... 126
6.4.4 SPI0 pin reassignment......................................................................................................................................127
6.4.5 IIC pins reassignments.....................................................................................................................................127
6.4.6 FTM0 channels pin reassignment.................................................................................................................... 127
6.4.7 FTM2 channels pin reassignment.................................................................................................................... 127
6.4.8 Bus clock output pin enable.............................................................................................................................127
6.5 System interconnection...................................................................................................................................................128
6.5.1 SCI0 TxD modulation......................................................................................................................................128
6.5.2 SCI0 RxD capture............................................................................................................................................ 129
6.5.3 SCI0 RxD filter................................................................................................................................................ 129
6.5.4 FTM2 software synchronization...................................................................................................................... 130
6.5.5 ADC hardware trigger......................................................................................................................................130
6.6 System Control Registers................................................................................................................................................131
6.6.1 System Reset Status Register (SYS_SRS).......................................................................................................131
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6.6.2 System Background Debug Force Reset Register (SYS_SBDFR)..................................................................133
6.6.3 System Device Identification Register: High (SYS_SDIDH)......................................................................... 134
6.6.4 System Device Identification Register: Low (SYS_SDIDL).......................................................................... 134
6.6.5 System Options Register 1 (SYS_SOPT1)...................................................................................................... 135
6.6.6 System Options Register 2 (SYS_SOPT2)...................................................................................................... 136
6.6.7 System Options Register 3 (SYS_SOPT3)...................................................................................................... 137
6.6.8 System Options Register 4 (SYS_SOPT4)...................................................................................................... 138
6.6.9 Illegal Address Register: High (SYS_ILLAH)................................................................................................139
6.6.10 Illegal Address Register: Low (SYS_ILLAL).................................................................................................139
6.6.11 Universally Unique Identifier Register 1 (SYS_UUID1)................................................................................140
6.6.12 Universally Unique Identifier Register 2 (SYS_UUID2)................................................................................140
6.6.13 Universally Unique Identifier Register 3 (SYS_UUID3)................................................................................141
6.6.14 Universally Unique Identifier Register 4 (SYS_UUID4)................................................................................141
6.6.15 Universally Unique Identifier Register 5 (SYS_UUID5)................................................................................142
6.6.16 Universally Unique Identifier Register 6 (SYS_UUID6)................................................................................142
6.6.17 Universally Unique Identifier Register 7 (SYS_UUID7)................................................................................143
6.6.18 Universally Unique Identifier Register 8 (SYS_UUID8)................................................................................143
Chapter 7
Parallel input/output
7.1 Introduction.....................................................................................................................................................................145
7.2 Port data and data direction.............................................................................................................................................147
7.3 Internal pullup enable..................................................................................................................................................... 148
7.4 Input glitch filter setting..................................................................................................................................................148
7.5 High current drive...........................................................................................................................................................149
7.6 Pin behavior in stop mode...............................................................................................................................................149
7.7 Port data registers............................................................................................................................................................149
7.7.1 Port A Data Register (PORT_PTAD)..............................................................................................................150
7.7.2 Port B Data Register (PORT_PTBD).............................................................................................................. 150
7.7.3 Port C Data Register (PORT_PTCD).............................................................................................................. 151
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7.7.4 Port D Data Register (PORT_PTDD)..............................................................................................................151
7.7.5 Port E Data Register (PORT_PTED)...............................................................................................................152
7.7.6 Port High Drive Enable Register (PORT_HDRVE)........................................................................................152
7.7.7 Port A Output Enable Register (PORT_PTAOE)............................................................................................153
7.7.8 Port B Output Enable Register (PORT_PTBOE)............................................................................................ 154
7.7.9 Port C Output Enable Register (PORT_PTCOE)............................................................................................ 156
7.7.10 Port D Output Enable Register (PORT_PTDOE)............................................................................................157
7.7.11 Port E Output Enable Register (PORT_PTEOE).............................................................................................158
7.7.12 Port A Input Enable Register (PORT_PTAIE)................................................................................................159
7.7.13 Port B Input Enable Register (PORT_PTBIE)................................................................................................ 160
7.7.14 Port C Input Enable Register (PORT_PTCIE)................................................................................................ 161
7.7.15 Port D Input Enable Register (PORT_PTDIE)................................................................................................163
7.7.16 Port E Input Enable Register (PORT_PTEIE).................................................................................................164
7.7.17 Port Filter Register 0 (PORT_IOFLT0)...........................................................................................................165
7.7.18 Port Filter Register 1 (PORT_IOFLT1)...........................................................................................................166
7.7.19 Port Filter Register 2 (PORT_IOFLT2)...........................................................................................................166
7.7.20 Port Clock Division Register (PORT_FCLKDIV).......................................................................................... 167
7.7.21 Port A Pullup Enable Register (PORT_PTAPE)............................................................................................. 168
7.7.22 Port B Pullup Enable Register (PORT_PTBPE)..............................................................................................169
7.7.23 Port C Pullup Enable Register (PORT_PTCPE)..............................................................................................171
7.7.24 Port D Pullup Enable Register (PORT_PTDPE)............................................................................................. 172
7.7.25 Port E Pullup Enable Register (PORT_PTEPE)..............................................................................................173
Chapter 8
Clock management
8.1 Clock module..................................................................................................................................................................175
8.2 Internal clock source (ICS)............................................................................................................................................. 177
8.2.1 Function description.........................................................................................................................................177
8.2.1.1 Bus frequency divider.................................................................................................................... 178
8.2.1.2 Low power bit usage......................................................................................................................178
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8.2.1.3 Internal reference clock (ICSIRCLK)............................................................................................178
8.2.1.4 Fixed frequency clock (ICSFFCLK)..............................................................................................179
8.2.1.5 BDC clock......................................................................................................................................180
8.2.2 Modes of operation.......................................................................................................................................... 180
8.2.2.1 FLL engaged internal (FEI)........................................................................................................... 181
8.2.2.2 FLL engaged external (FEE)..........................................................................................................182
8.2.2.3 FLL bypassed internal (FBI)..........................................................................................................182
8.2.2.4 FLL bypassed internal low power (FBILP)................................................................................... 182
8.2.2.5 FLL bypassed external (FBE)........................................................................................................183
8.2.2.6 FLL bypassed external low power (FBELP)................................................................................. 183
8.2.2.7 Stop (STOP)...................................................................................................................................184
8.2.3 FLL lock and clock monitor.............................................................................................................................185
8.2.3.1 FLL clock lock...............................................................................................................................185
8.2.3.2 External reference clock monitor...................................................................................................185
8.3 Initialization / application information........................................................................................................................... 185
8.3.1 Initializing FEI mode....................................................................................................................................... 186
8.3.2 Initializing FBI mode.......................................................................................................................................186
8.3.3 Initializing FEE mode...................................................................................................................................... 186
8.3.4 Initializing FBE mode......................................................................................................................................187
8.3.5 External oscillator (OSC).................................................................................................................................187
8.3.5.1 Bypass mode.................................................................................................................................. 188
8.3.5.2 Low-power configuration.............................................................................................................. 188
8.3.5.3 High-gain configuration.................................................................................................................189
8.3.5.4 Initializing external oscillator for peripherals................................................................................189
8.4 1 kHz low-power oscillator (LPO)................................................................................................................................. 190
8.5 Peripheral clock gating................................................................................................................................................... 190
8.6 ICS control registers....................................................................................................................................................... 190
8.6.1 ICS Control Register 1 (ICS_C1).................................................................................................................... 191
8.6.2 ICS Control Register 2 (ICS_C2).................................................................................................................... 192
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8.6.3 ICS Control Register 3 (ICS_C3).................................................................................................................... 193
8.6.4 ICS Control Register 4 (ICS_C4).................................................................................................................... 193
8.6.5 ICS Status Register (ICS_S)............................................................................................................................ 194
8.6.6 OSC Status and Control Register (ICS_OSCSC)............................................................................................ 195
8.7 System clock gating control registers............................................................................................................................. 196
8.7.1 System Clock Gating Control 1 Register (SCG_C1).......................................................................................197
8.7.2 System Clock Gating Control 2 Register (SCG_C2).......................................................................................198
8.7.3 System Clock Gating Control 3 Register (SCG_C3).......................................................................................199
8.7.4 System Clock Gating Control 4 Register (SCG_C4).......................................................................................200
Chapter 9
Chip configurations
9.1 Introduction.....................................................................................................................................................................203
9.2 Core modules.................................................................................................................................................................. 203
9.2.1 Central processor unit (CPU)...........................................................................................................................203
9.2.2 Debug module (DBG)......................................................................................................................................203
9.3 System modules.............................................................................................................................................................. 204
9.3.1 Watchdog (WDOG)......................................................................................................................................... 204
9.4 Clock module..................................................................................................................................................................204
9.5 Memory...........................................................................................................................................................................206
9.5.1 Random-access-memory (RAM)..................................................................................................................... 206
9.5.2 Non-volatile memory (NVM).......................................................................................................................... 206
9.6 Power modules................................................................................................................................................................206
9.7 Security........................................................................................................................................................................... 207
9.7.1 Cyclic redundancy check (CRC)......................................................................................................................207
9.8 Timers............................................................................................................................................................................. 209
9.8.1 FlexTimer module (FTM)................................................................................................................................209
9.8.1.1 FTM0 interconnection....................................................................................................................210
9.8.1.2 FTM2 interconnection....................................................................................................................211
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9.8.2 8-bit modulo timer (MTIM).............................................................................................................................211
9.8.2.1 MTIM0 as ADC hardware trigger................................................................................................. 212
9.8.3 Real-time counter (RTC)................................................................................................................................. 213
9.9 Communication interfaces.............................................................................................................................................. 215
9.9.1 Serial communications interface (SCI)............................................................................................................215
9.9.1.1 SCI0 infrared functions..................................................................................................................217
9.9.2 8-Bit Serial Peripheral Interface (8-bit SPI).................................................................................................... 218
9.9.3 Inter-Integrated Circuit (I2C)...........................................................................................................................219
9.10 Analog.............................................................................................................................................................................221
9.10.1 Analog-to-digital converter (ADC)..................................................................................................................221
9.10.1.1 ADC channel assignments............................................................................................................. 222
9.10.1.2 Alternate clock............................................................................................................................... 223
9.10.1.3 Hardware trigger............................................................................................................................ 223
9.10.1.4 Temperature sensor........................................................................................................................223
9.10.2 Analog comparator (ACMP)............................................................................................................................224
9.10.2.1 ACMP configuration information..................................................................................................225
9.10.2.2 ACMP in stop3 mode.....................................................................................................................226
9.10.2.3 ACMP for SCI0 RXD filter........................................................................................................... 226
9.11 Human-machine interfaces HMI.....................................................................................................................................226
9.11.1 Keyboard interrupts (KBI)...............................................................................................................................226
Chapter 10
Central processor unit
10.1 Introduction.....................................................................................................................................................................229
10.1.1 Features............................................................................................................................................................ 229
10.2 Programmer's Model and CPU Registers....................................................................................................................... 230
10.2.1 Accumulator (A).............................................................................................................................................. 230
10.2.2 Index Register (H:X)........................................................................................................................................231
10.2.3 Stack Pointer (SP)............................................................................................................................................ 231
10.2.4 Program Counter (PC)..................................................................................................................................... 232
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10.2.5 Condition Code Register (CCR)...................................................................................................................... 232
10.3 Addressing Modes.......................................................................................................................................................... 233
10.3.1 Inherent Addressing Mode (INH)....................................................................................................................234
10.3.2 Relative Addressing Mode (REL)....................................................................................................................234
10.3.3 Immediate Addressing Mode (IMM)...............................................................................................................234
10.3.4 Direct Addressing Mode (DIR)........................................................................................................................235
10.3.5 Extended Addressing Mode (EXT)..................................................................................................................235
10.3.6 Indexed Addressing Mode............................................................................................................................... 236
10.3.6.1 Indexed, No Offset (IX).................................................................................................................236
10.3.6.2 Indexed, No Offset with Post Increment (IX+)..............................................................................236
10.3.6.3 Indexed, 8-Bit Offset (IX1)............................................................................................................236
10.3.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+)........................................................................ 237
10.3.6.5 Indexed, 16-Bit Offset (IX2)..........................................................................................................237
10.3.6.6 SP-Relative, 8-Bit Offset (SP1)..................................................................................................... 237
10.3.6.7 SP-Relative, 16-Bit Offset (SP2)................................................................................................... 238
10.3.7 Memory to memory Addressing Mode............................................................................................................238
10.3.7.1 Direct to Direct...............................................................................................................................238
10.3.7.2 Immediate to Direct....................................................................................................................... 238
10.3.7.3 Indexed to Direct, Post Increment..................................................................................................238
10.3.7.4 Direct to Indexed, Post-Increment................................................................................................. 239
10.4 Operation modes............................................................................................................................................................. 239
10.4.1 Stop mode........................................................................................................................................................ 239
10.4.2 Wait mode........................................................................................................................................................239
10.4.3 Background mode............................................................................................................................................ 240
10.4.4 Security mode.................................................................................................................................................. 241
10.5 HCS08 V6 Opcodes........................................................................................................................................................243
10.6 Special Operations.......................................................................................................................................................... 243
10.6.1 Reset Sequence................................................................................................................................................ 243
10.6.2 Interrupt Sequence........................................................................................................................................... 243
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10.7 Instruction Set Summary.................................................................................................................................................244
Chapter 11
Keyboard Interrupts (KBI)
11.1 Introduction.....................................................................................................................................................................257
11.1.1 Features............................................................................................................................................................ 257
11.1.2 Modes of Operation......................................................................................................................................... 257
11.1.2.1 KBI in Wait mode..........................................................................................................................257
11.1.2.2 KBI in Stop modes.........................................................................................................................258
11.1.3 Block Diagram................................................................................................................................................. 258
11.2 External signals description............................................................................................................................................ 258
11.3 Register definition...........................................................................................................................................................259
11.4 Memory Map and Registers............................................................................................................................................259
11.4.1 KBI Status and Control Register (KBIx_SC).................................................................................................. 259
11.4.2 KBIx Pin Enable Register (KBIx_PE).............................................................................................................260
11.4.3 KBIx Edge Select Register (KBIx_ES)........................................................................................................... 261
11.5 Functional Description....................................................................................................................................................261
11.5.1 Edge-only sensitivity........................................................................................................................................261
11.5.2 Edge and level sensitivity................................................................................................................................ 262
11.5.3 KBI Pullup Resistor......................................................................................................................................... 262
11.5.4 KBI initialization..............................................................................................................................................262
Chapter 12
FlexTimer Module (FTM)
12.1 Introduction.....................................................................................................................................................................265
12.1.1 FlexTimer philosophy......................................................................................................................................265
12.1.2 Features............................................................................................................................................................ 266
12.1.3 Modes of operation.......................................................................................................................................... 267
12.1.4 Block diagram..................................................................................................................................................267
12.2 Signal description............................................................................................................................................................270
12.2.1 EXTCLK — FTM external clock.................................................................................................................... 270
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12.2.2 CHn — FTM channel (n) I/O pin.................................................................................................................... 270
12.2.3 FAULTj — FTM fault input............................................................................................................................270
12.3 Memory map and register definition...............................................................................................................................271
12.3.1 Module memory map.......................................................................................................................................271
12.3.2 Register descriptions........................................................................................................................................271
12.3.3 Status and Control (FTMx_SC)....................................................................................................................... 274
12.3.4 Counter High (FTMx_CNTH)......................................................................................................................... 275
12.3.5 Counter Low (FTMx_CNTL).......................................................................................................................... 276
12.3.6 Modulo High (FTMx_MODH)........................................................................................................................ 276
12.3.7 Modulo Low (FTMx_MODL)......................................................................................................................... 277
12.3.8 Channel Status and Control (FTMx_CnSC).................................................................................................... 277
12.3.9 Channel Value High (FTMx_CnVH)...............................................................................................................280
12.3.10 Channel Value Low (FTMx_CnVL)................................................................................................................281
12.3.11 Counter Initial Value High (FTMx_CNTINH)................................................................................................281
12.3.12 Counter Initial Value Low (FTMx_CNTINL).................................................................................................282
12.3.13 Capture and Compare Status (FTMx_STATUS).............................................................................................282
12.3.14 Features Mode Selection (FTMx_MODE)...................................................................................................... 284
12.3.15 Synchronization (FTMx_SYNC)..................................................................................................................... 285
12.3.16 Initial State for Channel Output (FTMx_OUTINIT)....................................................................................... 287
12.3.17 Output Mask (FTMx_OUTMASK)................................................................................................................. 289
12.3.18 Function for Linked Channels (FTMx_COMBINEn)..................................................................................... 290
12.3.19 Deadtime Insertion Control (FTMx_DEADTIME)......................................................................................... 292
12.3.20 External Trigger (FTMx_EXTTRIG).............................................................................................................. 293
12.3.21 Channels Polarity (FTMx_POL)......................................................................................................................294
12.3.22 Fault Mode Status (FTMx_FMS).....................................................................................................................296
12.3.23 Input Capture Filter Control (FTMx_FILTERn)............................................................................................. 297
12.3.24 Fault Input Filter Control (FTMx_FLTFILTER).............................................................................................298
12.3.25 Fault Input Control (FTMx_FLTCTRL)..........................................................................................................299
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12.4 Functional Description....................................................................................................................................................300
12.4.1 Clock Source....................................................................................................................................................301
12.4.1.1 Counter Clock Source.................................................................................................................... 301
12.4.2 Prescaler...........................................................................................................................................................302
12.4.3 Counter.............................................................................................................................................................302
12.4.3.1 Up counting....................................................................................................................................302
12.4.3.2 Up-down counting..........................................................................................................................305
12.4.3.3 Free running counter...................................................................................................................... 306
12.4.3.4 Counter reset.................................................................................................................................. 307
12.4.4 Input capture mode...........................................................................................................................................307
12.4.4.1 Filter for input capture mode......................................................................................................... 308
12.4.5 Output compare mode......................................................................................................................................309
12.4.6 Edge-aligned PWM (EPWM) mode................................................................................................................ 311
12.4.7 Center-aligned PWM (CPWM) mode..............................................................................................................313
12.4.8 Combine mode................................................................................................................................................. 315
12.4.8.1 Asymmetrical PWM...................................................................................................................... 322
12.4.9 Complementary mode......................................................................................................................................322
12.4.10 Update of the registers with write buffers........................................................................................................323
12.4.10.1 CNTINH:L registers...................................................................................................................... 323
12.4.10.2 MODH:L registers......................................................................................................................... 323
12.4.10.3 CnVH:L registers........................................................................................................................... 324
12.4.11 PWM synchronization......................................................................................................................................325
12.4.11.1 Hardware trigger............................................................................................................................ 325
12.4.11.2 Software trigger..............................................................................................................................326
12.4.11.3 Boundary cycle.............................................................................................................................. 327
12.4.11.4 MODH:L registers synchronization...............................................................................................328
12.4.11.5 CnVH:L registers synchronization.................................................................................................330
12.4.11.6 OUTMASK register synchronization............................................................................................ 330
12.4.11.7 FTM counter synchronization........................................................................................................332
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12.4.11.8 Summary of PWM synchronization...............................................................................................334
12.4.12 Deadtime insertion........................................................................................................................................... 336
12.4.12.1 Deadtime insertion corner cases.................................................................................................... 337
12.4.13 Output mask..................................................................................................................................................... 338
12.4.14 Fault control..................................................................................................................................................... 339
12.4.14.1 Automatic fault clearing.................................................................................................................341
12.4.14.2 Manual fault clearing..................................................................................................................... 342
12.4.15 Polarity control.................................................................................................................................................343
12.4.16 Initialization..................................................................................................................................................... 343
12.4.17 Features priority............................................................................................................................................... 344
12.4.18 Channel trigger output..................................................................................................................................... 344
12.4.19 Initialization trigger..........................................................................................................................................345
12.4.20 Capture test mode.............................................................................................................................................347
12.4.21 Dual edge capture mode...................................................................................................................................348
12.4.21.1 One-shot capture mode.................................................................................................................. 350
12.4.21.2 Continuous capture mode...............................................................................................................350
12.4.21.3 Pulse width measurement...............................................................................................................351
12.4.21.4 Period measurement.......................................................................................................................353
12.4.21.5 Read coherency mechanism...........................................................................................................355
12.4.22 TPM emulation................................................................................................................................................ 357
12.4.22.1 MODH:L and CnVH:L synchronization........................................................................................357
12.4.22.2 Free running counter...................................................................................................................... 357
12.4.22.3 Write to SC.....................................................................................................................................357
12.4.22.4 Write to CnSC................................................................................................................................357
12.4.23 BDM mode.......................................................................................................................................................357
12.5 Reset overview................................................................................................................................................................358
12.6 FTM Interrupts................................................................................................................................................................360
12.6.1 Timer overflow interrupt..................................................................................................................................360
12.6.2 Channel (n) interrupt........................................................................................................................................360
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Section number Title Page
12.6.3 Fault interrupt...................................................................................................................................................360
Chapter 13
8-bit modulo timer (MTIM)
13.1 Introduction.....................................................................................................................................................................361
13.2 Features...........................................................................................................................................................................361
13.3 Modes of operation......................................................................................................................................................... 361
13.3.1 MTIM in wait mode.........................................................................................................................................362
13.3.2 MTIM in stop mode......................................................................................................................................... 362
13.3.3 MTIM in active background mode.................................................................................................................. 362
13.4 Block diagram.................................................................................................................................................................362
13.5 External signal description..............................................................................................................................................363
13.6 Register definition...........................................................................................................................................................363
13.6.1 MTIM Status and Control Register (MTIMx_SC).......................................................................................... 363
13.6.2 MTIM Clock Configuration Register (MTIMx_CLK).................................................................................... 364
13.6.3 MTIM Counter Register (MTIMx_CNT)........................................................................................................ 365
13.6.4 MTIM Modulo Register (MTIMx_MOD)....................................................................................................... 366
13.7 Functional description.....................................................................................................................................................366
13.7.1 MTIM operation example................................................................................................................................ 367
Chapter 14
Real-time counter (RTC)
14.1 Introduction.....................................................................................................................................................................369
14.2 Features...........................................................................................................................................................................369
14.2.1 Modes of operation.......................................................................................................................................... 369
14.2.1.1 Wait mode......................................................................................................................................369
14.2.1.2 Stop modes.....................................................................................................................................370
14.2.2 Block diagram..................................................................................................................................................370
14.3 External signal description..............................................................................................................................................370
14.4 Register definition...........................................................................................................................................................371
14.4.1 RTC Status and Control Register 1 (RTC_SC1)............................................................................................. 371
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Section number Title Page
14.4.2 RTC Status and Control Register 2 (RTC_SC2)............................................................................................. 372
14.4.3 RTC Modulo Register: High (RTC_MODH).................................................................................................. 373
14.4.4 RTC Modulo Register: Low (RTC_MODL)................................................................................................... 373
14.4.5 RTC Counter Register: High (RTC_CNTH)................................................................................................... 374
14.4.6 RTC Counter Register: Low (RTC_CNTL).................................................................................................... 374
14.5 Functional description.....................................................................................................................................................375
14.5.1 RTC operation example................................................................................................................................... 376
14.6 Initialization/application information............................................................................................................................. 377
Chapter 15
Serial communications interface (SCI)
15.1 Introduction.....................................................................................................................................................................379
15.1.1 Features............................................................................................................................................................ 379
15.1.2 Modes of operation.......................................................................................................................................... 379
15.1.3 Block diagram..................................................................................................................................................380
15.2 SCI signal descriptions................................................................................................................................................... 382
15.2.1 Detailed signal descriptions............................................................................................................................. 382
15.3 Register definition...........................................................................................................................................................382
15.3.1 SCI Baud Rate Register: High (SCIx_BDH)................................................................................................... 383
15.3.2 SCI Baud Rate Register: Low (SCIx_BDL).................................................................................................... 384
15.3.3 SCI Control Register 1 (SCIx_C1)...................................................................................................................385
15.3.4 SCI Control Register 2 (SCIx_C2)...................................................................................................................386
15.3.5 SCI Status Register 1 (SCIx_S1)..................................................................................................................... 387
15.3.6 SCI Status Register 2 (SCIx_S2)..................................................................................................................... 389
15.3.7 SCI Control Register 3 (SCIx_C3)...................................................................................................................391
15.3.8 SCI Data Register (SCIx_D)............................................................................................................................392
15.4 Functional description.....................................................................................................................................................393
15.4.1 Baud rate generation........................................................................................................................................ 393
15.4.2 Transmitter functional description...................................................................................................................394
15.4.2.1 Send break and queued idle........................................................................................................... 394
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15.4.3 Receiver functional description....................................................................................................................... 395
15.4.3.1 Data sampling technique................................................................................................................396
15.4.3.2 Receiver wake-up operation...........................................................................................................397
15.4.4 Interrupts and status flags................................................................................................................................ 398
15.4.5 Baud rate tolerance...........................................................................................................................................399
15.4.5.1 Slow data tolerance........................................................................................................................ 400
15.4.5.2 Fast data tolerance..........................................................................................................................401
15.4.6 Additional SCI functions................................................................................................................................. 402
15.4.6.1 8- and 9-bit data modes..................................................................................................................402
15.4.6.2 Stop mode operation...................................................................................................................... 402
15.4.6.3 Loop mode..................................................................................................................................... 403
15.4.6.4 Single-wire operation.....................................................................................................................403
Chapter 16
8-Bit Serial Peripheral Interface (8-Bit SPI)
16.1 Introduction.....................................................................................................................................................................405
16.1.1 Features............................................................................................................................................................ 405
16.1.2 Modes of operation.......................................................................................................................................... 406
16.1.3 Block diagrams................................................................................................................................................ 407
16.1.3.1 SPI system block diagram..............................................................................................................407
16.1.3.2 SPI module block diagram.............................................................................................................407
16.2 External signal description..............................................................................................................................................409
16.2.1 SPSCK — SPI Serial Clock.............................................................................................................................409
16.2.2 MOSI — Master Data Out, Slave Data In....................................................................................................... 410
16.2.3 MISO — Master Data In, Slave Data Out....................................................................................................... 410
16.2.4 SS — Slave Select............................................................................................................................................410
16.3 Memory map/register definition..................................................................................................................................... 411
16.3.1 SPI Control Register 1 (SPIx_C1)................................................................................................................... 411
16.3.2 SPI Control Register 2 (SPIx_C2)................................................................................................................... 413
16.3.3 SPI Baud Rate Register (SPIx_BR)................................................................................................................. 414
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16.3.4 SPI Status Register (SPIx_S)........................................................................................................................... 415
16.3.5 SPI Data Register (SPIx_D).............................................................................................................................416
16.3.6 SPI Match Register (SPIx_M)..........................................................................................................................417
16.4 Functional description.....................................................................................................................................................417
16.4.1 General.............................................................................................................................................................417
16.4.2 Master mode.....................................................................................................................................................418
16.4.3 Slave mode.......................................................................................................................................................419
16.4.4 SPI clock formats.............................................................................................................................................421
16.4.5 SPI baud rate generation.................................................................................................................................. 424
16.4.6 Special features................................................................................................................................................ 424
16.4.6.1 SS Output....................................................................................................................................... 424
16.4.6.2 Bidirectional mode (MOMI or SISO)............................................................................................425
16.4.7 Error conditions................................................................................................................................................426
16.4.7.1 Mode fault error............................................................................................................................. 426
16.4.8 Low-power mode options................................................................................................................................ 427
16.4.8.1 SPI in Run mode............................................................................................................................ 427
16.4.8.2 SPI in Wait mode........................................................................................................................... 427
16.4.8.3 SPI in Stop mode............................................................................................................................428
16.4.9 Reset.................................................................................................................................................................428
16.4.10 Interrupts.......................................................................................................................................................... 429
16.4.10.1 MODF............................................................................................................................................ 429
16.4.10.2 SPRF.............................................................................................................................................. 429
16.4.10.3 SPTEF............................................................................................................................................ 430
16.4.10.4 SPMF............................................................................................................................................. 430
16.5 Initialization/application information............................................................................................................................. 430
16.5.1 Initialization sequence......................................................................................................................................430
16.5.2 Pseudo-Code Example..................................................................................................................................... 431
MC9S08PA16 Reference Manual, Rev. 2, 08/2014
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