AKM AK5572EN Evaluation Board Manual

[AKD55X4-B]

<KM119203> 2020/10

GENERAL DESCRIPTION

The AKD55X4-B is an evaluation board for AK55X4/X2, which is 32bit, 8k – 768kHz, 4ch/2ch ADC.

4ch ADC (AK55X4): AK5534, AK5554, AK5574

2ch ADC (AK55X2): AK5552, AK5572

The AKD55X4-B has the analog input circuit and a digital audio interface transmitter (DIT). In addition,

the regulators and crystal oscillator on the board generate the necessary power and clock for the ICs.

The AKD55X4-B can be easily connected to your audio system.

 Ordering guide

AKD55X4-B -- Evaluation board for AK55X4/X2

(A USB I/F BOX and control software for Windows 10 computer are included in this package.)

Features

 Onboard Voltage Regulators: Operate only with 15V power supplies.

 Onboard System Clocks: No clock source is required.

fs=48kHz, 96kHz, 192kHz are available.

 Analog Input: Differential input (CANNON) or Single-ended input (BNC)

 Digital Output: PCM, DSD (Header pins) and digital audio interface (BNC and Optical)

 Operation Mode Setting: Register control and pin control are available.

(note: Default setting of the board is register control with I2C)

Input

Circuit

AK4118A

(DIT)

AK55X4

AK55X2

Regulators

AVDD

3.3

V

or

1.8V

BNC

(COAX)

I2C

or

SPI

Control Signals

Input

Circuit

BNC

(Single-ended)

Optical

1.8V

-15V +15V

TVDD VDD18

CANNON

(Differential)

MCLK, LRCK, BICK

10pin Header

DSD

Banana Jack

10pin Header

USB

I/F Box

PCM

AK55x4 only

Control

Signals

5

V

or

3.3V

Figure 1. AKD55X4/X2-B Block Diagram

* Circuit diagram and PCB layout are attached at the end of this manual.

AK

D55X4

-

B

AK55X4/X2 Evaluation Board Rev.2

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Evaluation Board Diagram

 Layout of Connectors and Switches

J

801

J

802

J

800

S

W6

04

S

W6

00

U

4

J

200

J

202

J

2

03

J

2

01

S

W6

03

S

W6

01

P

ORT5

00

T

1

T

2

J

805

J

804

T3

J

806

J

807

J

808

J

809

J

3

00

J

3

02

J

3

03

J

3

01

T4

T5

S

W602

J

4

00

P

ORT4

00

P

ORT6

02

P

OR

T601

PORT

600

J

6

00

SW

4

00

U

1

AKD55X4

-

B

AK55X4/X2

-

15V

VSS

+15V

VBIAS

AVDD

VC

C

TVD

D

VDD18

D3.

3V

J

6

0

1

J

6

0

2

OPT

COAX

JP705

JP70

0

-

704

AK4118A

Figure 2. Layout of Connectors and Switches

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 Overview of Connectors and Switches

(1) U1 (AK55X4/AK55X2)

32bit,8k - 768kHz,4ch/2ch A/D Converter.

(2) J200, J201, J300, J301 (Cannon connector)

Differential Analog Signal Input

(3) J202, J203, J302, J303 (BNC Connector)

Single-ended Analog Signal Input.

(4) J400 (BNC Connector)

Digital Audio Interface Coaxial Output.

(5) PORT400 (Optical Connector)

Digital Audio Interface Optical Output.

(6) J800, J801, J802, J804, J805, J806, J807, J808, J809 (Banana Jack)

Power Supply Input.

(7) PORT600 (Pin Header)

Clocks Input / Output and PCM data outputs (MCLK, BICK, LRCK, SDTO1, SDTO2).

(8) PORT601 (Pin Header)

TDM data input (TDMIN).

(9) PORT602 (Pin Header)

DSD data and clock output (DCLK, DSDOL1/R1, DSDOL2/R2).

(10)PORT500 (Pin Header)

I2C or 3w-serial signals input.

(11)U4 (AK4118A)

Generate system clocks. Convert A/D data as digital audio interface format.

(12)SW600 (Toggle Switch)

Set PDN of AK55X4/X2.

(13)SW601 (Toggle switch)

Set PDN of AK4118A.

(14)SW602, SW603, SW604 (DIP Switch)

Set pin logical level of AK55X4/X2 input pins.

(15)SW400 (DIP Switch)

Set input data format and output clock frequency of AK4118A.

(16)J600 (BNC Connector)

External Master Clock Input (MCLK).

(17)J601, J602 (BNC Connector)

General Purpose Clock Divider Input.

(18)T1, T2, T3, T4, T5

Regulator for power supply of AK55X4/X2, AK4118A, Logic Circuit.

T1: Regulated AVDD, VBIAS (5.0V/3.3V) from +15V.

T2: Regulated VCC1, VCC2 (5.0V) from +15V.

T3: Regulated TVDD (3.3V) from +5V.

T4: Regulated TVDD, VDD18 (1.8V) from +5V

T5: Regulated D33V (3.3V) from +5V.

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Board Setting

 Contents

[1] Power Supply Path Settings

[2] Clocks and Data Path Settings

[3] Control Mode Settings

[4] Analog Input Settings

[5] Slave Mode/Master Mode Setting

[6] AK4118A Settings

[7] AK55X4/X2 Setting Tables

[8] Start-up Sequence

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[1] Power Supply Path Settings

(1-1) Power Supply Banana Jacks

Name Color Voltage (Typ) Supply Destination Comments Default Usage

J800 +15V Green +15V Regulators and Op-amps Should always be connected. Supply +15V

J801 -15V Blue -15V Op-amps Should always be connected. Supply -15V

J804 AVDD Red

+5.0V or

+3.3V

AK55X4/X2 AVDD and

VREFH

Optional Input. Open

J805 VBIAS Red

+5.0V or

+3.3V

Source of Analog Input

Signal Common Level

Optional Input.

The signal common level

becomes VBIAS/2.

Open

J809 VCC Red +5.0V

Regulators for

AK55X4/X2 TVDD,

VDD18 and Peripheral

Logic IC

Optional Input. Open

J806 TVDD Orange

+1.8V or

+3.3V

AK55X4/X2 TVDD and

Peripheral Logic IC

Optional Input. Open

J807 VDD18 Orange +1.8V AK55X4/X2 VDD18 Optional Input. Open

J808 D3.3V Orange +3.3V Peripheral Logic IC Optional Input. Open

J802 VSS Black 0V Ground Should always be connected. Connect to GND

Table 1-1. Power Supply Banana Jacks

In the default settings of the board, the onboard regulators supply the power the AK55X4/X2 and peripheral ICs.

If you want to use external power supplies, set the jumpers as described on the next table.

(1-2) The Power Supply Source Selection

Name Function Setting

R807

R808

AVDD1 Select AVDD source.

R807=short, R808=open: Regulator output (default)

R807=open, R808=short: Jack input

R809

R810

VBIAS Select VBIAS source.

R809=short, R810=open: Regulator output (default)

R809=open, R810=short: Jack input

R811

R812

VCC1,

VCC2

Select VCC source.

R811=short, R812=open: Regulator output (default)

R811=open, R812=short: Jack input

JP800 TVDD-VSEL

Select regulator voltage for

TVDD.

JP800=3.3V: 3.3V regulator (default)

JP800=1.8V: 1.8V regulator

JP801 TVDD-SEL Select TVDD source.

JP801=REG: Regulator output (default)

JP801=JACK: Jack input

JP802 VDD18-SEL Select VDD18 source.

JP802=REG: Regulator output

JP802=JACK: Jack input

JP802=open: Internal LDO of AK55X4/X2 (default)

JP803 D33V-SEL

Select power supply source for

peripheral ICs.

JP803=REG: Regulator output (default)

JP803=JACK: Jack input

Table 1-2. Jumpers for Power Supply Setting

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When you want to operate the IO pins of AK55X4/X2 at 1.8V, turn off the internal LDO and supply 1.8V to TVDD pin

and VDD18 pin.

LDOE

SW604-1

LDO VDD18 pin Status

TVDD pin

Power Supply Voltage

L OFF External Power Supply Input 1.7 - 1.98V 1.7 - 1.98V

H ON LDO Power Output 3.0 - 3.6V default

Table 1-3. Internal LDO Setting (AK55X4/X2)

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[2] Clock and Data path settings

(2-1) Connecters for Clocks and Data

Name Function Default Status

PORT600 SDTO2 CH3 and CH4 A/D Data Output Output

SDTO1 CH1 and CH2 A/D Data Output Output

LRCK LRCK Input or Output Not connected anywhere

BICK BICK Input or Output Not connected anywhere

MCLK MCLK Input Not connected anywhere

PORT601 TDMIN_PORT TDMIN input Short to GND

PORT602 DSDOR2 CH4 DSD Data Output

Hi-Z

DSDOL2 CH3 DSD Data Output

Hi-Z

DSDOR1 CH2 DSD Data Output

Hi-Z

DSDOL1 CH1 DSD Data Output

Hi-Z

DCKL DCD Clock Output

Hi-Z

PORT400 TX-OPT Digital Audio Interface Output (Optical Connecter) No Signal

J400 TX-COAX Digital Audio Interface Output (BNC Connecter) Output

Table 2-1. Connecters for Clocks and Data

(2-2) Jumper Settings for Clocks and Data

Names Function Setting

JP400 TXDATA-SEL

Select output connector for the digital a

udio

interface TX data from AK4118A.

COAX: BNC (default)

OPT: Optical Connector

PORT605 BICK-SEL

Slave mode: Select clock source for BICK.

Master mode: Must be PORT.

DIT: AK4118A output (default)

PORT: Pin Header PORT600-BICK

GND: Connected to VSS

PORT606 LRCK-SEL

Slave mode: Select clock source for LRCK.

Master mode: Must be PORT.

DIT: AK4118A output (default)

PORT: Pin Header PORT600-LRCK

GND: Connected to VSS

PORT607 BICK-PHASE Select BICK polarity.

THR: Non-inverted (default)

INV: Inverted

PORT608 SDTO_SEL

Select A/D data channel inputting to

digital audio

interface transmitter (AK4118A).

SDTO1: SDTO1 pin, Channel 1 & 2 (default)

SDTO2: SDTO2 pin, Channel 3 & 4

PORT609 TDMI-SEL Select TDMIN input.

Open: No signal

Short: Pin Header PORT601-TDMIN (default)

PORT610 MCLK-SEL Select clock source for MCLK of AK55X4/X2.

DIT: AK4118A output (default)

PORT: Pin Header PORT600-MCLK input

EXT: External MCLK (J600 EXT-T) input.

GND: Connected to VSS

JP600 EXT-T Terminating External MCLK (BNC).

Open: Not terminate (default)

Short: Terminating with 51.

Table 2-2. Jumpers for clocks and data setting

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[3] Control Mode Setting

AK55X4/X2 can be controlled by pins or registers. The pin control mode is called parallel control mode in the

AK55X4/X2 datasheet. The register control mode is called serial control mode. The register access is made by

I2C bus or 3-wire serial bus. The setting method for each control mode is described below. The board default

setting is I2C bus mode. If you use parallel control mode or 3-wire serial control mode, change the DIP switch

and jumper settings.

I2C pin

SW604-6

PS pin

SW604-5

Control Mode

L L 3-wire Serial

L H 3-wire Serial

H L

I2C Bus

default

H H Parallel

Table 3-1. Control Mode Select (AK55X4/X2)

Names Function Setting

JP700 PS-SEL1 Select signal to CKS0/SDA/CDTI pin.

SDA/CDTI: Serila control data (default)

CKS0: CKS0 bit of SW603

JP701 PS-SEL2 Select signal to CKS1/CAD0-I2C/CSN pin.

CAD0-I2C/CSN: CAD0-I2C bit of SW602 or CSN signa

l of

3-wire serial bus. (default)

CKS1: CKS1 bit of SW603

JP702 PS-SEL3 Select signal to JP701 CAD0-I2C/CSN input.

CAD0-I2C: CAD0-I2C bit of SW602 (default)

CSN: CSN signal of 3-wire serial bus.

JP703 PS-SEL4 Select signal to CKS2/SCL/CCLK pin.

SCL/CCLK: Serila control clock (default)

CKS2: CKS2 bit of SW603

JP704 PS-SEL5 Select signal to CKS3/CAD1 pin.

CAD1: CAD1 bit of SW602. (default)

CKS3: CKS3 bit of SW603

JP705 PS-SEL6 Select signal to PS/CAD0-SPI pin.

PS: PS bit of SW604 (default)

CAD0-SPI: CAD0-SPI bit of SW602

Table 3-2. Jumper setting for control signal

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(3-1) I2C Bus Control Mode < default >

Switch and Jumper Settings

S

W

604

ON

1 2 3 4 5 6 7 8

L

H

LDOE

HPFE/DCKS

ODP

TDM0

TDM1

PS

I2C

DP

S

W

60

2

ON

1 2 3 4 5 6 7 8

L

H

TEST

CAD1

PW0

PW1

PW2

MSN

CAD0-SPI

CAD0-I2C

SW603

ON

1 2 3 4 5 6 7 8

L

H

CKS0

SD/PMOD

CKS1

CKS2

CKS3

DIF0/DSDSEL0

DIF1/DSDSEL1

SLOW/DCKB

a

nd

:

Switch Position

Set sub-address by CAD0-I2C bit and CAD1 bit.

Figure 3-1-1. Switch Settings for I2C Bus control mode

JP705

PS

CAD0-

SPI

JP700

CKS0

SDA/CDTI

JP701

CKS1

CAD0-

I2C/CSN

JP703

CKS2

SCL/CCLK

JP704

CKS

3

CAD1

JP702

CSN

CAD0-

I2C

Figure 3-1-2. Jumper Pin Settings for I2C Bus control mode

The default control mode for the board is I2C bus mode. Registers can be set using the included USB I/F BOX

and control software. Connect the flat cable from USB I/F BOX to PORT500. And connect USB I/F BOX to PC

by USB cable. In I2C bus mode, DIP switch settings except TEST, MSN, CAD0-I2C, CAD1, LDOE, PS and I2C

are invalid.

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(3-2) 3-wire Serial Bus Control Mode

Switch and Jumper Settings

S

W

604

ON

1 2 3 4 5 6 7 8

L

H

LDOE

HPFE/DCKS

ODP

TDM0

TDM1

PS

I2C

DP

S

W

60

2

ON

1 2 3 4 5 6 7 8

L

H

TEST

CAD1

PW0

PW1

PW2

MSN

CAD0-SPI

CAD0-I2C

ON

S

W

60

3

1 2 3 4 5 6 7 8

L

H

CKS0

SD/PMOD

CKS1

CKS2

CKS3

DIF0/DSDSEL0

DIF1/DSDSEL1

SLOW/DCKB

Set chip address by CAD0-SPI bit and CAD1 bit.

Figure 3-2-1. Switch Settings for 3-wire serial bus control mode

JP705

PS

CAD0-

SPI

JP700

CKS0

SDA/CDTI

JP701

CKS1

CAD0-

I2C/CSN

JP703

CKS2

SCL/CCLK

JP704

CKS

3

CAD1

JP702

CSN

CAD0-

I2C

Figure 3-2-2. Jumper Pin Settings for 3-wire serial bus control mode

The USB I/F BOX and control software don’t support 3-wire serial bus control mode. When controlling the board

by 3-wire serial bus, connect the CSN, CCLK and CDTI signals to header pins of PORT500.

Note) It seems that CSN, CCLK/SCL and CDTI/SDA are assigned to 10pin, 8pin and 6pin in the silk screen

printing on the board, but they are assigned to 9pin, 7pin and 5pin as shown in the figure below.

PORT500

CSN

1

CCLK/SCL

C

DTI/SDA

NC

GND

2

9

10

Silk Screen Print Actual Pin Assignment

Figure 3-2-3. The pin assignments of PORT500

In 3-wire serial bus mode, DIP switch settings except TEST, MSN, CAD0-SPI, CAD1, LDOE, PS and I2C are

invalid.

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(3-3) Parallel Control Mode

Switch and Jumper Settings

S

W

604

ON

1 2 3 4 5 6 7 8

L

H

LDOE

HPFE/DCKS

ODP

TDM0

TDM1

PS

I2C

DP

S

W

60

2

ON

1 2 3 4 5 6 7 8

L

H

TEST

CAD1

PW0

PW1

PW2

MSN

CAD0-SPI

CAD0-I2C

SW603

ON

1 2 3 4 5 6 7 8

L

H

CKS0

SD/PMOD

CKS1

CKS2

CKS3

DIF0/DSDSEL0

DIF1/DSDSEL1

SLOW/DCKB

Figure 3-3-1. Switch Settings for Parallel Control mode

JP705

PS

CAD0-

SPI

JP700

CKS0

SDA/CDTI

JP701

CKS1

CAD0-I2C/CSN

JP703

CKS

2

SCL/CCLK

JP704

CKS

3

CAD1

JP702

CSN

CAD0-

I2C

Figure 3-3-2. Jumper Pin Settings for Parallel Control mode

In parallel control mode, set the operation mode with the DIP switches. USB I/F BOX and control software are

not used.

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[4] Analog Signal Input Settings

(4-1) Differential Input

Differential signals can be connected to the cannon connectors. The table below shows the relationship

between channel number and connector number.

ADC AIN1 AIN2 AIN3 AIN4

AK55X4 J200 J201 J300 J301

AK55X2 J200 J201 - -

Table 4-1. Differential Analog Signal Input Cannon Connector

(4-2) Single-ended Input

Single-ended signals can be connected to the BNC connectors. The table below shows the relationship

between channel number and connector number.

ADC AIN1 AIN2 AIN3 AIN4

AK55X4 J202 J203 J302 J303

AK55X2 J202 J203 - -

Table 4-2. Single-ended Analog Signal Input BNC Connector

The single-ended input signal and its inverted signal are not connected to input nodes (Vin+, Vin-) in board

default setting. When inputting single-ended signal from the BNC connector, short the “open” lands (R240 -

R247, R340 - R347) with an OΩ resistors or lead wires.

4.7k

-

+

-

+

1

0

3.3k

620

-

+

10

620

Analog In

14.9Vpp

68µ

NJM5534

VA=+5V

VP=15V

4.7k

10µ

+

10k

0.1µ

Bias

VA+

2.8Vpp

VP+

VP-

Bias

1n

3.3k

1n

Bias

15n

68µ

Cannon

XLR

Vin-

Vin+

open

NJM5534

AK55X4/X2 AINn+

AK55X4/X2 AINn-

100p

open

3

2

1

BNC

Figure 4-2. Analog Input Circuit

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[5] Slave Mode/Master Mode Setting

(5-1) Slave Mode (Default)

The default setting for the board is slave mode. The MCLK, LRCK and BICK are supplied from AK4118A

(DIT) to AK55X4/X2.

S

W

60

2

ON

1 2 3 4 5 6 7 8

L

H

TEST

CAD1

PW0

PW1

PW2

MSN

CAD0-SPI

CAD0-I2C

PORT605

BICK-SEL

DIT

PORT

GND

PORT606

LRCK-SEL

DIT

PORT

GND

PORT610

MCLK-SEL

DIT

PORT

EXT

GND

Figure 5-1. Switch and Jumper Settings for Slave Mode

(5-2) Master Mode ( with output to PORT600 )

Set the DIP switch SW602-5 to “H” and select “PORT” in PORT605, PORT606 when using in master mode.

LRCK and BICK are output to PORT600 together with SDTO. Jumper PORT610 selects the MCLK input

connector. The “PORT” is the header pin PORT600 and the “EXT” is the BNC J600.

S

W

60

2

ON

1 2 3 4 5 6 7 8

L

H

TEST

CAD1

PW0

PW1

PW2

MSN

CAD0-SPI

CAD0-I2C

PORT605

BICK-SEL

DIT

PORT

GND

PORT606

LRCK-SEL

DIT

PORT

GND

PORT610

MCLK-SEL

DIT

PORT

EXT

GND

Figure 5-2. Switch and Jumper Settings for Master Mode

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[6] AK4118A settings

The onboard AK4118A converts A/D data to digital audio interface format. Select the data format with the DIP

switch SW400.

S

W

400

ON

1 2 3 4 5

L

H

DIF2

DIF

1

DIF

0

O

CKS1

OCKS0

Figure 6. SW400 Assignment (AK4118A)

(3-1). Setting for SW400 (Sets AK4118A (U4) audio format and master clock setting)

No. Switch Name Function default

1 DIF2 DIT input and output data format select H

2 DIF1 DIT input and output data format select L

3 DIF0 DIT input and output data format select H

4 OCKS1 System clocks frequency select H

5 OCKS0 System clocks frequency select L

Table 6-1. SW400 Setting (AK4118A)

Mode

DIF2

SW400_1

DIF1

SW400_2

DIF0

SW400_3

DAUX input

from AK55X4/X2

SDTO output

to COAX, OPT

LRCK BICK

Pol.

I/O

Freq.

I/O

0

L

24bit, Left

justified

16bit, Right justified

H/L

O

64fs

O

1

L

H

24bit, Left justified

18bit

, Ri

ght justified

H/L

O

64fs

O

2

L

H

L

24bit, Left j

ust

ified

2

0b

i

t, Right justified

H/L

O

64fs

O

3

L

H

24bit,

Left

justified

24bit, Right justified

H

/L

O

64fs

O

4

H

L

24bit, Lef

t justified

24bit, Left justified

H/L

O

64fs

O

5 H L H

24bit, I2S 24bit, I2S

L/H O 64fs O

default

6

H

L

24bit, Left justi

fie

d

24bit

,

L

eft justified

H/L

I

64

-

128fs

I

7 H H H

24bit,

I2S

24bit,

I2S

L/H I 64-128fs I

Table 6-2. Audio format (AK4118A)

In the default settings of the board, the AK4118A generate the system clocks (MCLK, LRCK and BICK) and

supply them to AK55X4/X2. The AK4118A supports up to fs=192kHz.

OCKS1

SW400_4

OCKS0

SW400_5

X’tal

(24.576MHz)

MCKO1 MCKO2

Sampling freq.

fs

L L 256fs 256fs 256fs 96 kHz

L H 256fs 256fs 128fs 96 kHz

H L 512fs 512fs 256fs 48 kHz default

H H 128fs 128fs 64fs 192 kHz

Table 6-3. Output Clock Frequency (AK4118A)

If you want higher fs than 192kHz, connect external clocks to pin headers or connecters and set the jumpers.

See the Table 2-2.

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[7] AK55X4/X2 setting tables

(7-1) Serial Control mode (I2C bus)

The AK55X4/X2 operation modes are set by the control software in I2C control mode.

Figure 7-1. Control Software Main Window (AK55X4)

Register data is indicated on the register map. Each bit on the register map is a push-button switch. Button DOWN with

red lettering indicates “1” and button UP with blue lettering indicates “0”. Buttons with “---“ are undefined in the

datasheet.

 PW4-1: Power Down control for channel 4-1 (PW2-1 for AK55X2)

0: Power OFF

1: Power ON (default)

 RSTN: Internal Timing Reset

0: Reset. All registers are not initialized.

1: Normal Operation (default)

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 MONO2-1: Channel Summation Select

MONO2

bit

MONO1

bit

Data

on Slot

Slot 4

Slot 3

Slot 2

Slot 1

0

CH4

CH3

CH2

CH1

0

1

All

“0”

or TDMI

All “0”

or TDMI

(CH3+4)/2

(CH1+2)/2

1

0

CH4

CH3

CH2

CH1

1

All “0”

or TDMI

All “0”

or TDMI

All “0”

or TDMI

(CH1+2+3+4)/4

Figure 7-1-1. Slot Data Assign (AK55X4)

MONO2

bit

MONO1

bit

Data on Slot

Slot 2

Slot 1

0

CH2

CH1

0

1

(CH1+2)/

2

(CH1+2)/2

1

0

CH2

CH1

1

All “0”

(CH1+2)/2

Figure 7-1-2. Slot Data Assign (AK55X2)

 HPFE: High Pass Filter Enable

0: High Pass Filter OFF

1: High Pass Filter ON (default)

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<KM119203> 2020/10

 DIF1-0: Audio Data Interface Modes Select (default = 00b)

 TDM1-0: TDM Modes Select (default = 00b)

The format of AK4118A is I2S at the default of the board. When using DIT output, set DIF1-0 bits to "01b".

*: Don’t Care

No.

Multiplex

Mode

Speed

Mode

TDM1

bit

TDM0

bit

MSN

SW602-5

DIF1

bit

DIF0

bit

SDTO

LRCK

BICK

MCLK

Pol.

I/O

Freq.

I/O

Freq.

I/O

0

Normal

Double

Quad

0 0

L

0

24-bit, MSB ↑ I 48-128fs I 128-1024fs I

1

0

1

24-bit, I2S ↓ I 48-128fs I 128-1024fs I

2

1

0

32-bit, MSB ↑ I 64-128fs I 128-1024fs I

3

1

32-bit, I2S ↓ I 64-128fs I 128-1024fs I

4

H

0

24-bit, MSB ↑ O 64fs O 128-1024fs I

5

0

1

24-bit, I2S ↓ O 64fs O 128-1024fs I

6

1

0

32-bit, MSB ↑ O 64fs O 128-1024fs I

7

1

32-bit, I2S ↓ O 64fs O 128-1024fs I

8

OCT

HEX

0 0

L

*

0

16-bit, MSB ↑ I 32fs I 32-96fs I

9

*

1

16-bit, I2S ↓ I 32fs I 32-96fs I

10

*

0

24-bit, MSB ↑ I 48fs I 32-96fs I

11

*

1

24-bit, I2S ↓ I 48fs I 32-96fs I

12

0

24-bit, MSB ↑ O 64fs O 32-96fs I

13

0

1

24-bit, I2S ↓ O 64fs O 32-96fs I

14

1

0

32-bit, MSB ↑ O 64fs O 32-96fs I

15

1

32-bit, I2S ↓ O 64fs O 32-96fs I

16

H

*

0

16-bit, MSB ↑ I 32fs I 32fs I

17

*

1

16-bit, I2S ↓ I 32fs I 32fs I

18

*

0

24-bit, MSB ↑ I 48fs I 48fs I

19

*

1

24-bit, I2S ↓ I 48fs I 48fs I

20

0

24-bit, MSB ↑ O 64fs O 64fs I

21

0

1

24-bit, I2S ↓ O 64fs O 64fs I

22

1

0

32-bit, MSB ↑ O 64fs O 64fs I

23

1

32-bit, I2S ↓ O 64fs O 64fs I

24

TDM128

Normal

Double

Quad

0 1

L

0

24-bit, MSB



I 128fs I 128-1024fs I

25

0

1

24-bit, I2S



I 128fs I 128-1024fs I

26

1

0

32-bit, MSB



I 128fs I 128-1024fs I

27

1

32-bit, I2S



I 128fs I 128-1024fs I

28

H

0

24-bit, MSB



O 128fs O 128-1024fs I

29

0

1

24-bit, I2S



O 128fs O 128-1024fs I

30

1

0

32-bit, MSB



O 128fs O 128-1024fs I

31

1

32-bit, I2S



O 128fs O 128-1024fs I

32

TDM256

Normal

Double

1 0

L

0

24-bit, MSB



I 256fs I 256-1024fs I

33

0

1

24-bit, I2S



I 256fs I 256-1024fs I

34

1

0

32-bit, MSB



I 256fs I 256-1024fs I

35

1

32-bit, I2S



I 256fs I 256-1024fs I

36

H

0

24-bit, MSB



O 256fs O 256-1024fs I

37

0

1

24-bit, I2S



O 256fs O 256-1024fs I

38

1

0

32-

bit, MSB



O 256fs O 256-1024fs I

39

1

32-bit, I2S



O 256fs O 256-1024fs I

40

TDM512 Normal

1 1

L

0

24-bit, MSB



I 512fs I 512-1024fs I

41

0

1

24-bit, I2S



I 512fs I 512-1024fs I

42

1

0

32-bit, MSB



I 512fs I 512-1024fs I

43

1

32-bit, I2S



I 512fs I 512-1024fs I

44

H

0

24-bit, MSB



O 512fs O 512-1024fs I

45

0

1

24-bit, I2S



O 512fs O 512-1024fs I

46

1

0

32-bit, MSB



O 512fs O 512-1024fs I

47

1

32-bit, I2S



O 512fs O 512-1024fs I

Table 7-1-3. Data Interface mode setting

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 CKS3-0: Sampling Speed Mode and MCLK Frequency Select

In default setting for the board, AK4118A supplies LRCK and MCLK to AK55X4/X2. The LRCK (fs) is 48kHz

and the MCLK is 512fs. When using the board in default settings, set CKS3-0 bits to "0000b".

CKS3

bit

CKS2

b

it

CKS1

b

it

CKS0

b

it

M

S

N

p

in

S

W

6

0

2

-

5

MCLK

Frequency

fs Range

0 0 0 0

L

128fs

Q

uad Speed Mode

108

k

Hz



fs



216

k

Hz

d

efaul

t

H

0 0 0 1

L

192fs

Q

uad Speed Mode

1

08

k

H

z



fs



216

k

Hz

H

0 0 1 0

L

256fs

N

ormal Speed

M

ode

8

k

Hz



fs



54

k

Hz

H

0 0 1 1

L

256fs

D

ouble Speed Mo

de

54

k

Hz



fs



108

k

Hz

H

0 1 0 0

L

384fs

D

ouble

Spe

ed Mode

54

k

Hz



fs



108

k

Hz

H

0 1 0 1

L

384fs

N

ormal

S

peed Mode

8

k

Hz



fs



54

k

Hz

H

0 1 1 0

L

512fs

N

ormal Sp

eed Mode

8

k

Hz



fs



54

k

Hz

H

0 1 1 1

L

768fs

N

ormal S

peed Mode

8

k

Hz



fs



54

k

Hz

H

1 0 0 0

L

64fs

O

ct Speed Mode

fs = 384kHz

H

1 0 0 1

L

32fs

H

ex Speed

Mode

fs = 768kHz

H

1 0 1 0

L

96fs

O

ct S

peed Mode

fs = 3

84kHz

H

1 0 1 1

L

48fs

H

ex Speed Mode

fs = 768kHz

H

1 1 0 0

L

64fs

H

ex Speed Mode

fs = 768kH

z

H

1 1 0 1

L

1024fs

N

o

rmal Speed Mode

8kH

z

≤

fs

≤

32kHz

H

1 1 1 0

L

NA NA

H

1 1 1 1

L

Auto

8

k

Hz



fs



216k

Hz

H

N

A

N

A

Table 7-1-4. Speed mode and MCLK Frequency setting

 SLOW: Slow Roll-off Filter Select

 SD: Short Delay Select

SD

bit

SLOW

bit

Filter Type

0 0 Sharp Roll-off Filter default

0 1 Slow Roll-off Filter

1 0 Short Delay Sharp Roll-off Filter

1 1 Short Delay Slow Roll-off Filter

Table 7-1-5. Digital Filter Select: PCM Mode

 DP: DSD Mode Select

0: PCM mode (default)

1: DSD mode

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 DSDSEL1-0: Select the Frequency of DCLK

DSDSEL1

bit

DSDSEL0

bit

Frequency

Mode

DSD Sampling Frequency

fs=32kHz fs=44.1kHz fs=48kHz

0 0 64fs 2.048MHz 2.8224MHz 3.072MHz default

0 1 128fs 4.096MHz 5.6448MHz 6.144MHz

1 0 256fs 8.192MHz 11.2896MHz 12.288MHz

1 1 - Reserved Reserved Reserved

Table 7-1-6. DSD Sampling Frequency Select

 DCKB: Polarity of DCLK

0: DSD data is output from DCLK Falling Edge (default)

1: DSD data is output from DCLK Rising Edge

 PMOD: DSD Phase Modulation Mode

0: Not Phase Modulation mode (default)

1: Phase Modulation mode

 DCKS: Master Clock Frequency Select at DSD mode

0: 512fs (default)

1: 768fs

 TST7-0: Test register.

Must be “0”

 TRST: Test register

Must be “0”

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<KM119203> 2020/10

(7-2) Parallel Control mode (DIP Switch)

The AK55X4/X2 operation modes are set by the DIP switches in parallel control mode.

SW603

ON

1 2 3 4 5 6 7 8

L

H

CKS0

SD/PMOD

SW604

ON

1 2 3 4 5 6 7 8

L

H

LDOE

HPFE/DCKS

ODP

TDM0

TDM1

PS

I2C

DP

CKS1

CKS2

CKS3

DIF0/DSDSEL0

DIF1/DSDSEL1

SLOW/DCKB

SW602

ON

1 2 3 4 5 6 7 8

L

H

TEST

CAD1

PW0

PW1

PW2

MSN

CAD0-SPI

CAD0-I2C

Figure 7-2. DIP Switches for AK55X4/X2 Operation Settings

No. Switch Name Function default

1 TEST TEST Enable. Must be “L”. L

2 PW0 Power and Summation mode setting. See Table 7-2-4. ~ Table 7-2-7. H

3 PW1 Power and Summation mode setting. See Table 7-2-4. ~ Table 7-2-7. H

4 PW2 Power and Summation mode setting. See Table 7-2-4. ~ Table 7-2-7. H

5 MSN

Master/Slave select.

L: Slave Mode

H: Master Mode

L

6 CAD0-SPI Chip Address0 Pin in 3-wire serial control mode. L

7 CAD0-I2C Chip Address0 Pin in I2C bus serial control mode. L

8 CAD1 Chip Address1 Pin in I2C bus or 3-wire serial control mode. L

Table 7-2-1. SW602 assignment

No. Switch Name Function default

1 CKS0 Clock Mode Setting #0 See Table 7-2-8. L

2 CKS1 Clock Mode Setting #1 See Table 7-2-8. H

3 CKS2 Clock Mode Setting #2 See Table 7-2-8. H

4 CKS3 Clock Mode Setting #3 See Table 7-2-8. L

5 DIF0/DSDSEL0

Audio Data Format select in PCM Mode See Table 7-2-9.

DSD Sampling Rate Control in DSD Mode See Table 7-2-10.

H

6 DIF1/DSDSEL1

DIF1: Audio Data Format select in PCM Mode See Table 7-2-9.

DSD Sampling Rate Control in DSD Mode See Table 7-2-10.

L

7 SLOW/DCKB

Slow Roll-OFF Digital Filter select in PCM Mode See Table 7-2-11.

Polarity of DCLK in DSD Mode

L: Not-Invert

H: Invert

L

8 SD/PMOD

Short Delay Digital Filter select in PCM Mode See Table 7-2-11.

DSD Phase Modulation Mode select in DSD Mode

L: Normal

H: Phase Modulation

L

Table 7-2-2. SW603 assignment

- 20-

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AKM AK5572EN Evaluation Board Manual

AKM AK5572EN Evaluation Board Manual

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