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Intel Triple-Speed User guide

  • Hello! I've analyzed the provided user guide for the Intel Agilex Triple-Speed Ethernet FPGA IP. This document gives you the necessary instructions to generate, simulate, and test design examples using this IP. I'm familiar with the steps for hardware testing, simulation and configuration. I'm ready to help you with any questions you might have about the document or the device.
  • What is the purpose of the Triple-Speed Ethernet Intel FPGA IP?
    Which Intel devices are compatible with this IP?
    Does the design example support internal FIFO?
    What kind of loopback modes are supported?
Triple-Speed Ethernet Intel Agilex
FPGA IP Design Example User Guide
Updated for Intel® Quartus® Prime Design Suite: 22.3
IP Version: 21.1.0
Online Version
Send Feedback
ID: 741330
Version: 2022.12.09
Contents
1. Quick Start Guide............................................................................................................ 3
1.1. Directory Structure................................................................................................ 3
1.2. Generating the Design Example...............................................................................5
1.2.1. Design Example Parameters........................................................................ 7
1.3. Simulating the Triple-Speed Ethernet Intel FPGA IP Design Example Testbench.............. 8
1.4. Compiling and Configuring the Design Example in Hardware........................................8
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII
PCS and Embedded PMA............................................................................................ 9
2.1. Features...............................................................................................................9
2.2. Hardware and Software Requirements...................................................................... 9
2.3. Functional Description.......................................................................................... 10
2.3.1. Design Components................................................................................. 11
2.3.2. Clock and Reset Signals............................................................................ 11
2.4. Simulation.......................................................................................................... 11
2.4.1. Testbench............................................................................................... 12
3. Document Revision History for the Triple-Speed Ethernet Intel FPGA IP Intel
Agilex Design Example User Guide.......................................................................... 14
Contents
Triple-Speed Ethernet Intel Agilex FPGA IP Design Example User Guide Send Feedback
2
1. Quick Start Guide
The Triple-Speed Ethernet Intel® FPGA IP for Intel Agilex™ provides the capability of
generating design examples for selected configurations, which allows you to:
• Compile the design to get an estimate of the IP area usage and timing.
• Simulate the design to verify the IP functionality through simulation.
• Test the design on the hardware using the Intel Agilex I-Series Transceiver-SoC
Development Kit.
When you generate a design example, the parameter editor automatically creates the
files necessary to simulate, compile, and test the design in hardware.
Note: Hardware support is currently not available in the Intel Quartus® Prime Pro Edition
Software version 22.3.
Figure 1. Development Stages for the Design Example
Design
Example
Generation
Compilation
(Simulator)
Functional
Simulation
Compilation
(Quartus Prime)
Hardware
Testing
Note: In Intel Quartus Prime Pro Edition Software version 22.3, a patch is required to avoid
simulation failure on the design example. For more information, refer to the KDB link:
Why does simulation fail for the Triple-Speed Ethernet Intel FPGA IP Multiport Design
Example?.
Related Information
Why does simulation fail for the Triple-Speed Ethernet Intel® FPGA IP Multiport Design
Example?
1.1. Directory Structure
The Triple-Speed Ethernet Intel FPGA IP design example file directories contain the
following generated files for the 10/100/1000 Multiport Ethernet MAC Design Example
with 1000BASE-X/SGMII PCS and Embedded PMA:
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Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel
Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Intel assumes no responsibility or liability arising out of the
application or use of any information, product, or service described herein except as expressly agreed to in
writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
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9001:2015
Registered
• The hardware configuration and test files (the hardware design example) are
located in <design_example_dir>/hardware_test_design.
• The simulation files (testbench for simulation only) are located in
<design_example_dir>/example_testbench.
•The compilation-only design example is located in <design_example_dir>/
compilation_test_design.
• The compilation test and hardware test designs use files in
<design_example_dir>/ex_tse/common.
Figure 2. Directory Structure for the Design Example
ex_tse
<supporting IP>
compilation_test_design
<supporting files>
altera_eth_tse.qpf
sim
ex_tse.ip
basic_avl_tb_top.v
<Simulation Script>
<Simulation Script>
example_testbench
<eth_tse_0_example_design>
synth
common
ex_tse.cmp
ex_tse.csv
ex_tse.html
ex_tse.qgsimc
ex_tse.qgsynthc
ex_tse.qip
ex_tse.sopcinfo
ex_tse.spd
ex_tse.xml
ex_tse.bb.v
ex_tse.generation.rpt
ex_tse.inst.v
ex_tse.inst.vhd
•
•altera_eth_tse.qsf
altera_eth_tse.srf
altera_eth_tse.v
hardware_test_design
common
hwtest
altera_eth_tse_hw.qpf
altera_eth_tse_hw.qsf
altera_eth_tse_hw.sdc
altera_eth_tse_hw.v
Table 1. Triple-Speed Ethernet Intel FPGA IP Testbench File Description
Directory/File Description
Testbench and Simulation Files
<design_example_dir>/example_testbench/
basic_avl_tb_top_mac_pcs.sv
Top-level testbench file. The testbench instantiates the DUT
and runs Verilog HDL tasks to generate and accept packets.
Testbench Scripts
<design_example_dir>/example_testbench/
run_vsim_mac_pcs.sh
The ModelSim script to run the testbench.
continued...
1. Quick Start Guide
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Triple-Speed Ethernet Intel Agilex FPGA IP Design Example User Guide Send Feedback
4
Directory/File Description
<design_example_dir>/example_testbench/
run_vcs_mac_pcs.sh
The Synopsys* VCS script to run the testbench.
<design_example_dir>/example_testbench/
run_vcsmx_mac_pcs.sh
The Synopsys VCS MX script (combined Verilog HDL and
System Verilog with VHDL) to run the testbench
<design_example_dir>/example_testbench/
run_xcelium_mac_pcs.sh
The Xcelium* script to run the testbench.
Table 2. Triple-Speed Ethernet Intel FPGA IP Hardware Design Example File
Description
Directory/File Description
<design_example_dir>/hardware_test_design/
altera_eth_tse_hw.qpf
Intel Quartus Prime project file.
<design_example_dir>/hardware_test_design/
altera_eth_tse_hw.qsf
Intel Quartus Prime project settings file.
<design_example_dir>/hardware_test_design/
altera_eth_tse_hw.sdc
Synopsys Design Constraints files. You can copy and modify
these files for your own Intel Stratix® 10 design.
<design_example_dir>/hardware_test_design/
altera_eth_tse_hw.v
Top-level Verilog HDL design example file.
<design_example_dir>/hardware_test_design/
common/
Hardware design example support files.
1.2. Generating the Design Example
Figure 3. Procedure to Generate Design Example
Start Parameter
Editor
Specify IP Variation
and Select Device
Select
Design Parameters
Initiate
Design Generation
Specify
Example Design
1. Quick Start Guide
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Send Feedback Triple-Speed Ethernet Intel Agilex FPGA IP Design Example User Guide
5
Figure 4. Example Design Tab in the Triple-Speed Ethernet Intel FPGA IP Parameter
Editor
Follow these steps to generate the hardware design example and testbench:
1. In the Intel Quartus Prime Pro Edition software, click File ➤ New Project Wizard
to create a new Quartus Prime project, or File ➤ Open Project to open an
existing Quartus Prime project. The wizard prompts you to specify a device.
2. Select Intel Agilex device family and select a device that has LVDS.
3. Click Finish to close the wizard.
4. In the IP Catalog, locate and select Interface Protocol ➤ Ethernet ➤ 1G Multi-
rate Ethernet ➤ Triple-Speed Ethernet Intel FPGA IP. The New IP
Variation window appears.
5. Specify a top-level name <your_ip> for your custom IP variation. The parameter
editor saves the IP variation settings in a file named <your_ip>.ip.
6. Click OK. The parameter editors appears.
7. To generate a design example, select a design example preset from the Presets
library and click Apply. When you select a design, the system automatically
populates the IP parameters for the design. The parameter editor automatically
sets the parameters required to generate the design example. Do not change the
preset parameters in the IP tab.
8. For Example Design Files, select the Simulation option to generate the
testbench, or the Synthesis option to generate the hardware design example.
Note: You must select at least one of the options to generate the design example.
9. On the Example Design tab, under Generated HDL Format, select Verilog
HDL or VHDL.
Note: If you select VHDL, you must simulate the testbench with a mixed language
simulator. The device under test is a VHDL model, but the main testbench
file is a System Verilog file.
1. Quick Start Guide
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Triple-Speed Ethernet Intel Agilex FPGA IP Design Example User Guide Send Feedback
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10. Under Target Development Kit, select the Agilex I-Series Transceiver-SoC
Development Kit (AGIB027R31B1E2VR0) or select None.
Note: a. If you select a specific development kit as the Target Development
Kit, the design example is generated based on the specific device and
overwrites the device you selected in your project file.
b. If you select None as the Target Development Kit, ensure that the
selected device is your targeted device and adjust the pins assignment
in the .qsf file. By default, the .qsf file is generated based on the
device used in the development kit.
11. Click the Example Design: “example_design” button. The Select Example
Design Directory window appears.
12. If you want to modify the design example directory path or name from the
defaults displayed (eth_tse_0_example_design), browse to the new path and type
the new design example directory name (<design_example_dir>).
Note: You must perform the parameter settings based on the steps above to
generate the design example.
13. Click OK.
1.2.1. Design Example Parameters
Table 3. Parameters in the Example Design Tab
Parameter Description
Select Design Available example designs for the IP parameter settings.
Example Design Files The files to generate for the different development phase.
• Simulation—generates the necessary files for simulating the example
design.
• Synthesis—generates the synthesis files. Use these files to compile
the design in the Intel Quartus Prime Pro Edition software for
hardware testing and perform static timing analysis.
Generate File Format The format of the RTL files for simulation—Verilog or VHDL.
Select Board Supported hardware for design implementation. When you select an
Intel FPGA development board, the Target Device is the one that
matches the device on the Development Kit.
If this menu is not available, there is no supported board for the options
that you select.
Agilex I-Series Transceiver-SoC Development Kit: This option
allows you to test the design example on the selected Intel FPGA IP
development kit. This option automatically selects the Target Device to
match the device on the Intel FPGA IP development kit. If your board
revision has a different device grade, you can change the target device.
None: This option excludes the hardware aspects for the design
example.
1. Quick Start Guide
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1.3. Simulating the Triple-Speed Ethernet Intel FPGA IP Design
Example Testbench
Figure 5. Procedure to Simulate Example Testbench
Change to
Testbench
Directory
Run
<Simulation Script>
Analyze
Results
Follow these steps to simulate the testbench:
1. Change to the testbench simulation directory <design_example_dir>/
example_testbench.
2. Run the simulation script for the supported simulator of your choice. The script
compiles and runs the testbench in the simulator. Refer to the table Steps to
Simulate the Testbench.
Table 4. Steps to Simulate the Testbench
Simulator Instructions
ModelSim* In the command line, type vsim -do run_vsim_mac_pcs.do. If you prefer to simulate
without bringing up the ModelSim GUI, type vsim -c -do run_vsim_mac_pcs.do.
Synopsys VCS*/ VCS MX In the command line, type sh run_vcs_mac_pcs.sh or sh run_vcsmx_mac_pcs.sh.
Xcelium In the command line, type sh run_xcelium_mac_pcs.sh.
3. Analyze the results. The successful testbench sends ten packets, receives the
same number of packets, and displays the following message:
End of Simulation - Break
1.4. Compiling and Configuring the Design Example in Hardware
To compile the hardware design example and configure it on your Intel Agilex device,
follow these steps:
1. Ensure hardware design example generation is complete.
2. In the Intel Quartus Prime Pro Edition software, open the Intel Quartus Prime
project <design_example_dir>/hardware_test_design/
altera_eth_tse_hw.qpf.
3. On the Processing menu, click Start Compilation.
4. After a successful compilation, a.sof file is available in
<design_example_dir>/hardwarde_test_design directory.
1. Quick Start Guide
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2. 10/100/1000 Multiport Ethernet MAC Design Example
with 1000BASE-X/SGMII PCS and Embedded PMA
This design example demonstrates an Ethernet solution for Intel Agilex devices using
the Triple-Speed Ethernet IP. You can generate the design from the Example Design
tab of the Triple-Speed Ethernet IP parameter editor.
To generate the design example, you must first set the parameter values for the IP
variation you intend to generate in your end product. Generating the design example
creates a copy of the IP. The testbench and hardware design example use the copy of
the IP as the device under test (DUT). If you do not set the parameter values for the
DUT to match the parameter values in your end product, the design example you
generate does not exercise the IP variation that you intend.
Note: 1. The testbench demonstrates a basic test of the IP. It is not intended to be a
substitute for a full verification environment. You must perform more extensive
verifications of your own Triple-Speed Ethernet design in simulation and in
hardware.
2.1. Features
• Generates the design example for Triple-Speed Ethernet Multiport Ethernet MAC
without Internal FIFO and PCS with LVDS I/O using multi-channel shared FIFO.
• Generates traffic at the transmit path and validates received data through the
transceiver LVDS I/O external loopback.
• Tx and RX serial external loopback mode through LVDS I/O.
• Supports only external loopback.
• Supports only four ports.
2.2. Hardware and Software Requirements
Intel uses the following hardware and software to test the design example in a Linux
system:
• Intel Quartus Prime Pro Edition software
• ModelSim, VCS, VCS MX, and Xcelium simulators
Note: Hardware support is currently not available in the Intel Quartus Prime Pro Edition
Software version 22.3.
741330 | 2022.12.09
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Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel
Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Intel assumes no responsibility or liability arising out of the
application or use of any information, product, or service described herein except as expressly agreed to in
writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered
2.3. Functional Description
Figure 6. Block Diagram—10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMI PCS
Port 0
data_tx_data_n
Avalon-ST
Multi-Channel
Shared
Memory FIFO
Client Logic
(Traffic
Controller)
Control
and Status
Interface
Jtag to
Avalon-MM
Address Decoder
System Console
Avalon-ST Tx
Triple Speed Ethernet Design Example
Intel® Agilex™ I-Series Transceiver SoC Development Kit
Avalon-ST Rx
Avalon-MM
rx_afull_clk
clk
8X4
tx_p_n
Triple Speed Ethernet Intel FPGA IP
Port 1
Port 2
Port 3
CSR Interface
ref_clk
reset_n
iopll_refclk
Multiport TSE MAC
without Internal FIFO
+
1000BASE-X/SGMII PCS
+
LVDS I/O
Control and Status Interface (CSR)
rx_p_n
data_rx_data_n
8X4
csr_clk
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and
Embedded PMA
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2.3.1. Design Components
Table 5. Design Components
Component Description
Triple-Speed Ethernet Intel
FPGA IP
The Triple-Speed Ethernet Intel FPGA IP (altera_eth_tse) is instantiated with the
following configuration:
• Core Configurations:
—Core Variation: 10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII PCS
—Use internal FIFO: Not selected
—Number of ports: 4
—Transceiver type: LVDS I/O
• MAC Options:
—Enable MAC 10/100 half duplex support: Selected
—Enable local loopback on MII/GMII: Selected
—Enable supplemental MAC unicast addresses: Not selected
—Include statistics counters: Selected
—Enable 64-bit statistics byte counters: Not selected
—Include multicast hashtable: Not selected
—Align packet headers to 32-bit boundary: Not selected
—Enable full-duplex flow control: Selected
—Enable VLAN detection: Not selected
—Enable magic packet detection: Selected
—Include MDIO module (MDC/MDIO): Selected
—Host clock divisor: 50
• Timestamp Options:
—Enable timestamping: Not selected
• PCS/Transceiver Options:
—Enable SGMII bridge: Selected
Client Logic Generates and monitors packets sent or received through the IP.
Ethernet Traffic Controller Controlled via Avalon® memory-mapped interface.
JTAG to Avalon memory-
mapped interface Address
Decoder
Convert JTAG Signals for Avalon memory-mapped interface.
2.3.2. Clock and Reset Signals
Table 6. Clock and Reset Signals
Signal Direction Width Description
ref_clk Input 1 Drives register access reference clock and MAC FIFO
status interface clock. Set the clock to 100 MHz.
iopll_refclk Input 1 125 MHz reference clock for the 1.25 Gbps serial
LVDS I/O interface.
2.4. Simulation
The simulation test case performs the following steps:
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and
Embedded PMA
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1. Starts up the design example with an operating speed of 1G.
2. Configures the Triple-Speed Ethernet MAC and PCS registers.
3. Waits until the assertion of the measure valid signal.
4. Sends non-PTP packets to port 0.
5. MAC RX port 0 sends the received packets to MAC TX port 1.
When simulation ends, the values of the MAC statistics counters for port 3 are
displayed in the transcript window. The transcript window also displays PASSED if the
RX Avalon streaming interface received all packets successfully, all statistics error
counters are zero, and the RX MAC statistics counters of port 3 are equal to the TX
MAC statistics counters of port 0.
2.4.1. Testbench
Figure 7. Block Diagram of the Design Example Multiport 10/100/1000Mb Ethernet
MAC with 1000BASE-X/SGMII PCS with LVDS I/O Simulation Testbench
Client
Logic
(Traffic
Controller)
Avalon-ST
Multi-Channel
Shared
Memory FIFO
Avalon
Streaming
Interface
Avalon
Memory-Mapped
Interface
iopll_refclk
ref_clk
rx_afull_clk
Control and Status
Interface
Triple-Speed Ethernet Intel FPGA IP
with MAC without internal FIFO, PCS,
and LVDS I/O
Port 0
Port 1
Port 2
Port 3
A successful testbench sends ten packets and receives the same number of packets.
The following sample output illustrates the excerpt of the output:
Figure 8. Simulation Test Result of VCS Simulator
Statistics MAC Tx Path
— Frames sent in TX path total: 10
— Tx_good_sent: 10
— Tx_vlan_sent: 0
— Tx_stack_vlan_sent: 0
— Payload_err_sent: 0
Statistics MAC Rx Path — Loopback Test
— Rx_good_rcvd: 10
— Rx_vlan_rcvd: 0
— Rx_stack_vlan_rcvd: 0
— Rx_fifo_overflow_rcvd: 0
— Rx_payload_err_rcvd: 0
— Rx_crc_err_rcvd: 0
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and
Embedded PMA
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-- The total number of good packets received by the traffic monitor: 10
-- The total number of packets received with CRC error: 0
-- Loopback Simulation Ended with no Error
- -------------------------------------------------------------------------- -
End of Simulation — Break
$finish called from file "basic_avl_tb_top_mac_pcs.sv", line 5380.
$finish at simulation time 327000000000
V C S S i m u l a t i o n R e p o r t
Time: 327000000000 fs
CPU Time: 259.890 seconds; Data structure size: 9.3Mb
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and
Embedded PMA
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3. Document Revision History for the Triple-Speed
Ethernet Intel FPGA IP Intel Agilex Design Example User
Guide
Document Version Intel Quartus
Prime Version
IP Version Changes
2022.12.09 22.3 21.1.0 Initial release.
741330 | 2022.12.09
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Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel
Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Intel assumes no responsibility or liability arising out of the
application or use of any information, product, or service described herein except as expressly agreed to in
writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered
/