Broadcom BCM7405 General Information Manual

2/24/2008 9T6WP

PRELIMINARY HARDWARE DATA MODULE

BCM7405

7405-1HDM00-R

5300 California Avenue • Irvine, CA 92617 • Phone: 949-926-5000 • Fax: 949-926-5203 06/29/07

General Information

2/24/2008 9T6WP

Broadcom Corporation

5300 California Avenue

Irvine, CA 92617

Printed in the U.S.A.

Broadcom

®

, the pulse logo, Connecting everything

®

, and the Connecting everything logo are among the trademarks of

Broadcom Corporation and/or its affiliates in the United States, certain other countries and/or the EU. Any other trademarks

or trade names mentioned are the property of their respective owners.

This hardware data module (including, without limitation, the Broadcom component(s) identified herein) is not designed,

intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations, pollution control,

hazardous substances management, or other high risk application. BROADCOM PROVIDES THIS HARDWARE DATA

MODULE "AS-IS", WITHOUT WARRANTY OF ANY KIND. BROADCOM DISCLAIMS ALL WARRANTIES, EXPRESSED

AND IMPLIED, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS

FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT.

REVISION HISTORY

Revision # Date Change Description

7405-1HDM00-R 06/29/07 Preliminary release.

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TABLE OF CONTENTS

Document Overview.................................................................................................................................. 1-1

Overview .............................................................................................................................................. 1-2

Functional Description ............................................................................................................................. 1-3

Top-Level Overview ............................................................................................................................. 1-4

Features........................................................................................................................................ 1-5

Video Data Flow................................................................................................................................... 1-8

Overview ....................................................................................................................................... 1-8

Compressed Video Input .............................................................................................................. 1-8

Personal Video Recording ............................................................................................................ 1-9

Digital Video Decompression........................................................................................................ 1-9

ITU-R 656 Input ............................................................................................................................ 1-9

Video Processing.......................................................................................................................... 1-9

Video Encoder ............................................................................................................................ 1-10

Video DACs ................................................................................................................................ 1-10

Data Transport Processor.................................................................................................................. 1-11

Overview ..................................................................................................................................... 1-11

Features...................................................................................................................................... 1-11

Functional Overview ................................................................................................................... 1-13

Data Transport I/O Connections ................................................................................................. 1-16

Data Transport Input Bands

................................................................................................ 1-16

Throughput Data Rate

........................................................................................................ 1-16

PID Parser

.......................................................................................................................... 1-17

Packet Input Buffer

............................................................................................................. 1-17

PID/Packet Substitution and Generation Module

................................................................ 1-18

Multistream CableCard Interface

........................................................................................ 1-19

Condition Access Descramblers (The Downstream Descramblers)

................................... 1-20

NDS ICAM Module

.............................................................................................................. 1-20

Copy Protection

.................................................................................................................. 1-20

PES Parser

......................................................................................................................... 1-21

PSI Section Filter and Processor

........................................................................................ 1-21

Memory Buffer Manager

..................................................................................................... 1-22

Interrupt Controller

.............................................................................................................. 1-22

Record Audio Video Engine (RAVE)

................................................................................... 1-22

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Audio/Video Interface

..........................................................................................................1-25

Playback

..............................................................................................................................1-25

Playback Sync Extractor

.....................................................................................................1-26

Remux Module

....................................................................................................................1-26

PCR Recovery Block

...........................................................................................................1-27

Serial STC Broadcast Module

.............................................................................................1-28

Broadcom Security Processor ............................................................................................................1-28

Advanced Video Decoder...................................................................................................................1-29

VC-1

....................................................................................................................................1-30

MPEG-2

...............................................................................................................................1-30

MPEG-4 Part2

.....................................................................................................................1-30

DivX

.....................................................................................................................................1-30

XVID

....................................................................................................................................1-31

MPEG-1/H.261/H.263

.........................................................................................................1-31

Features ......................................................................................................................................1-31

Supported Picture Sizes..............................................................................................................1-31

Output Data Format.....................................................................................................................1-31

AVD Block Diagram and Data Flow Description .........................................................................1-32

Advanced Audio Module.....................................................................................................................1-33

Features ......................................................................................................................................1-34

Overview of Audio Module ..........................................................................................................1-35

Video and Graphics Display ...............................................................................................................1-36

Overview .....................................................................................................................................1-36

Features

..............................................................................................................................1-36

Video Subsystem

................................................................................................................1-36

Graphics Subsystem

...........................................................................................................1-38

Top Level Partitioning..................................................................................................................1-38

Video (Broadcom Video Network) Subblock Description ............................................................1-39

AVC/MPEG-2/VC-1 Feeder

.................................................................................................1-40

Video Feeder

.......................................................................................................................1-40

Graphics Feeder

..................................................................................................................1-40

Video Scaler

........................................................................................................................1-41

Motion Adaptive De-interlacer

.............................................................................................1-41

Film Grain Technology

........................................................................................................1-42

Compositor

..........................................................................................................................1-42

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Capture Block

..................................................................................................................... 1-42

Digital Noise Reduction ............................................................................................................. 1-43

DNR Operations

.................................................................................................................. 1-43

Digital Contour Removal............................................................................................................. 1-43

Graphics Subblock Description...................................................................................................1-44

Scaler Overview

.................................................................................................................. 1-45

Feeder Architecture (Source and Destination)

.................................................................... 1-46

Color Keying and Color Matrix Architecture

........................................................................ 1-47

Compositor Architecture

..................................................................................................... 1-48

ROP Architecture

................................................................................................................ 1-49

Capture Architecture

........................................................................................................... 1-49

Digital Video Decoder (ITU-R-656) ............................................................................................. 1-50

VBI Decoding

...................................................................................................................... 1-50

Analog Video Encoder ................................................................................................................ 1-50

VBI Encoding

...................................................................................................................... 1-52

Video DACs ................................................................................................................................ 1-53

Digital Video Encoder ................................................................................................................. 1-53

Safe Mode

........................................................................................................................... 1-53

Supported Modes

................................................................................................................ 1-54

Supported PC Scan Rates

.................................................................................................. 1-55

RF Modulator ..................................................................................................................................... 1-56

Overview ..................................................................................................................................... 1-56

Features...................................................................................................................................... 1-56

Typical Usage Modes ................................................................................................................. 1-57

Supported Television Standards

......................................................................................... 1-57

Audio Transmission Modes

................................................................................................. 1-58

Baseband BTSC Composite Output Mode

......................................................................... 1-58

Sound IF Output Mode

........................................................................................................ 1-58

Unsupported Audio Mode

................................................................................................... 1-58

Memory Controller ............................................................................................................................. 1-59

Overview ..................................................................................................................................... 1-59

DRAM Physical Layer Controller ................................................................................................ 1-61

Memory Configurations Supported

..................................................................................... 1-61

DRAM Transaction Layer Controller ........................................................................................... 1-62

Arbitration

............................................................................................................................ 1-62

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Buses

..................................................................................................................................1-62

DDR-SDRAM Memory Image Organization

........................................................................1-62

Digital Video Compression Standards

.................................................................................1-62

Memory Accesses for Video Decompression

......................................................................1-62

DDR Clock Generation................................................................................................................1-62

MIPS4380 Processor Core.................................................................................................................1-63

Overview .....................................................................................................................................1-63

Architecture .................................................................................................................................1-63

Micro-Architecture .......................................................................................................................1-64

EJTAG Debug Support................................................................................................................1-64

Major Functional Blocks ..............................................................................................................1-65

Execution Unit

.....................................................................................................................1-65

Multiply Divide Unit

..............................................................................................................1-66

Floating-Point Unit

...............................................................................................................1-66

eDSP Extended Instructions .......................................................................................................1-67

MIPS16e Application-Specific Extension ....................................................................................1-67

Memory Management Unit with TLB ...........................................................................................1-67

System Control Coprocessor (CP0) ............................................................................................1-68

Instruction Cache ........................................................................................................................1-68

Data Cache .................................................................................................................................1-68

Level-Two Cache ........................................................................................................................1-69

Readahead Cache ......................................................................................................................1-69

Little and Big Endianness of Byte Ordering.................................................................................1-69

Debugging Support Unit ..............................................................................................................1-70

Peripherals .........................................................................................................................................1-71

Overview .....................................................................................................................................1-71

Peripheral Control Unit ................................................................................................................1-71

Keypad Controller........................................................................................................................1-71

LED Controller.............................................................................................................................1-71

IR Receiver Controller .................................................................................................................1-71

IR Blaster Controller ....................................................................................................................1-72

UHF Receiver..............................................................................................................................1-74

UART...........................................................................................................................................1-75

General Description

.............................................................................................................1-75

Functional Description

.........................................................................................................1-76

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Generic I/O Port Controller ......................................................................................................... 1-77

SPI Master .................................................................................................................................. 1-77

Programmable Queue

......................................................................................................... 1-78

Wraparound Transfer Mode

................................................................................................ 1-78

Programmable Transfer Length

.......................................................................................... 1-78

Programmable Transfer Delay

............................................................................................ 1-78

Programmable Queue Pointer

............................................................................................ 1-78

BSC Master ................................................................................................................................ 1-78

BSC Master Interface Operation

......................................................................................... 1-79

BSC Slave .................................................................................................................................. 1-79

BSC Operation

.................................................................................................................... 1-79

PWMs ......................................................................................................................................... 1-80

Timer/Counters ........................................................................................................................... 1-80

Smart Card Interfaces................................................................................................................. 1-80

Features

.............................................................................................................................. 1-81

M-Card CPU Interface ................................................................................................................ 1-82

Introduction

......................................................................................................................... 1-82

Input and Output Processes

............................................................................................... 1-83

PCI and External Bus Interface ..................................................................................................1-84

Advanced Connectivity Interface ................................................................................................ 1-89

Ethernet

.............................................................................................................................. 1-89

Serial ATA Controller

.......................................................................................................... 1-89

USB

..................................................................................................................................... 1-90

Soft Modem

......................................................................................................................... 1-91

PCI

...................................................................................................................................... 1-91

JTAG Interface............................................................................................................................ 1-91

Testability........................................................................................................................................... 1-92

Overview ..................................................................................................................................... 1-92

Production Testing ...................................................................................................................... 1-92

Scan

.................................................................................................................................... 1-92

Built-In Self-Test

................................................................................................................. 1-92

Functional Testing ...................................................................................................................... 1-92

Test Modes

......................................................................................................................... 1-92

Test Buses

.......................................................................................................................... 1-92

On-Board Testing ....................................................................................................................... 1-92

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JTAG

...................................................................................................................................1-92

EJTAG

.................................................................................................................................1-92

Power Features ..................................................................................................................................1-93

Power Modes for DDR DRAM Memory Controller ......................................................................1-93

Power-Up Sequence ...................................................................................................................1-94

Hardware Signal Descriptions................................................................................................................1-95

Pin Definition Notations ......................................................................................................................1-96

Pin Labels....................................................................................................................................1-96

Pin Type ......................................................................................................................................1-96

Power-On Strap Settings..................................................................................................................1-147

Timing and AC Characteristics ............................................................................................................1-149

Data Transport Input Timing.............................................................................................................1-150

MPOD Input Timing ..........................................................................................................................1-151

Data Transport Output Timing ..........................................................................................................1-152

RMX Serial Output Port Timing (Clock/Data/Sync Mode) .........................................................1-152

MPOD Output Timing .......................................................................................................................1-153

I2S Audio/Compressed I2S Output Timing.......................................................................................1-154

SPDIF Audio Output Timing .............................................................................................................1-155

DAC Audio Output Timing ................................................................................................................1-156

256Fs Audio Clock Output Timing....................................................................................................1-157

PCI Interface Timing.........................................................................................................................1-158

EBI Timing........................................................................................................................................1-159

Asynchronous Read Transfer....................................................................................................1-159

Asynchronous Write Transfer....................................................................................................1-160

Synchronous Read Transfer .....................................................................................................1-161

Synchronous Write Transfer......................................................................................................1-162

DDR Interface Timing .......................................................................................................................1-163

HDMI and DVO.................................................................................................................................1-165

ITU656 Output Timing ......................................................................................................................1-166

Timing For ITU656 Output at vo_656 Pins ...............................................................................1-166

Timing For Alternate 656 Output at vi0_656 Pins .....................................................................1-167

Serial Teletext Port Output Timing ............................................................................................1-167

Timing For Serial Teletext Output at rmx_data1 Pin .................................................................1-167

Crystal Requirements............................................................................................................................1-168

Crystal Requirements .......................................................................................................................1-169

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3rd Overtone Crystal Oscillator.................................................................................................1-169

External Components ............................................................................................................... 1-170

SATA Crystal ............................................................................................................................ 1-170

Electrical Characteristics ..................................................................................................................... 1-171

Absolute Maximum Ratings ............................................................................................................. 1-172

Recommended Operating Conditions.............................................................................................. 1-172

Thermal Data ......................................................................................................................................... 1-173

Thermal Data ................................................................................................................................... 1-174

Mechanical Characteristics .................................................................................................................. 1-175

Mechanical Drawings ....................................................................................................................... 1-176

Ordering Information ............................................................................................................................ 1-179

Ordering Information ........................................................................................................................ 1-180

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LIST OF FIGURES

Figure 1-1: Functional Block Diagram ............................................................................................................. 1-7

Figure 1-2: Video Data Flow Diagram ............................................................................................................. 1-8

Figure 1-3: Data Transport and Broadcom Security Processor Block Diagram ............................................ 1-14

Figure 1-4: Data Transport I/O Connections Diagram................................................................................... 1-16

Figure 1-5: Advanced Video Decoding Module Block Diagram..................................................................... 1-32

Figure 1-6: Audio Block Diagram................................................................................................................... 1-33

Figure 1-7: Video and Graphics Block Diagram ............................................................................................ 1-38

Figure 1-8: Video Display Engine Block Diagram.......................................................................................... 1-39

Figure 1-9: DNR Position in BVN .................................................................................................................. 1-43

Figure 1-10: Memory-to-Memory Compositor Block Diagram ....................................................................... 1-45

Figure 1-11: Stripe Example.......................................................................................................................... 1-46

Figure 1-12: Color Keying Flow ..................................................................................................................... 1-48

Figure 1-13: VEC Block Diagram .................................................................................................................. 1-52

Figure 1-14: RF Modulator Block Diagram .................................................................................................... 1-56

Figure 1-15: Memory Controller Partition ...................................................................................................... 1-60

Figure 1-16: Block Diagram of the CPU ........................................................................................................ 1-65

Figure 1-17: Little and Big Endian Byte Ordering .......................................................................................... 1-69

Figure 1-18: Flash IR Scheme Example........................................................................................................ 1-72

Figure 1-19: IR Blaster Block Diagram .......................................................................................................... 1-72

Figure 1-20: Analog Front End of UHF Receiver with External Components................................................ 1-74

Figure 1-21: Digital Front End of UHF Receiver............................................................................................ 1-75

Figure 1-22: UART Functional Block Diagram .............................................................................................. 1-76

Figure 1-23: Asynchronous Serial Data Waveform (01001011 Data, 8-bit Character, Even Parity) ............. 1-76

Figure 1-24: Variable-Frequency PWM Generation Diagram........................................................................ 1-80

Figure 1-25: Smart Card Interface Block Diagram ........................................................................................ 1-81

Figure 1-26: M-Card CPU Interface............................................................................................................... 1-82

Figure 1-27: MCIF Interfaces......................................................................................................................... 1-83

Figure 1-28: EBI Synchronous Read Cycle Between Two PCI Cycles ......................................................... 1-85

Figure 1-29: EBI Asynchronous Read Cycle Between Two PCI Cycles ....................................................... 1-86

Figure 1-30: EBI Asynchronous Write Cycle Between Two PCI Cycles........................................................ 1-87

Figure 1-31: EBI Synchronous Write Cycle Between Two PCI Cycles ......................................................... 1-88

Figure 1-32: SATA Core Block Diagram........................................................................................................ 1-90

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Figure 1-33: Soft Modem Connections ..........................................................................................................1-91

Figure 1-34: Power-Up Sequence Waveforms Without On-chip Voltage Regulator......................................1-94

Figure 1-35: Data Transport Input Band Timing ..........................................................................................1-150

Figure 1-36: MPOD Input Timing .................................................................................................................1-151

Figure 1-37: RMX Serial Output Port Timing (Clock/Data/Sync Mode) .......................................................1-152

Figure 1-38: MPOD Output Timing ..............................................................................................................1-153

Figure 1-39: I2S Audio/Compressed I2S Output Timing Diagram ...............................................................1-154

Figure 1-40: SPDIF Audio Output Timing Diagram......................................................................................1-155

Figure 1-41: DAC Audio Output Timing Diagram.........................................................................................1-156

Figure 1-42: 256Fs Audio Clock Output Timing Diagram ............................................................................1-157

Figure 1-43: PCI Interface Timing Diagram .................................................................................................1-158

Figure 1-44: Async Read Timing Diagram ...................................................................................................1-159

Figure 1-45: Async Write Timing Diagram ...................................................................................................1-160

Figure 1-46: Synchronous Read Timing Diagram........................................................................................1-161

Figure 1-47: Synchronous Write Timing Diagram........................................................................................1-162

Figure 1-48: Write Cycle Timing ..................................................................................................................1-163

Figure 1-49: Read Cycle Timing ..................................................................................................................1-163

Figure 1-50: Clock-to-Data Timing ...............................................................................................................1-165

Figure 1-51: ITU656 Output Timing Diagram...............................................................................................1-166

Figure 1-52: Serial Teletext Port Output Timing Diagram ............................................................................1-167

Figure 1-53: Example: Vendor (TXC) Part Number for 3OT Crystal: 7EA0000023 .....................................1-170

Figure 1-54: 976-FCBGA+HS Package (With Heat Sink)............................................................................1-176

Figure 1-55: 976-FCBGA+HS Package (Without Heat Sink).......................................................................1-177

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LIST OF TABLES

Table 1-1: Document Overview ....................................................................................................................... 1-2

Table 1-2: Video DAC Configuration ............................................................................................................. 1-10

Table 1-3: Definition of Terms ....................................................................................................................... 1-15

Table 1-4: Decode and Display Formats ....................................................................................................... 1-37

Table 1-5: Color and Alpha Selection............................................................................................................ 1-48

Table 1-6: Digital Video Decoder Supported Modes ..................................................................................... 1-50

Table 1-7: VBI Decoding ............................................................................................................................... 1-50

Table 1-8: Analog Video Encoder.................................................................................................................. 1-51

Table 1-9: VBI Encoding................................................................................................................................ 1-52

Table 1-10: DVI Supported Modes ................................................................................................................ 1-54

Table 1-11: ITU-656 Supported Modes ......................................................................................................... 1-54

Table 1-12: DVI PC Scan Clock Rates.......................................................................................................... 1-55

Table 1-13: PC Display Support .................................................................................................................... 1-55

Table 1-14: Supported Modulation Standards............................................................................................... 1-57

Table 1-15: RFM Audio Usage Modes for Normal Operation........................................................................ 1-58

Table 1-16: FPU Latency and Repeat Rate .................................................................................................. 1-67

Table 1-17: Power Estimate .......................................................................................................................... 1-93

Table 1-18: Power Configuration Example.................................................................................................... 1-93

Table 1-19: Pin Descriptions ......................................................................................................................... 1-96

Table 1-20: Power-On Strap Settings.......................................................................................................... 1-147

Table 1-21: Data Transport Input Band Timing Parameters........................................................................ 1-150

Table 1-22: MPOD Input Timing Parameters .............................................................................................. 1-151

Table 1-23: RMX Serial Output Port Timing (Clock/Data/Sync Mode) Parameters .................................... 1-152

Table 1-24: MPOD Output Timing Parameters ........................................................................................... 1-153

Table 1-25: I2S Audio/Compressed I2S Output Timing Parameters........................................................... 1-154

Table 1-26: SPDIF Audio Output Timing Parameters ................................................................................. 1-155

Table 1-27: DAC Audio Output Timing Parameters .................................................................................... 1-156

Table 1-28: 256Fs Audio Clock Output Timing Parameters ........................................................................ 1-157

Table 1-29: PCI Interface Timing Parameters ............................................................................................. 1-158

Table 1-30: Async Read Timing Parameters............................................................................................... 1-159

Table 1-31: Async Write Timing Parameters............................................................................................... 1-160

Table 1-32: Synchronous Read Timing Parameters ................................................................................... 1-161

Table 1-33: Synchronous Write Timing Parameters.................................................................................... 1-162

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Table 1-34: DDR Interface Timing Parameters............................................................................................1-164

Table 1-35: Nominal DVO Output Propagation Delays................................................................................1-165

Table 1-36: Timing for ITU656 Output at vo_656 Pins ................................................................................1-166

Table 1-37: Timing for Alternate 656 Output at vi0_656 Pins ......................................................................1-167

Table 1-38: Timing for Serial Teletext Output at rmx_data1 Pin..................................................................1-167

Table 1-39: Electrical Specifications ............................................................................................................1-169

Table 1-40: SATA Crystal Electrical Characteristics ....................................................................................1-170

Table 1-41: Absolute Maximum Ratings ......................................................................................................1-172

Table 1-42: Recommended Operating Conditions.......................................................................................1-172

Table 1-43: Thermal Data (Without External Heat Sink, 2s2p Board) .........................................................1-174

Table 1-44: Ordering Information .................................................................................................................1-180

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General Information

DOCUMENT OVERVIEW

Overview ............................................................................................................................................ 1-2

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OVERVIEW

The highlighted portion of Table 1-1 outlines information contained within the BCM7405.

Table 1-1: Document Overview

Document # Document Title Description

7405-1HDM0x General Information This document contains the following information:

• A Functional Description containing brief summaries of each functional

block contained within the BCM7405.

• Hardware Signal Descriptions

• Timing and AC Characteristics

• Electrical Characteristics

• Mechanical Drawing

• Ordering Information

7405-2HDM0x Front-End Functions The BCM7405 does not contain Front-End Functions

7405-3HDM0x Data Transport, Audio,

Video, and Graphics

This document contains information on the following functionality:

• Data Transport Processor

• Advanced Audio Module

• Advanced Video Decoder

• Video and Graphics Display Module

• Broadcom Video Network (BVN) Components

• ITU656 Input

• Video Encoder Design

• High-Definition Multimedia Interface (HDMI)

• Memory-To-Memory Compositor

• RF Modulator

7405-4HDM0x I/O Devices This document contains information on the following functionality:

• Peripheral Module

• DDR-SDRAM Controller

• Memory Bus Architecture

• Shared EBI and PCI Bus

• Ethernet Controller and Interface

• Serial ATA 1.0 Host Controller

• Soft Modem Codec Interface

• Universal Serial Bus (USB) Host Interface

• Test BSC Slave Interface

7405-5HDM0x CPU Information This document contains information on the following functionality:

• MIPS32™ CPU Core

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General Information

FUNCTIONAL DESCRIPTION

Top-Level Overview ........................................................................................................................... 1-4

Video Data Flow ................................................................................................................................. 1-8

Data Transport Processor ................................................................................................................ 1-11

Broadcom Security Processor .......................................................................................................... 1-28

Advanced Video Decoder................................................................................................................. 1-29

Advanced Audio Module .................................................................................................................. 1-33

Video and Graphics Display ............................................................................................................. 1-36

RF Modulator.................................................................................................................................... 1-56

Memory Controller ............................................................................................................................ 1-59

MIPS4380 Processor Core............................................................................................................... 1-63

Peripherals ....................................................................................................................................... 1-71

Testability ......................................................................................................................................... 1-92

Power Features ................................................................................................................................ 1-93

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TOP-LEVEL OVERVIEW

The BCM7405 is a next-generation high-definition satellite, cable, and IP set-top box solution offering integrated AVC

(H.264/MPEG-4 Part 10), MPEG-4 Part 2, MPEG-2, and VC-1 video decoding technology. It also supports DivX, H.263, and

XviD formats. The BCM7405 combines a data transport processor, high-definition video decoder, advanced-audio decoder,

2D graphics processing, high-quality video scaling and motion adaptive de-interlacing, six video DACs, stereo high-fidelity

audio DACs, a MIPS 4380 class processor with FPU, and a peripheral control unit providing a variety of set-top box control

functions.

The Data Transport Processor is an MPEG-2 DVB-compliant transport stream message/PES parser and demultiplexer. It is

capable of simultaneously processing 255 PIDs via 128 PID channels in up to six independent external transport stream

inputs and five internal playback channels. The data transport supports decryption for up to 128 PID channels in all streams.

All 128 PID channels can be used by the Record, Audio, and Video interface engine (RAVE), PCR processors, message

filter as well as for output via the high-speed transport or remux module. The data transport module RAVE supports 24

channels. Each RAVE channel can be configured as either a record channel for PVR functionality or as an AV channel to

interface to audio and video decoders. The transport provides 1DES/3DES/DVB/Multi2/AES descrambling support.

A

memory-to-memory DMA security module may be programmed for supporting AES/1DES/3DES/CSS/CPRM/CPPM/DTCP

copy protection algorithms/standards.

The BCM7405 features an enhanced Broadcom Secure Processor providing secure boot key generation, management, and

protection.

An advanced video decoder is featured in the BCM7405, capable of supporting high-definition AVC, VC-1, and ATSC

MPEG-2 streams. AVC support is up to High Profile Level 4.1. New tools in the AVC Fidelity Range extensions are

supported, including 8x8 transform and spatial prediction modes, and adaptive quantization matrix. The video decoder also

supports high-definition VC-1 (Advanced Profile Level 3, Main, and Simple Profiles) and ATSC compliant MPEG-2, Main

Profile at Main and High Levels. The BCM7405 has an advanced programmable audio processor capable of decoding a

broad range of formats including Dolby Digital, Dolby Digital Plus, AAC 5.1, AAC+ Level 2, AAC+ Level 4, WMA, and MPEG

1 Layer 1, 2, and 3 with simultaneous pass-through support. 3D SRS Audio is also supported. The audio processor also

supports advanced transcoding to DTS as an example. Available audio outputs are an SPDIF and one pair of analog outputs.

High-quality video and graphics processing are integrated into the chip, featuring advanced studio quality 2D graphics

processing while still maintaining efficient use of memory bandwidth. Also included are motion adaptive de-interlacing with

3:2 pull-down, and Letterbox Detection. Digital Noise Reduction support is also included; this reduces mosquito noise and

MPEG artifacts, including block noise. Digital contour removal is also supported for low bit rate AVC streams.

The BCM7405 has a dual-stream analog video encoder with Macrovision™ that supports the following output standards:

NTSC-M, NTSC-J, PAL-BDGHIN, PAL-M, PAL-Nc, and SECAM. The following output formats are supported: composite, S-

video, SCART1, SCART2, RGB and YPrPb component. The following output resolutions are supported: 480i, 480p, 576i,

576p, 720p, and 1080i. Six output DACs are available to be shared amongst the output functions. The BCM7405 also

supports output over an HDMI interface and a Channel 3/4 RF Modulator. An ITU-R-656 output port with Teletext sideband

is available if an interface to an additional external video encoder is desired. A high-definition digital video output port is also

available.

The BCM7405 incorporates a complete R4000 family FPU-based microprocessor subsystem, including caches with bridging

to memory and a local bus. NAND and NOR flash is supported. Integrated peripherals include three UARTS, two ISO7816

smart card interfaces, counter/timers, GPIO, LED/keypad controller, IR receivers, IR blaster, UHF remote control receiver,

an integrated soft modem system side device, and BSC and SPI controllers. Advanced connectivity features include two

USB 2.0/1.1 ports, an additional independent USB 2.0/1.1 port, a serial ATA port, an Ethernet port with MAC with an

integrated PHY and a dedicated Media Independent Interface (MII).

2/24/2008 9T6WP

Preliminary Hardware Data Module BCM7405

06/29/07 Functional Description

Broadcom Corporation

Document 7405-1HDM00-R Top-Level Overview Page 1-5

The Macrovision enabled version of this device may only be sold or distributed to authorized Macrovision buyers. If you have

a Macrovision enabled device, then the following applies:

This device is protected by U.S. patent numbers 4,631,603,4,577,216 and 4,819,098 and other intellectual property

rights. The use of Macrovision's copy protection technology in the device must be authorized by Macrovision and is

intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by Macrovision.

Reverse engineering or disassembly is prohibited.

FEATURES

• Advanced AVC/MPEG-2/VC-1 video decoder supporting the following:

- High profile up to level 4.1 H.264/AVC streams (up to Mbps) at 30 frames/sec.

- High or main profile level 3.1 H.264/AVC streams at 60 frames/sec

- New tools in the AVC fidelity range extensions

• 8 x 8 transform and spatial prediction modes

• Adaptive quantization matrix

• DivX 3.11, 4.1, 5.x progressive and interlaced

- VC-1 advanced profile @ level 3

- VC-1 simple and main profile

- HD MPEG-2 4:2:0 streams (up to 125 Mbps) at 30 frames/sec

- SD MPEG-2 4:2:0 streams at 60 frames/sec

- Still picture decode

- HD +SD simultaneous decode

- MPEG4 P2 SP/ASP L5 SD Progressive/Interlaced

• Advanced Audio Processor supporting decode of the following formats:

- AAC LC, AAC LC+SBR Level 2, AAC+ Level 2, AAC+ Level 4

- Dolby Digital, Dolby Digital Plus

- MPEG I Layer 1, 2

- MPEG I Layer 3 (MP3)

- Windows Media Audio (WMA)

-WMA pro

- AAC HE 5.1 decode plus DTS 5.1 encode SPDIF output

- AAC HE 5.1 decode plus AC3 5.1 encode SPDIF output

- MP3 encoding

• One pair of stereo high-fidelity audio DAC

• 3D SRS Audio Support

• One I

2

S input port

• One I

2

S output port

• One SPDIF output

• Advanced 2D-effects graphic engines

- Studio quality text and graphics at HD resolution

- Supports multiple layers and windows

• Digital Noise Reduction (DNR)

- Reduces MPEG artifacts including block noise reduction

- Reduces mosquito noise

• Digital Contour Removal

2/24/2008 9T6WP

BCM7405 Preliminary Hardware Data Module

Functional Description 06/29/07

Broadcom Corporation

Page 1-6 Top-Level Overview Document 7405-1HDM00-R

- Removes banding effects in low bit rate video applications

• Motion adaptive de-interlacer (MAD) with reverse 3:2/2:2 pull-down

• Letter box detection

• ITU-R-656 Digital input. Film grain technology.

• Video encoder

- Supports one SD/HD video stream

- Additionally supports one SD video stream scaled down from the HD content or independent SD.

- NTSC-M, NTSC-J, PAL-BDGHIN, PAL-M, PAL-Nc, SECAM Analog Outputs

- 480i/480p/576i/576p/720p/1080i output formats

- Component RGB or YPrPb Output

- Macrovision 7.1 Support

- Euro-SCART

- Displays component, S-video, and composite via six on-chip DACs

• HDMI/DVI with HDCP 1.2

• ITU-R-656 and 12-bit double clocked 24 bpp HD DVO Outputs

• Next generation Broadcom Security Processor supporting external codes and keys

• AES/1DES/3DES/CPRM/CPPM/CSS/DTCP copy protection algorithms/standards

• DVB, ARIB, and DC2-compliant transport demux with 1DES/3DES/DVB/Multi2/AES descramblers

• V.92 capable soft modem with:

- Integrated SiLab Si305X System Side Device

- Optional five-wire external interface

• 33 MHz PCI 2.3 with 5 volt tolerance

• On chip VCXOs

• Two DDR DRAM controllers

- Primary 64-/32-bit DDR controller

- Optional 32-/16-bit DDR controller

• Dual USB 2.0 host controller with dual port integrated transceiver

- Additional USB 2.0/1.1 host/client controller independent from the dual USB 2.0 controller

• Dual serial ATA-II interface

- SATA ports support hot plug and external SATA drives

• MIPS 4380 class processor with FPU

• RF Modulator with BTSC encoder

• Dual Ethernet

- First MAC to connect to internal integrated 10/100 BASE-T PHY

- Second MAC to connect to MII interface

The BCM7405 incorporates a complete MIPS 4380 Floating Point CPU microprocessor subsystem. including with bridging

to memory and a local bus, where external peripherals can be attached. Integrated peripherals include the following:

• Three UARTS

• UARTC is 16550 compatible

• Two ISO7816 smart card interfaces

• Counter/timers

• GPIO

• LED/keypad controller

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Broadcom BCM7405 General Information Manual

Broadcom BCM7405 General Information Manual

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