MPC860ADS, Revision B - User’s Manual
Release 1.4a
5
General Information
1•6 Revision A to Revision B Changes
1) Added restraining resistors over Dram SIMM address lines and Flash SIMM strobe lines. Exist-
ing restraining resistors, over dram strobe lines, which were glued-in with revision A, are intro-
duced into the PCB.
2) Fixed support for SM732A1000A and SM732A2000 by Smart.
3) Added 2’nd RS232 port over SMC2, with its own dedicated Enable bit in BCSR1.
4) RS232 connector is replaced with a stacked connector block, to support both RS232 ports.
5) Added 4 pull-up resistors over the MSB of each Byte of Dram data lines. This allows for normal
FPM / EDO discrmination.
6) Additional support for external tools: DS1/4 state replaces GND in P9(D20), BRS_EN2~ replac-
es GND in P12(B22) and N.C. in P13(C6). Since ready made tools for previous revisions might
have connected these signals to GND, both are protected with series resistors.
7) Revision field in BCSR3 was changed to ’0011’.
1•7 Revision Pilot to Revision A Changes
1) DS2 which on PILOT revision was connected on SP2 with blue wires, is now integrated into the
PCB, located nearby SP2.
2) UA38 which on revision PILOT was glued and connected with blue-wires, is now integrated into
the PCB. Gate allocation within UA38, is different from revision PILOT, to provide better PCB
routing.
3) Revision code in BCSR is changed to 2.
4) Added optional RA21 (0 ohm) and CA7 (0.01
µ
F) for 10-Base-T interface network.
5) Some SMD pads were enlarged to assist manufacturing.
1•8 Revision ENG to Revision PILOT Changes
1) Added support for ads to function as debug station:
• Added independent 20MHz clock generator for debug port controller
• Added MUX (U38) so that internal logic is clocked by the above generator
• Removed pervious debug clock logic, derived from CLKOUT of the MPC.
• Added signal named CHINS~ (CHip-In-Socket, active-low) which is connected to one
of the MPC's GND pins (isolated from GND layer). This signal controls the above mux
and the indication LEDs illumination.
• Added pull-up resistors on the Chip-Select lines, to avoid possible data-bus contention
when MPC is off-socket.
• DRAMEN~ becomes active-low to allow buffer manipulation supporting LEDs dark-
ness when MPC off-socket. Signal RUN becomes active-high from the same reason.
(Sh. 1, 7, 8, 9, 11, 14)
2) Signals EXTM(1:4) changed to BADDR(28:30),AS~ correspondingly, to support future external
master support. (Sh. 1, 11, 13)
3) MODCK0 renamed to MODCK2, to comply with MPC’s spec convention. (Sh 1, 3, 13)
4) Signal BCLOS~, which was optional for data buffers’ enable logic, is found redundant and re-
moved from ADS logic. Renamed to GPL4A~. (Sh 1, 2, 3, 12)