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HCS08
Microcontrollers
freescale.com
MC9S08QA4
MC9S08QA2
Reference Manual
MC9S08QA4RM
Rev. 2
3/2008
Related Documentation:
• MC9S08QA4 (Data Sheet)
Contains pin assignments and diagrams, all electrical
specifications, and mechanical drawing outlines.
Find the most current versions of all documents at:
http://www.freescale.com
8-Bit HCS08 Central Processor Unit (CPU)
• Up to 20 MHz CPU at 3.6 V to 1.8 V across
temperature range of –40°C to 85°C
• HC08 instruction set with added BGND
instruction
• Support for up to 32 interrupt/reset sources
On-Chip Memory
• Flash read/program/erase over full
operating voltage and temperature
• Random-Access memory (RAM)
• Security circuitry to prevent unauthorized
access to RAM and flash contents
Power-Saving Modes
• Two very low power stop modes
• Peripheral clock enable register can disable
clocks to unused modules, thereby reducing
currents
• Very low power real time counter for use in
run, wait, and stop modes with internal
clock sources
Clock Source Options
• Internal Clock Source (ICS) — Internal
clock source module with a
frequency-locked-loop (FLL) controlled by
internal reference; precision trimming of
internal reference, which allows 0.2%
resolution and 2% deviation over
temperature and voltage; support of bus
frequencies from 1 MHz to
10 MHz
System Protection
• Watchdog computer operating properly
(COP) reset with option to run from
dedicated 1 kHz internal clock source or
bus clock
• Low-Voltage detection with reset or
interrupt
• Selectable trip points
• Illegal opcode detection with reset
• Illegal address detection with reset
• Flash block protection
Development Support
• Single-Wire background debug interface
• Breakpoint capability to allow single
breakpoint setting during in-circuit
debugging
Peripherals
• ADC — 4-channel, 10-bit resolution;
1.7 mV/°C temperature sensor; automatic
compare function; internal bandgap
reference channel; operation in stop3; full
functionality from 3.6 V to 1.8 V.
• ACMP — analog comparator with
selectable interrupt on rising, falling, or
either edge of comparator output; compare
option to fixed internal bandgap reference
voltage; output can be tied internally to
TPM input capture; operation in stop3
• TPM — One 1-channel timer/pulse-width
modulator (TPM) module; selectable input
capture, output compare, or buffered edge-
or center-aligned PWM on each channel;
ACMP output which can be tied internally
to input capture
• MTIM — 8-bit modulo timer module with
8-bit prescaler
• KBI — 4-pin keyboard interrupt module
with software selectable polarity on edge or
edge/level modes
Input/Output
• Four GPIOs, one input-only pin and one
output-only pin
• Hysteresis and configurable pullup device
on all input pins; configurable slew rate and
drive strength on all output pins except
PTA5
Package Options
• 8-pin SOIC, 8-pin DIP, 8-pin DFN
MC9S08QA4 Features
MC9S08QA4 MCU Series Reference Manual
Covers: MC9S08QA4
MC9S08QA2
MC9S08QA4
Rev. 2
3/2008
MC9S08QA4 MCU Series Reference Manual, Rev. 2
6 Freescale Semiconductor
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com
The following revision history table summarizes changes contained in this document.
Revision
Number
Revision
Date
Description of Changes
1 1/2008 Initial public release
2 3/2008 Changed Chapter 11, “Internal Clock Source (S08ICSV1)” to use the ICSV1.
Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
© Freescale Semiconductor, Inc., 2008. All rights reserved.
MC9S08QA4 MCU Series Reference Manual, Rev. 2
Freescale Semiconductor
7
List of Chapters
Chapter Number Title Page
Chapter 1 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chapter 2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Chapter 3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Chapter 4 Memory Map and Register Definition. . . . . . . . . . . . . . . . . . . . . . . 33
Chapter 5 Resets, Interrupts, and General System Control . . . . . . . . . . . . . 51
Chapter 6 Parallel Input/Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Chapter 7 Central Processor Unit (S08CPUV2) . . . . . . . . . . . . . . . . . . . . . . .75
Chapter 8 Keyboard Interrupt (S08KBIV2) . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Chapter 9 Analog Comparator (S08ACMPV2). . . . . . . . . . . . . . . . . . . . . . . . 103
Chapter 10 Analog-to-Digital Converter (S08ADC10V1) . . . . . . . . . . . . . . .111
Chapter 11 Internal Clock Source (S08ICSV1) . . . . . . . . . . . . . . . . . . . . . . . 139
Chapter 12 Modulo Timer (S08MTIMV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Chapter 13 Timer/Pulse-Width Modulator (S08TPMV2) . . . . . . . . . . . . . . . . 161
Chapter 14 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
MC9S08QA4 MCU Series Reference Manual, Rev. 2
Freescale Semiconductor 9
Contents
Section Number Title Page
Chapter 1
Device Overview
1.1 Introduction .....................................................................................................................................17
1.1.1 Devices in the MC9S08QA4 Series ..................................................................................17
1.1.2 MCU Block Diagram ........................................................................................................18
1.2 System Clock Distribution ..............................................................................................................19
Chapter 2
External Signal Description
2.1 Device Pin Assignment ...................................................................................................................21
2.2 Recommended System Connections ...............................................................................................21
2.2.1 Power ................................................................................................................................22
2.2.2 Reset (Input Only) ............................................................................................................23
2.2.3 Background / Mode Select (BKGD/MS) ..........................................................................23
2.2.4 General-Purpose I/O and Peripheral Ports ........................................................................24
Chapter 3
Modes of Operation
3.1 Introduction .....................................................................................................................................27
3.2 Features ...........................................................................................................................................27
3.3 Run Mode ........................................................................................................................................27
3.4 Active Background Mode ...............................................................................................................27
3.5 Wait Mode .......................................................................................................................................28
3.6 Stop Modes ......................................................................................................................................29
3.6.1 Stop3 Mode .......................................................................................................................29
3.6.2 Stop2 Mode .......................................................................................................................30
3.6.3 Stop1 Mode .......................................................................................................................31
3.6.4 On-Chip Peripheral Modules in Stop Modes ....................................................................32
Chapter 4
Memory Map and Register Definition
4.1 MC9S08QA4 Series Memory Map .................................................................................................33
4.2 Reset and Interrupt Vector Assignments .........................................................................................34
4.3 Register Addresses and Bit Assignments ........................................................................................35
4.4 RAM ................................................................................................................................................38
4.5 Flash ................................................................................................................................................39
4.5.1 Features .............................................................................................................................39
4.5.2 Program and Erase Times .................................................................................................39
4.5.3 Program and Erase Command Execution .........................................................................40
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10 Freescale Semiconductor
4.5.4 Burst Program Execution ..................................................................................................41
4.5.5 Access Errors ....................................................................................................................43
4.5.6 Flash Block Protection ......................................................................................................43
4.5.7 Vector Redirection ............................................................................................................44
4.6 Security ............................................................................................................................................44
4.7 Flash Registers and Control Bits .....................................................................................................45
4.7.1 Flash Clock Divider Register (FCDIV) ............................................................................46
4.7.2 Flash Options Register (FOPT and NVOPT) ....................................................................47
4.7.3 Flash Configuration Register (FCNFG) ...........................................................................48
4.7.4 Flash Protection Register (FPROT and NVPROT) ..........................................................48
4.7.5 Flash Status Register (FSTAT) ..........................................................................................49
4.7.6 Flash Command Register (FCMD) ...................................................................................50
Chapter 5
Resets, Interrupts, and General System Control
5.1 Introduction .....................................................................................................................................51
5.2 Features ...........................................................................................................................................51
5.3 MCU Reset ......................................................................................................................................51
5.4 Computer Operating Properly (COP) Watchdog .............................................................................52
5.5 Interrupts .........................................................................................................................................53
5.5.1 Interrupt Stack Frame .......................................................................................................54
5.5.2 External Interrupt Request Pin (IRQ) ...............................................................................54
5.5.3 Interrupt Vectors, Sources, and Local Masks ...................................................................55
5.6 Low-Voltage Detect (LVD) System ................................................................................................56
5.6.1 Power-On Reset Operation ...............................................................................................57
5.6.2 LVD Reset Operation ........................................................................................................57
5.6.3 LVD Interrupt Operation ...................................................................................................57
5.6.4 Low-Voltage Warning (LVW) ...........................................................................................57
5.7 Real-Time Interrupt (RTI) ...............................................................................................................57
5.8 Reset, Interrupt, and System Control Registers and Control Bits ...................................................58
5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) ............................................59
5.8.2 System Reset Status Register (SRS) .................................................................................60
5.8.3 System Background Debug Force Reset Register (SBDFR) ............................................61
5.8.4 System Options Register 1 (SOPT1) ................................................................................62
5.8.5 System Options Register 2 (SOPT2) ................................................................................63
5.8.6 System Device Identification Register (SDIDH, SDIDL) ................................................64
5.8.7 System Real-Time Interrupt Status and Control Register (SRTISC) ................................65
5.8.8 System Power Management Status and Control 1 Register (SPMSC1) ...........................66
5.8.9 System Power Management Status and Control 2 Register (SPMSC2) ...........................67
5.8.10 System Power Management Status and Control 3 Register (SPMSC3) ...........................68
Chapter 6
Parallel Input/Output Control
6.1 Port Data and Data Direction ..........................................................................................................69
6.2 Pin Control — Pullup, Slew Rate, and Drive Strength ...................................................................70
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Freescale Semiconductor 11
6.3 Pin Behavior in Stop Modes ............................................................................................................70
6.4 Parallel I/O Registers ......................................................................................................................71
6.4.1 Port A Registers ................................................................................................................71
6.4.2 Port A Control Registers ...................................................................................................72
Chapter 7
Central Processor Unit (S08CPUV2)
7.1 Introduction .....................................................................................................................................75
7.1.1 Features .............................................................................................................................75
7.2 Programmer’s Model and CPU Registers .......................................................................................76
7.2.1 Accumulator (A) ...............................................................................................................76
7.2.2 Index Register (H:X) ........................................................................................................76
7.2.3 Stack Pointer (SP) .............................................................................................................77
7.2.4 Program Counter (PC) ......................................................................................................77
7.2.5 Condition Code Register (CCR) .......................................................................................77
7.3 Addressing Modes ...........................................................................................................................79
7.3.1 Inherent Addressing Mode (INH) .....................................................................................79
7.3.2 Relative Addressing Mode (REL) ....................................................................................79
7.3.3 Immediate Addressing Mode (IMM) ................................................................................79
7.3.4 Direct Addressing Mode (DIR) ........................................................................................79
7.3.5 Extended Addressing Mode (EXT) ..................................................................................80
7.3.6 Indexed Addressing Mode ................................................................................................80
7.4 Special Operations ...........................................................................................................................81
7.4.1 Reset Sequence .................................................................................................................81
7.4.2 Interrupt Sequence ............................................................................................................81
7.4.3 Wait Mode Operation ........................................................................................................82
7.4.4 Stop Mode Operation ........................................................................................................82
7.4.5 BGND Instruction .............................................................................................................83
7.5 HCS08 Instruction Set Summary ....................................................................................................84
Chapter 8
Keyboard Interrupt (S08KBIV2)
8.1 Introduction .....................................................................................................................................95
8.1.1 Features .............................................................................................................................97
8.1.2 Modes of Operation ..........................................................................................................97
8.1.3 Block Diagram ..................................................................................................................97
8.2 External Signal Description ............................................................................................................98
8.3 Register Definition ..........................................................................................................................98
8.3.1 KBI Status and Control Register (KBISC) .......................................................................98
8.3.2 KBI Pin Enable Register (KBIPE) ....................................................................................99
8.3.3 KBI Edge Select Register (KBIES) ..................................................................................99
8.4 Functional Description ..................................................................................................................100
8.4.1 Edge Only Sensitivity .....................................................................................................100
8.4.2 Edge and Level Sensitivity .............................................................................................100
8.4.3 KBI Pullup/Pulldown Resistors ......................................................................................101
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12 Freescale Semiconductor
8.4.4 KBI Initialization ............................................................................................................101
Chapter 9
Analog Comparator (S08ACMPV2)
9.1 Introduction ...................................................................................................................................103
9.1.1 ACMP Configuration Information ..................................................................................103
9.1.2 ACMP/TPM Configuration Information ........................................................................103
9.1.3 Features ...........................................................................................................................105
9.1.4 Modes of Operation ........................................................................................................105
9.1.5 Block Diagram ................................................................................................................105
9.2 External Signal Description ..........................................................................................................107
9.3 Register Definition ........................................................................................................................107
9.3.1 ACMP Status and Control Register (ACMPSC) ............................................................108
9.4 Functional Description ..................................................................................................................109
Chapter 10
Analog-to-Digital Converter (S08ADC10V1)
10.1 Introduction ...................................................................................................................................111
10.1.1 Module Configurations ...................................................................................................112
10.1.2 Features ...........................................................................................................................115
10.1.3 Block Diagram ................................................................................................................115
10.2 External Signal Description ..........................................................................................................116
10.2.1 Analog Power (V
DDAD
) ..................................................................................................117
10.2.2 Analog Ground (V
SSAD
) .................................................................................................117
10.2.3 Voltage Reference High (V
REFH
) ...................................................................................117
10.2.4 Voltage Reference Low (V
REFL
) ....................................................................................117
10.2.5 Analog Channel Inputs (ADx) ........................................................................................117
10.3 Register Definition ........................................................................................................................117
10.3.1 Status and Control Register 1 (ADCSC1) ......................................................................117
10.3.2 Status and Control Register 2 (ADCSC2) ......................................................................119
10.3.3 Data Result High Register (ADCRH) .............................................................................120
10.3.4 Data Result Low Register (ADCRL) ..............................................................................120
10.3.5 Compare Value High Register (ADCCVH) ....................................................................121
10.3.6 Compare Value Low Register (ADCCVL) .....................................................................121
10.3.7 Configuration Register (ADCCFG) ................................................................................121
10.3.8 Pin Control 1 Register (APCTL1) ..................................................................................123
10.3.9 Pin Control 2 Register (APCTL2) ..................................................................................124
10.3.10Pin Control 3 Register (APCTL3) ..................................................................................125
10.4 Functional Description ..................................................................................................................126
10.4.1 Clock Select and Divide Control ....................................................................................126
10.4.2 Input Select and Pin Control ...........................................................................................127
10.4.3 Hardware Trigger ............................................................................................................127
10.4.4 Conversion Control .........................................................................................................127
10.4.5 Automatic Compare Function .........................................................................................130
10.4.6 MCU Wait Mode Operation ............................................................................................130
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Freescale Semiconductor 13
10.4.7 MCU Stop3 Mode Operation ..........................................................................................130
10.4.8 MCU Stop1 and Stop2 Mode Operation .........................................................................131
10.5 Initialization Information ..............................................................................................................131
10.5.1 ADC Module Initialization Example .............................................................................131
10.6 Application Information ................................................................................................................133
10.6.1 External Pins and Routing ..............................................................................................133
10.6.2 Sources of Error ..............................................................................................................135
Chapter 11
Internal Clock Source (S08ICSV1)
11.1 Introduction ...................................................................................................................................139
11.1.1 Module Configuration .....................................................................................................139
11.1.2 Factory Trim Value .........................................................................................................139
11.1.3 Features ...........................................................................................................................141
11.1.4 Modes of Operation ........................................................................................................141
11.1.5 Block Diagram ................................................................................................................142
11.2 External Signal Description ..........................................................................................................143
11.3 Register Definition ........................................................................................................................143
11.3.1 ICS Control Register 1 (ICSC1) .....................................................................................143
11.3.2 ICS Control Register 2 (ICSC2) .....................................................................................144
11.3.3 ICS Trim Register (ICSTRM) .........................................................................................145
11.3.4 ICS Status and Control (ICSSC) .....................................................................................145
11.4 Functional Description ..................................................................................................................146
11.4.1 Operational Modes ..........................................................................................................146
11.4.2 Mode Switching ..............................................................................................................148
11.4.3 Bus Frequency Divider ...................................................................................................148
11.4.4 Low Power Bit Usage .....................................................................................................149
11.4.5 Internal Reference Clock ................................................................................................149
11.4.6 Optional External Reference Clock ................................................................................149
11.4.7 Fixed Frequency Clock ...................................................................................................149
Chapter 12
Modulo Timer (S08MTIMV1)
12.1 Introduction ...................................................................................................................................151
12.1.1 MTIM/TPM Configuration Information .........................................................................151
12.1.2 Features ...........................................................................................................................153
12.1.3 Modes of Operation ........................................................................................................153
12.1.4 Block Diagram ................................................................................................................154
12.2 External Signal Description ..........................................................................................................154
12.3 Register Definition ........................................................................................................................154
12.3.1 MTIM1 Status and Control Register (MTIM1SC) .........................................................156
12.3.2 MTIM1 Clock Configuration Register (MTIM1CLK) ...................................................157
12.3.3 MTIM1 Counter Register (MTIM1CNT) .......................................................................158
12.3.4 MTIM1 Modulo Register (MTIM1MOD) ......................................................................158
12.4 Functional Description ..................................................................................................................159
MC9S08QA4 MCU Series Reference Manual, Rev. 2
14 Freescale Semiconductor
12.4.1 MTIM Operation Example .............................................................................................160
Chapter 13
Timer/Pulse-Width Modulator (S08TPMV2)
13.1 Introduction ...................................................................................................................................161
13.1.1 ACMP/TPM Configuration Information ........................................................................161
13.1.2 MTIM/TPM Configuration Information .........................................................................161
13.1.3 Features ...........................................................................................................................163
13.1.4 Block Diagram ................................................................................................................163
13.2 External Signal Description ..........................................................................................................165
13.2.1 External TPM Clock Sources .........................................................................................165
13.2.2 TPMxCHn — TPMx Channel n I/O Pins .......................................................................165
13.3 Register Definition ........................................................................................................................165
13.3.1 Timer Status and Control Register (TPMxSC) ...............................................................166
13.3.2 Timer Counter Registers (TPMxCNTH:TPMxCNTL) ...................................................167
13.3.3 Timer Counter Modulo Registers (TPMxMODH:TPMxMODL) ..................................168
13.3.4 Timer Channel n Status and Control Register (TPMxCnSC) .........................................169
13.3.5 Timer Channel Value Registers (TPMxCnVH:TPMxCnVL) .........................................170
13.4 Functional Description ..................................................................................................................171
13.4.1 Counter ............................................................................................................................171
13.4.2 Channel Mode Selection .................................................................................................172
13.4.3 Center-Aligned PWM Mode ...........................................................................................174
13.5 TPM Interrupts ..............................................................................................................................175
13.5.1 Clearing Timer Interrupt Flags .......................................................................................175
13.5.2 Timer Overflow Interrupt Description ............................................................................175
13.5.3 Channel Event Interrupt Description ..............................................................................176
13.5.4 PWM End-of-Duty-Cycle Events ...................................................................................176
Chapter 14
Development Support
14.1 Introduction ...................................................................................................................................177
14.1.1 Module Configuration .....................................................................................................177
14.1.2 Features ...........................................................................................................................178
14.2 Background Debug Controller (BDC) ..........................................................................................178
14.2.1 BKGD Pin Description ...................................................................................................179
14.2.2 Communication Details ..................................................................................................180
14.2.3 BDC Commands .............................................................................................................182
14.2.4 BDC Hardware Breakpoint .............................................................................................185
14.3 On-Chip Debug System (DBG) ....................................................................................................186
14.3.1 Comparators A and B .....................................................................................................186
14.3.2 Bus Capture Information and FIFO Operation ...............................................................186
14.3.3 Change-of-Flow Information ..........................................................................................187
14.3.4 Tag vs. Force Breakpoints and Triggers .........................................................................187
14.3.5 Trigger Modes .................................................................................................................188
14.3.6 Hardware Breakpoints ....................................................................................................190
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Freescale Semiconductor 15
14.4 Register Definition ........................................................................................................................190
14.4.1 BDC Registers and Control Bits .....................................................................................190
14.4.2 System Background Debug Force Reset Register (SBDFR) ..........................................192
14.4.3 DBG Registers and Control Bits .....................................................................................193
MC9S08QA4 MCU Series Reference Manual, Rev. 2
16 Freescale Semiconductor
MC9S08QA4 MCU Series Reference Manual, Rev. 2
Freescale Semiconductor 17
Chapter 1
Device Overview
1.1 Introduction
The MC9S08QA4 series are members of the low-cost, high-performance HCS08 family of 8-bit
microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available
with a variety of modules, memory sizes, memory types, and package types. Refer to Table 1-1 for features
associated with each device in this series.
1.1.1 Devices in the MC9S08QA4 Series
Table 1-1 summarizes the features available in the MC9S08QA4 series of MCUs.
Table 1-1. Devices in the MC9S08QA4 Series
Feature Device
MC9S08QA4 MC9S08QA2
Package 8-Pin 8-Pin
Flash 4K 2K
RAM 256 160
ICS yes
ACMP yes
ADC 4-ch
DBG yes
IRQ yes
KBI 4-pin
MTIM yes
TPM 1-ch
I/O pins
4 I/O
1 output only
1 input only
Package
Types
8 DFN
8 SOIC
8 PDIP
Chapter 1 Device Overview
MC9S08QA4 MCU Series Reference Manual, Rev. 2
18 Freescale Semiconductor
1.1.2 MCU Block Diagram
Figure 1-1. MC9S08QA4 Series Block Diagram
Table 1-2 provides the functional versions of the on-chip modules.
USER FLASH
USER RAM
(MC9S08QA4 = 4096 BYTES)
HCS08 CORE
CPU
BDC
NOTES:
1
Port pins are software configurable with pullup device if input port.
2
Port pins are software configurable for output drive strength.
3
Port pins are software configurable for output slew rate control.
4
IRQ contains a software configurable (IRQPDD) pullup device if PTA5 enabled as IRQ pin function (IRQPE = 1).
5
RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1).
6
PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1).
7
When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can
be used to reconfigure the pullup as a pulldown device.
16-BIT TIMER/PWM
MODULE (TPM)
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
RTI COP
IRQ LVD
8-BIT MODULO TIMER
MODULE (MTIM)
(MC9S08QA2 = 2048 BYTES)
VOLTAGE REGULATOR
PORT A
PTA5//IRQ/TCLK/RESET
PTA4/ACMPO/BKGD/MS
PTA3/KBIP3/ADP3
PTA2/KBIP2/ADP2
PTA1/KBIP1/ADP1/ACMP–
PTA0/KBIP0/TPMCH0/ADP0/ACMP+
8-BIT KEYBOARD
INTERRUPT MODULE (KBI)
(MC9S08QA4 = 256 BYTES)
(MC9S08QA2 = 160BYTES)
DEBUG MODULE (DBG)
ANALOG COMPARATOR
(ACMP)
16 MHz INTERNAL CLOCK
SOURCE (ICS)
V
SS
V
DD
V
SSA
V
DDA
V
REFL
V
REFH
4
ANALOG-TO-DIGITAL
CONVERTER (ADC)
10-BIT
TPMCH0
ACMPO
ACMP–
TCLK
BKGD/MS
IRQ
ACMP+
4
Chapter 1 Device Overview
MC9S08QA4 MCU Series Reference Manual, Rev. 2
Freescale Semiconductor 19
1.2 System Clock Distribution
Figure 1-2 shows a simplified clock connection diagram. Some modules in the MCU have selectable clock
inputs as shown. The clock inputs to the modules indicate which clock(s) are used to drive the module
function. All memory mapped registers associated with the modules are clocked with BUSCLK.
Figure 1-2. System Clock Distribution Diagram
Table 1-2. Versions of On-Chip Modules
Module Version
Analog Comparator (ACMP) 2
Analog-to-Digital Converter (ADC) 1
Central Processing Unit (CPU) 2
Internal Clock Source (ICS) 1
Keyboard Interrupt (KBI) 2
Modulo Timer (MTIM) 1
Timer Pulse-Width Modulator (TPM) 2
Debug Module (DBG) 2
TPM MTIM
CPU
BDC
ADC
FLASH
ICS
ICSOUT
÷2
ICSFFE
SYSTEM
LOGIC
BUSCLK
ICSLCLK
1
CONTROL
FIXED FREQ CLOCK (XCLK)
RTI
1
ICSLCLK is the alternate BDC clock source for the MC9S08QA4 series.
2
ADC has min and max frequency requirements. See the ADC chapter and MC9S08QA4 Series Data Sheet.
3
Flash has frequency requirements for program and erase operation. See MC9S08QA4 Series Data Sheet.
÷2
ICSFFCLK
COP1 kHz
TCLK
Chapter 1 Device Overview
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