NXP S08QE Reference guide

HCS08

Microcontrollers

freescale.com

MC9S08QE8

MC9S08QE4

Reference Manual

MC9S08QE8RM

Rev. 7

4/2011

MC9S08QE8 Series Features

8-Bit HCS08 Central Processor Unit (CPU)

• Up to 20 MHz CPU at 3.6 V to 1.8 V across temperature

range of –40°C to 85°C

• HC08 instruction set with added BGND instruction

• Support for up to 32 interrupt/reset sources

On-Chip Memory

• Flash read/program/erase over full operating voltage and

temperature

• Random-Access memory (RAM)

• Security circuitry to prevent unauthorized access to RAM

and flash contents

Power-Saving Modes

• Two low power stop modes

• Reduced power wait mode

• Low power run and wait modes allow peripherals to run

while voltage regulator is in standby

• Peripheral clock gating register can disable clocks to unused

modules, thereby reducing currents.

• Very low power external oscillator that can be used in stop2

and stop3 modes to provide accurate clock source to real

time counter

•6 s typical wake up time from stop3 mode

Clock Source Options

• Oscillator (XOSC) — Loop-Control Pierce oscillator;

crystal or ceramic resonator range of 31.25 kHz to

38.4 kHz or 1 MHz to 16 MHz

• Internal Clock Source (ICS) — Internal clock source

module containing a frequency-locked-loop (FLL)

controlled by internal or external reference; precision

trimming of internal reference allows 0.2% resolution and

2% deviation over temperature and voltage; supporting bus

frequencies from 1 MHz to 10 MHz.

System Protection

• Watchdog computer operating properly (COP) reset with

option to run from dedicated 1 kHz internal clock source or

bus clock

• Low-Voltage warning with interrupt

• Low-Voltage detection with reset or interrupt

• Illegal opcode detection with reset

• Illegal address detection with reset

• Flash block protection

Development Support

• Single-Wire background debug interface

• Breakpoint capability to allow single breakpoint setting

during in-circuit debugging (plus two more breakpoints in

on-chip debug module)

• On-Chip in-circuit emulator (ICE) debug module

containing three comparators and nine trigger modes. Eight

deep FIFO for storing change-of-flow addresses and

event-only data. Debug module supports both tag and force

breakpoints

Peripherals

• ADC — 10-channel, 12-bit resolution; 2.5 s conversion

time; automatic compare function; 1.7 mV/C temperature

sensor; internal bandgap reference channel; operation in

stop3; fully functional from 3.6 V to 1.8 V

• ACMPx — Two analog comparators with selectable

interrupt on rising, falling, or either edge of comparator

output; compare option to fixed internal bandgap reference

voltage; outputs can be optionally routed to TPM module;

operation in stop3

• SCI — Full-Duplex non-return to zero (NRZ); LIN master

extended break generation; LIN slave extended break

detection; wake-up on active edge

• SPI — Full-Duplex or single-wire bidirectional;

double-buffered transmit and receive; master or slave mode;

MSB-first or LSB-first shifting

• IIC — IIC with up to 100 kbps with maximum bus loading;

multi-master operation; programmable slave address;

interrupt driven byte-by-byte data transfer; supporting

broadcast mode and 10-bit addressing

• TPMx — Two 3-channel TPMs (TPM1 and TPM2);

selectable input capture, output compare, or buffered edge-

or center-aligned PWM on each channel

• RTC — (Real-Time counter) 8-bit modulus counter with

binary or decimal based prescaler; external clock source for

precise time base, time-of-day, calendar or task scheduling

functions; free running on-chip low power oscillator

(1 kHz) for cyclic wake-up without external components;

runing in all MCU modes

Input/Output

• 26 GPIOs, one output-only pin and one input-only pin

• Eight KBI interrupts with selectable polarity

• Hysteresis and configurable pullup device on all input pins;

configurable slew rate and drive strength on all output pins.

Package Options

• 32-pin LQFP, 32-pin QFN, 28-pin SOIC, 20-pin SOIC,

16-pin PDIP, 16-pin TSSOP

MC9S08QE8 Reference Manual

Covers MC9S08QE8

MC9S08QE4

MC9S08QE8RM

Rev. 7

4/2011

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.

Related Documentation:

• MC9S08QE8 (Data Sheet)

Contains pin assignments and diagrams, all electrical

specifications, and mechanical drawing outlines.

Find the most current versions of all documents at:

http://www.freescale.com

MC9S08QE8 Series Reference Manual, Rev. 7

6 Freescale Semiconductor

Revision History

To provide the most up-to-date information, the revision of our documents on the World Wide Web will be

the most current. Your printed copy may be an earlier revision. To verify you have the latest information

available, refer to:

http://freescale.com/

The following revision history table summarizes changes contained in this document.

Revision

Number

Revision

Date

Description of Changes

2 Nov 2007 Initial preliminary release

3 Jan 2008 Initial public release

4 Jan 2009

Changed the ADC conversion time to 2.5 s in the feature page. Changed the

unit in Equation 10-2 to s.

Added a note to the Section 15.1, “Introduction.”

Fixed the cross reference in Section 12.7, “Initialization/Application Information.”

Added a paragraph before Table 4- 4 and added a footnote of IFR at the same

page.

Updated “How to reach us” information.

5 May 19, 2009

Updated Section 13.1.5, “RTC Clock Gating.”

Updated Figure 4-2 and Figure 4-3.

In Chapter 11, “Internal Clock Source (S08ICSV3),” added a note in

Section 11.1.3.7, “Stop (STOP);” updated Figure 11-2 to reflect ICSERCLK is

gated off when STOP is high or when ERCLKEN is low.

In Chapter 10, “Analog-to-Digital Converter (S08ADC12V1),” Changed V

DDAD

supply references to V

DDA

; fixed ADCRH:L description for compare operation,

including an updates of Section 10.4.5, “Automatic Compare Function”

description and ADCRH:L register descriptions (Section 10.3.3, “Data Result

High Register (ADCRH) and Section 10.3.4, “Data Result Low Register

(ADCRL).”)

Reworded Chapter 16, “Timer/Pulse-Width Modulator (S08TPMV3).”

6 Sept 2, 2009

Added FLS bit description in the Ta bl e 5- 15 .

Updated Section 13.1.2, “RTC Clock Sources,” to clarify the clock sources for

the RTC.

7 April 12, 2011 Added 32-pin QFN package information.

This product incorporates SuperFlash



Technology licensed from SST.

MC9S08QE8 Series Reference Manual, Rev. 7

Freescale Semiconductor 7

List of Chapters

Chapter 1 Device Overview ......................................................................19

Chapter 2 Pins and Connections ............................................................. 23

Chapter 3 Modes of Operation ................................................................. 33

Chapter 4 Memory ..................................................................................... 45

Chapter 5 Resets, Interrupts, and General System Control.................. 67

Chapter 6 Parallel Input/Output Control.................................................. 87

Chapter 7 Keyboard Interrupt (S08KBIV2) ............................................ 101

Chapter 8 Central Processor Unit (S08CPUV4) .................................... 109

Chapter 9 Analog Comparator (S08ACMPVLPV1) ............................... 129

Chapter 10 Analog-to-Digital Converter (S08ADC12V1)........................135

Chapter 11 Internal Clock Source (S08ICSV3)........................................ 163

Chapter 12 Inter-Integrated Circuit (S08IICV2) ....................................... 177

Chapter 13 Real-Time Counter (S08RTCV1) ........................................... 195

Chapter 14 Serial Communications Interface (S08SCIV4)..................... 205

Chapter 15 Serial Peripheral Interface (S08SPIV3) ................................225

Chapter 16 Timer/Pulse-Width Modulator (S08TPMV3) ......................... 241

Chapter 17 Development Support ........................................................... 263

Chapter 18 Debug Module (S08DBGV3) (64K)........................................275

MC9S08QE8 Series Reference Manual, Rev. 7

Freescale Semiconductor 9

Section Number Title Page

Chapter 1

Device Overview

1.1 Devices in the MC9S08QE8 Series ................................................................................................19

1.2 MCU Block Diagram ......................................................................................................................20

1.3 System Clock Distribution ..............................................................................................................21

Chapter 2

Pins and Connections

2.1 Device Pin Assignment ...................................................................................................................23

2.2 Recommended System Connections ...............................................................................................26

2.2.1 Power ................................................................................................................................27

2.2.2 Oscillator ...........................................................................................................................28

2.2.3 R

ESET Pin ........................................................................................................................28

2.2.4 Background / Mode Select (BKGD/MS) ..........................................................................29

2.2.5 General-Purpose I/O (GPIO) and Peripheral Ports ...........................................................30

Chapter 3

Modes of Operation

3.1 Introduction .....................................................................................................................................33

3.2 Features ...........................................................................................................................................33

3.3 Run Mode ........................................................................................................................................33

3.3.1 Low Power Run Mode (LPRun) .......................................................................................33

3.4 Active Background Mode ...............................................................................................................34

3.5 Wait Mode .......................................................................................................................................35

3.5.1 Low Power Wait Mode (LPWait) .....................................................................................36

3.6 Stop Modes ......................................................................................................................................36

3.6.1 Stop2 Mode .......................................................................................................................37

3.6.2 Stop3 Mode .......................................................................................................................38

3.6.3 Active BDM Enabled in Stop Mode .................................................................................38

3.6.4 LVD Enabled in Stop Mode ..............................................................................................38

3.6.5 Stop Modes in Low Power Run Mode ..............................................................................39

3.7 Mode Selection ................................................................................................................................39

3.7.1 On-Chip Peripheral Modules in Stop and Low Power Modes .........................................42

Chapter 4

Memory

4.1 MC9S08QE8 Series Memory Map .................................................................................................45

4.2 Reset and Interrupt Vector Assignments .........................................................................................46

4.3 Register Addresses and Bit Assignments ........................................................................................47

4.4 RAM ................................................................................................................................................53

4.5 Flash ................................................................................................................................................53

4.5.1 Features .............................................................................................................................54

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10 Freescale Semiconductor

Section Number Title Page

4.5.2 Program and Erase Times .................................................................................................54

4.5.3 Program and Erase Command Execution .........................................................................55

4.5.4 Burst Program Execution ..................................................................................................56

4.5.5 Access Errors ....................................................................................................................58

4.5.6 Flash Block Protection ......................................................................................................58

4.5.7 Vector Redirection ............................................................................................................59

4.6 Security ............................................................................................................................................59

4.7 Flash Registers and Control Bits .....................................................................................................60

4.7.1 Flash Clock Divider Register (FCDIV) ............................................................................61

4.7.2 Flash Options Register (FOPT and NVOPT) ....................................................................62

4.7.3 Flash Configuration Register (FCNFG) ...........................................................................63

4.7.4 Flash Protection Register (FPROT and NVPROT) ..........................................................63

4.7.5 Flash Status Register (FSTAT) ..........................................................................................64

4.7.6 Flash Command Register (FCMD) ...................................................................................65

Chapter 5

Resets, Interrupts, and General System Control

5.1 Introduction .....................................................................................................................................67

5.2 Features ...........................................................................................................................................67

5.3 MCU Reset ......................................................................................................................................67

5.4 Computer Operating Properly (COP) Watchdog .............................................................................68

5.5 Interrupts .........................................................................................................................................69

5.5.1 Interrupt Stack Frame .......................................................................................................70

5.5.2 External Interrupt Request (IRQ) Pin ...............................................................................70

5.5.3 Interrupt Vectors, Sources, and Local Masks ...................................................................71

5.6 Low-Voltage Detect (LVD) System ................................................................................................73

5.6.1 Power-On Reset Operation ...............................................................................................73

5.6.2 Low-Voltage Detection (LVD) Reset Operation ...............................................................73

5.6.3 Low-Voltage Detection (LVD) Interrupt Operation ..........................................................73

5.6.4 Low-Voltage Warning (LVW) Interrupt Operation ...........................................................73

5.7 Peripheral Clock Gating ..................................................................................................................73

5.8 Reset, Interrupt, and System Control Registers and Control Bits ...................................................74

5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) ............................................75

5.8.2 System Reset Status Register (SRS) .................................................................................76

5.8.3 System Background Debug Force Reset Register (SBDFR) ............................................77

5.8.4 System Options Register 1 (SOPT1) ................................................................................78

5.8.5 System Options Register 2 (SOPT2) ................................................................................79

5.8.6 System Device Identification Register (SDIDH, SDIDL) ................................................80

5.8.7 System Power Management Status and Control 1 Register (SPMSC1) ...........................81

5.8.8 System Power Management Status and Control 2 Register (SPMSC2) ...........................82

5.8.9 System Power Management Status and Control 3 Register (SPMSC3) ...........................83

5.8.10 System Clock Gating Control 1Register (SCGC1) ...........................................................84

MC9S08QE8 Series Reference Manual, Rev. 7

Freescale Semiconductor 11

Section Number Title Page

5.8.11 System Clock Gating Control 2 Register (SCGC2) ..........................................................85

Chapter 6

Parallel Input/Output Control

6.1 Port Data and Data Direction ..........................................................................................................87

6.2 Pullup, Slew Rate, and Drive Strength ............................................................................................88

6.2.1 Port Internal Pullup Enable ...............................................................................................88

6.2.2 Port Slew Rate Enable ......................................................................................................88

6.2.3 Port Drive Strength Select ................................................................................................88

6.3 Pin Behavior in Stop Modes ............................................................................................................89

6.4 Parallel I/O and Pin Control Registers ............................................................................................89

6.4.1 Port A Registers ................................................................................................................90

6.4.2 Port B Registers ................................................................................................................92

6.4.3 Port C Registers ................................................................................................................95

6.4.4 Port D Registers ................................................................................................................97

Chapter 7

Keyboard Interrupt (S08KBIV2)

7.1 Introduction ...................................................................................................................................101

7.1.1 KBI Clock Gating ...........................................................................................................101

7.1.2 Features ...........................................................................................................................103

7.1.3 Modes of Operation ........................................................................................................103

7.1.4 Block Diagram ................................................................................................................103

7.2 External Signal Description ..........................................................................................................104

7.3 Register Definition ........................................................................................................................104

7.3.1 KBI Interrupt Status and Control Register (KBISC) ......................................................104

7.3.2 KBI Interrupt Pin Select Register (KBIPE) ....................................................................105

7.3.3 KBI Interrupt Edge Select Register (KBIES) .................................................................106

7.4 Functional Description ..................................................................................................................106

7.4.1 Edge Only Sensitivity .....................................................................................................106

7.4.2 Edge and Level Sensitivity .............................................................................................107

7.4.3 Pullup/Pulldown Resistors ..............................................................................................107

7.4.4 Keyboard Interrupt Initialization ....................................................................................107

Chapter 8

Central Processor Unit (S08CPUV4)

8.1 Introduction ...................................................................................................................................109

8.1.1 Features ...........................................................................................................................109

8.2 Programmer’s Model and CPU Registers .....................................................................................110

8.2.1 Accumulator (A) .............................................................................................................110

8.2.2 Index Register (H:X) ......................................................................................................110

8.2.3 Stack Pointer (SP) ...........................................................................................................111

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12 Freescale Semiconductor

Section Number Title Page

8.2.4 Program Counter (PC) ....................................................................................................111

8.2.5 Condition Code Register (CCR) .....................................................................................111

8.3 Addressing Modes .........................................................................................................................113

8.3.1 Inherent Addressing Mode (INH) ...................................................................................113

8.3.2 Relative Addressing Mode (REL) ..................................................................................113

8.3.3 Immediate Addressing Mode (IMM) ..............................................................................113

8.3.4 Direct Addressing Mode (DIR) ......................................................................................113

8.3.5 Extended Addressing Mode (EXT) ................................................................................114

8.3.6 Indexed Addressing Mode ..............................................................................................114

8.4 Special Operations .........................................................................................................................115

8.4.1 Reset Sequence ...............................................................................................................115

8.4.2 Interrupt Sequence ..........................................................................................................115

8.4.3 Wait Mode Operation ......................................................................................................116

8.4.4 Stop Mode Operation ......................................................................................................116

8.4.5 BGND Instruction ...........................................................................................................117

8.5 HCS08 Instruction Set Summary ..................................................................................................118

Chapter 9

Analog Comparator (S08ACMPVLPV1)

9.1 Introduction ...................................................................................................................................129

9.1.1 ACMP Configuration Information ..................................................................................129

9.1.2 ACMP/TPM Configuration Information ........................................................................129

9.1.3 ACMP Clock Gating .......................................................................................................129

9.1.4 Interrupt Vectors .............................................................................................................129

9.1.5 Stop1 Not Available ........................................................................................................130

9.1.6 Features ...........................................................................................................................131

9.1.7 Modes of Operation ........................................................................................................131

9.1.8 Block Diagram ................................................................................................................131

9.2 External Signal Description ..........................................................................................................132

9.3 Register Definition ........................................................................................................................132

9.3.1 Status and Control Register (ACMPxSC) .......................................................................132

9.4 Functional Description ..................................................................................................................133

9.5 Interrupts .......................................................................................................................................133

Chapter 10

Analog-to-Digital Converter (S08ADC12V1)

10.1 Introduction ...................................................................................................................................135

10.1.1 ADC Clock Gating ..........................................................................................................135

10.1.2 Module Configurations ...................................................................................................136

10.1.3 Features ...........................................................................................................................139

10.1.4 ADC Module Block Diagram .........................................................................................139

10.2 External Signal Description ..........................................................................................................140

MC9S08QE8 Series Reference Manual, Rev. 7

Freescale Semiconductor 13

Section Number Title Page

10.2.1 Analog Power (V

DDA

) ....................................................................................................141

10.2.2 Analog Ground (V

SSA

) ...................................................................................................141

10.2.3 Voltage Reference High (V

REFH

) ...................................................................................141

10.2.4 Voltage Reference Low (V

REFL

) ....................................................................................141

10.2.5 Analog Channel Inputs (ADx) ........................................................................................141

10.3 Register Definition ........................................................................................................................141

10.3.1 Status and Control Register 1 (ADCSC1) ......................................................................141

10.3.2 Status and Control Register 2 (ADCSC2) ......................................................................143

10.3.3 Data Result High Register (ADCRH) .............................................................................144

10.3.4 Data Result Low Register (ADCRL) ..............................................................................144

10.3.5 Compare Value High Register (ADCCVH) ....................................................................145

10.3.6 Compare Value Low Register (ADCCVL) .....................................................................145

10.3.7 Configuration Register (ADCCFG) ................................................................................145

10.3.8 Pin Control 1 Register (APCTL1) ..................................................................................147

10.3.9 Pin Control 2 Register (APCTL2) ..................................................................................148

10.3.10Pin Control 3 Register (APCTL3) ..................................................................................149

10.4 Functional Description ..................................................................................................................150

10.4.1 Clock Select and Divide Control ....................................................................................150

10.4.2 Input Select and Pin Control ...........................................................................................151

10.4.3 Hardware Trigger ............................................................................................................151

10.4.4 Conversion Control .........................................................................................................151

10.4.5 Automatic Compare Function .........................................................................................154

10.4.6 MCU Wait Mode Operation ............................................................................................155

10.4.7 MCU Stop3 Mode Operation ..........................................................................................155

10.4.8 MCU Stop2 Mode Operation ..........................................................................................156

10.5 Initialization Information ..............................................................................................................156

10.5.1 ADC Module Initialization Example .............................................................................156

10.6 Application Information ................................................................................................................158

10.6.1 External Pins and Routing ..............................................................................................158

10.6.2 Sources of Error ..............................................................................................................160

Chapter 11

Internal Clock Source (S08ICSV3)

11.1 Introduction ...................................................................................................................................163

11.1.1 Features ...........................................................................................................................165

11.1.2 Block Diagram ................................................................................................................165

11.1.3 Modes of Operation ........................................................................................................166

11.2 External Signal Description ..........................................................................................................167

11.3 Register Definition ........................................................................................................................167

11.3.1 ICS Control Register 1 (ICSC1) .....................................................................................168

11.3.2 ICS Control Register 2 (ICSC2) .....................................................................................169

11.3.3 ICS Trim Register (ICSTRM) .........................................................................................170

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14 Freescale Semiconductor

Section Number Title Page

11.3.4 ICS Status and Control (ICSSC) .....................................................................................170

11.4 Functional Description ..................................................................................................................172

11.4.1 Operational Modes ..........................................................................................................172

11.4.2 Mode Switching ..............................................................................................................174

11.4.3 Bus Frequency Divider ...................................................................................................175

11.4.4 Low Power Bit Usage .....................................................................................................175

11.4.5 DCO Maximum Frequency with 32.768 kHz Oscillator ................................................175

11.4.6 Internal Reference Clock ................................................................................................175

11.4.7 External Reference Clock ...............................................................................................176

11.4.8 Fixed Frequency Clock ...................................................................................................176

11.4.9 Local Clock .....................................................................................................................176

Chapter 12

Inter-Integrated Circuit (S08IICV2)

12.1 Introduction ...................................................................................................................................177

12.1.1 Module Configuration .....................................................................................................177

12.1.2 IIC Clock Gating .............................................................................................................177

12.1.3 Features ...........................................................................................................................179

12.1.4 Modes of Operation ........................................................................................................179

12.1.5 Block Diagram ................................................................................................................179

12.2 External Signal Description ..........................................................................................................180

12.2.1 SCL — Serial Clock Line ...............................................................................................180

12.2.2 SDA — Serial Data Line ................................................................................................180

12.3 Register Definition ........................................................................................................................180

12.3.1 IIC Address Register (IICA) ...........................................................................................181

12.3.2 IIC Frequency Divider Register (IICF) ..........................................................................181

12.3.3 IIC Control Register (IICC1) ..........................................................................................184

12.3.4 IIC Status Register (IICS) ...............................................................................................184

12.3.5 IIC Data I/O Register (IICD) ..........................................................................................185

12.3.6 IIC Control Register 2 (IICC2) .......................................................................................186

12.4 Functional Description ..................................................................................................................187

12.4.1 IIC Protocol .....................................................................................................................187

12.4.2 10-bit Address .................................................................................................................190

12.4.3 General Call Address ......................................................................................................191

12.5 Resets ............................................................................................................................................191

12.6 Interrupts .......................................................................................................................................191

12.6.1 Byte Transfer Interrupt ....................................................................................................191

12.6.2 Address Detect Interrupt .................................................................................................192

12.6.3 Arbitration Lost Interrupt ................................................................................................192

12.7 Initialization/Application Information ..........................................................................................193

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Freescale Semiconductor 15

Section Number Title Page

Chapter 13

Real-Time Counter (S08RTCV1)

13.1 Introduction ...................................................................................................................................195

13.1.1 ADC Hardware Trigger ..................................................................................................195

13.1.2 RTC Clock Sources .........................................................................................................195

13.1.3 RTC Modes of Operation ................................................................................................195

13.1.4 RTC Status after Stop2 Wakeup ......................................................................................195

13.1.5 RTC Clock Gating ..........................................................................................................195

13.1.6 Features ...........................................................................................................................197

13.1.7 Modes of Operation ........................................................................................................197

13.1.8 Block Diagram ................................................................................................................198

13.2 External Signal Description ..........................................................................................................198

13.3 Register Definition ........................................................................................................................198

13.3.1 RTC Status and Control Register (RTCSC) ....................................................................199

13.3.2 RTC Counter Register (RTCCNT) ..................................................................................200

13.3.3 RTC Modulo Register (RTCMOD) ................................................................................200

13.4 Functional Description ..................................................................................................................200

13.4.1 RTC Operation Example .................................................................................................201

13.5 Initialization/Application Information ..........................................................................................202

Chapter 14

Serial Communications Interface (S08SCIV4)

14.1 Introduction ...................................................................................................................................205

14.1.1 SCI Clock Gating ............................................................................................................205

14.1.2 Features ...........................................................................................................................207

14.1.3 Modes of Operation ........................................................................................................207

14.1.4 Block Diagram ................................................................................................................207

14.2 Register Definition ........................................................................................................................210

14.2.1 SCI Baud Rate Registers (SCIBDH, SCIBDL) ..............................................................210

14.2.2 SCI Control Register 1 (SCIC1) .....................................................................................211

14.2.3 SCI Control Register 2 (SCIC2) .....................................................................................212

14.2.4 SCI Status Register 1 (SCIS1) ........................................................................................213

14.2.5 SCI Status Register 2 (SCIS2) ........................................................................................215

14.2.6 SCI Control Register 3 (SCIC3) .....................................................................................216

14.2.7 SCI Data Register (SCID) ...............................................................................................217

14.3 Functional Description ..................................................................................................................217

14.3.1 Baud Rate Generation .....................................................................................................217

14.3.2 Transmitter Functional Description ................................................................................218

14.3.3 Receiver Functional Description ....................................................................................219

14.3.4 Interrupts and Status Flags ..............................................................................................221

14.3.5 Additional SCI Functions ...............................................................................................222

MC9S08QE8 Series Reference Manual, Rev. 7

16 Freescale Semiconductor

Section Number Title Page

Chapter 15

Serial Peripheral Interface (S08SPIV3)

15.1 Introduction ...................................................................................................................................225

15.1.1 SPI Clock Gating ............................................................................................................225

15.1.2 Features ...........................................................................................................................227

15.1.3 Block Diagrams ..............................................................................................................227

15.1.4 SPI Baud Rate Generation ..............................................................................................229

15.2 External Signal Description ..........................................................................................................230

15.2.1 SPSCK — SPI Serial Clock ............................................................................................230

15.2.2 MOSI — Master Data Out, Slave Data In ......................................................................230

15.2.3 MISO — Master Data In, Slave Data Out ......................................................................230

15.2.4 SS — Slave Select ..........................................................................................................230

15.3 Modes of Operation .......................................................................................................................231

15.3.1 SPI in Stop Modes ..........................................................................................................231

15.4 Register Definition ........................................................................................................................231

15.4.1 SPI Control Register 1 (SPIC1) ......................................................................................231

15.4.2 SPI Control Register 2 (SPIC2) ......................................................................................232

15.4.3 SPI Baud Rate Register (SPIBR) ....................................................................................233

15.4.4 SPI Status Register (SPIS) ..............................................................................................234

15.4.5 SPI Data Register (SPID) ...............................................................................................235

15.5 Functional Description ..................................................................................................................236

15.5.1 SPI Clock Formats ..........................................................................................................236

15.5.2 SPI Interrupts ..................................................................................................................239

15.5.3 Mode Fault Detection .....................................................................................................239

Chapter 16

Timer/Pulse-Width Modulator (S08TPMV3)

16.1 Introduction ...................................................................................................................................241

16.1.1 ACMP/TPM Configuration Information ........................................................................241

16.1.2 TPM External Clock .......................................................................................................241

16.1.3 TPM Pin Repositioning ..................................................................................................241

16.1.4 TPM Clock Gating ..........................................................................................................241

16.1.5 Features ...........................................................................................................................243

16.1.6 Modes of Operation ........................................................................................................243

16.1.7 Block Diagram ................................................................................................................244

16.2 Signal Description .........................................................................................................................246

16.2.1 Detailed Signal Descriptions ..........................................................................................246

16.3 Register Definition ........................................................................................................................249

16.3.1 TPM Status and Control Register (TPMxSC) ................................................................249

16.3.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL) ....................................................250

16.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) ....................................251

16.3.4 TPM Channel n Status and Control Register (TPMxCnSC) ..........................................252

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Freescale Semiconductor 17

Section Number Title Page

16.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) ..........................................253

16.4 Functional Description ..................................................................................................................255

16.4.1 Counter ............................................................................................................................255

16.4.2 Channel Mode Selection .................................................................................................256

16.5 Reset Overview .............................................................................................................................259

16.5.1 General ............................................................................................................................259

16.5.2 Description of Reset Operation .......................................................................................260

16.6 Interrupts .......................................................................................................................................260

16.6.1 General ............................................................................................................................260

16.6.2 Description of Interrupt Operation .................................................................................260

Chapter 17

Development Support

17.1 Introduction ...................................................................................................................................263

17.1.1 Forcing Active Background ............................................................................................263

17.1.2 Module Configuration .....................................................................................................263

17.1.3 Features ...........................................................................................................................264

17.2 Background Debug Controller (BDC) ..........................................................................................264

17.2.1 BKGD Pin Description ...................................................................................................265

17.2.2 Communication Details ..................................................................................................265

17.2.3 BDC Commands .............................................................................................................268

17.2.4 BDC Hardware Breakpoint .............................................................................................271

17.3 Register Definition ........................................................................................................................271

17.3.1 BDC Registers and Control Bits .....................................................................................271

17.3.2 System Background Debug Force Reset Register (SBDFR) ..........................................274

Chapter 18

Debug Module (S08DBGV3) (64K)

18.1 Introduction ...................................................................................................................................275

18.1.1 Features ...........................................................................................................................275

18.1.2 Modes of Operation ........................................................................................................276

18.1.3 Block Diagram ................................................................................................................276

18.2 Signal Description .........................................................................................................................276

18.3 Memory Map and Registers ..........................................................................................................277

18.3.1 Module Memory Map .....................................................................................................277

18.3.2 Register Descriptions ......................................................................................................278

18.4 Functional Description ..................................................................................................................290

18.4.1 Comparator .....................................................................................................................290

18.4.2 Breakpoints .....................................................................................................................290

18.4.3 Trigger Selection .............................................................................................................291

18.4.4 Trigger Break Control (TBC) .........................................................................................291

18.4.5 FIFO ................................................................................................................................295

MC9S08QE8 Series Reference Manual, Rev. 7

18 Freescale Semiconductor

Section Number Title Page

18.4.6 Interrupt Priority .............................................................................................................296

18.5 Resets ............................................................................................................................................296

18.6 Interrupts .......................................................................................................................................296

MC9S08QE8 Series Reference Manual, Rev. 7

Freescale Semiconductor 19

Chapter 1

Device Overview

The MC9S08QE8 and MC9S08QE4 are members of the low-cost, low-power, high-performance HCS08

family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and

are available with a variety of modules, memory sizes, memory types, and package types.

1.1 Devices in the MC9S08QE8 Series

Table 1-1 summarizes the feature set available in the MC9S08QE8 series of MCUs.

t

Table 1-1. MC9S08QE8 Series Features by MCU and Package

Feature MC9S08QE8 MC9S08QE4

Flash size (bytes) 8192 4096

RAM size (bytes) 512 256

Pin quantity 32 28 20 16 32 28 20 16

ACMP1 yes

ACMP2 yes yes no no yes yes no no

ADC channels 10 10 8 8 10 10 8 8

ADC Resolution 12 12 10 10 12 12 10 10

DBG yes

ICS yes

IIC yes

IRQ yes

KBI 8

Port I/O

1

Port I/O count does not include the output-only PTA4 or the input-only

PTA5 pins.

26 22 16 12 26 22 16 12

RTC yes

SCI yes

SPI yes

TPM1 channels 3 3323332

TPM2 channels 3 3323332

XOSCVLP yes

Chapter 1 Device Overview

MC9S08QE8 Series Reference Manual, Rev. 7

20 Freescale Semiconductor

1.2 MCU Block Diagram

The block diagram in Figure 1-1 shows the structure of the MC9S08QE8 series MCU.

Figure 1-1. MC9S08QE8 Series Block Diagram

IIC MODULE (IIC)

USER FLASH

USER RAM

HCS08 CORE

CPU

BDC

PTB7/SCL/EXTAL

PORT B

HCS08 SYSTEM CONTROL

RESETS AND INTERRUPTS

MODES OF OPERATION

POWER MANAGEMENT

COP

LVD

PTB6/SDA/XTAL

PTB5/TPM1CH1/SS

PTB4/TPM2CH1/MISO

PTB3/KBIP7/MOSI/ADP7

PTB2/KBIP6/SPSCK/ADP6

VOLTAGE REGULATOR

PORT A

PTA1/KBIP1/TPM2CH0/ADP1/ACMP1–

ANALOG COMPARATOR

(ACMP1)

LOW-POWER OSCILLATOR

20 MHz INTERNAL CLOCK

SOURCE (ICS)

31.25 kHz to 38.4 kHz

1 MHz to 16 MHz

(XOSCVLP)

V

SS

V

DD

ANALOG-TO-DIGITAL

CONVERTER (ADC12)

12-BIT

PTB1/KBIP5/TxD/ADP5

PTB0/KBIP4/RxD/ADP4

PORT C

PTC7/ACMP2-

PTC6/ACMP2+

PTC5/ACMP2O

PTC4

REAL-TIME COUNTER

(MC9S08QE8 = 8192 BYTES)

(MC9S08QE4 = 4096 BYTES)

(MC9S08QE8 = 512 BYTES)

(MC9S08QE4 = 256 BYTES)

PTA3/KBIP3/SCL/ADP3

PTA2/KBIP2/SDA/ADP2

PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+

PTA4/ACMP1O/BKGD/MS

PTA5/IRQ/TCLK/RESET

IRQ

pins not available on 16-pin packages

pins not available on 16-pin or 20-pin packages

(RTC)

ANALOG COMPARATOR

(ACMP2)

PTA7/TPM2CH2/ADP9

PTA6/TPM1CH2/ADP8

PTC3

PTC2

PTC1/TPM2CH2

PTC0/TPM1CH2

PORT D

PTD3

PTD2

PTD1

PTD0

V

SSA

/V

REFL

V

DDA

/V

REFH

pins not available on 16-pin, 20-pin or 28-pin packages

BKGD/MS

IRQ

EXTAL

XTAL

V

REFL

V

REFH

SCL

SDA

SERIAL PERIPHERAL

INTERFACE MODULE (SPI)

MISO

MOSI

SPSCK

SS

INTERFACE MODULE (SCI)

SERIAL COMMUNICATIONS

RxD

TxD

DEBUG MODULE (DBG)

TCLK

TPM2CH0

TPM2CH1

ACMP1O

ACMP1–

ACMP1+

ACMP2O

ACMP2–

ACMP2+

ADP9–ADP0

TPM2CH2

TCLK

TPM1CH0

TPM1CH1

TPM1CH2

16-BIT TIMER PWM

MODULE (TPM1)

16-BIT TIMER PWM

MODULE (TPM2)

KEYBOARD INTERRUPT

MODULE (KBI)

KBIP7–KBIP0

V

SSA

V

DDA

V

SSA

V

DDA

Notes: When PTA5 is configured as RESET, pin becomes bi-directional with output being open-drain drive containing an internal pullup device.

When PTA4 is configured as BKGD, pin becomes bi-directional.

For the 16-pin and 20-pin packages, V

SSA

/V

REFL

and V

DDA

/V

REFH

are double bonded to V

SS

and V

DD

respectively.

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NXP S08QE Reference guide

NXP S08QE Reference guide

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