Freescale Semiconductor MC9S12XHY Series Reference guide

Type
Reference guide

This manual is also suitable for

S12
Microcontrollers
freescale.com
MC9S12XHY256
Reference Manual
Covers MC9S12XHY Family
MC9S12XHY256RMV1
Rev. 1.01
03/2011
Data Sheet: Advance Information
This document contains information on a new product. Specifications and information here in are subject to change without notice.
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
A full list of family members and options is included in the appendices.
The following revision history table summarizes changes contained in this document.
This document contains information for all constituent modules, with the exception of the CPU. For CPU
information please refer to CPU12-1 in the CPU12 & CPU12X Reference Manual.
Revision History
Date
Revision
Level
Description
Jun,3,2010 0.11
update block: TIM SCI PIM Chapter1
update
Table A-6., “5-V I/O Characteristics, item 11/12,unit is Kand uA
update
A.1.10.1, “Typical Run Current Measurement Conditions
update Table A-6., “5-V I/O Characteristics, 4(a) , remove V C contitions
update Table A-6., “5-V I/O Characteristics,4(b), remove temperature
update Table A-10., “Run and Wait Current Characteristics, remove item
update
Table A-11., “Pseudo Stop and Full Stop Current,
-10a/10b/11/12/13/14,remove temperature except -40/25/150
-15, change to FSP mode
remove Typeical Run supply table
update Table A-11., “Pseudo Stop and Full Stop Current, add LCP FSP mode
Jun,11,2010 0.12
update Appendix electrical parameter
-
Table A-6., “5-V I/O Characteristics 4a 9 10 11 12
Table A-11., “Pseudo Stop and Full Stop Current,10a,11a,12a,14,15
-Table A-4./A-721 LCD/Motor Driver pad can only be work under >4.5V
-A.1.3.1/A-718, change to 4.5v to 5.5v
-remove 12 bit resolution at table
Table A-12./A-731
update chapter MMC to Ver04.11 3.1/3-157
update chapter MSCAN to Ver03.12
update Table D-2./D-768,all parts has 2x CAN and SCI
Mar,25,2011 1.01
update Appendix electrical parameter value
Table A-11., “Pseudo Stop and Full Stop Current,
Table A-9., “Module Run Supply Currents
Table A-6., “5-V I/O Characteristics, item 4b
update Appendix, change classifications or conditions
Table A-6., “5-V I/O Characteristics, item 4b, change from 80c to 150c
Table A-11., “Pseudo Stop and Full Stop Current,item 11b,change from P to C
fix typo Table A-6., “5-V I/O Characteristics, 11 and 12, resistance not current
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© Freescale Semiconductor, Inc. 2006
MC9S12XHY-Family Reference Manual, Rev. 1.01
4 Freescale Semiconductor
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor 5
Chapter 1
Device Overview MC9S12XHY-Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Chapter 2
Port Integration Module (S12XHYPIMV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Chapter 3
Memory Mapping Control (S12XMMCV4) . . . . . . . . . . . . . . . . . . . . . . . . . . .157
Chapter 4
Interrupt (S12XINTV2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
Chapter 5
Background Debug Module (S12XBDMV2) . . . . . . . . . . . . . . . . . . . . . . . . .197
Chapter 6
S12X Debug (S12XDBGV3) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
Chapter 7
S12XE Clocks and Reset Generator (S12XECRGV2) . . . . . . . . . . . . . . . . .259
Chapter 8
Pierce Oscillator (S12XOSCLCPV2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289
Chapter 9
Voltage Regulator (S12VREGL3V3V1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
Chapter 10
Analog-to-Digital Converter (ADC12B12CV1) . . . . . . . . . . . . . . . . . . . . . . .315
Chapter 11
Freescale’s Scalable Controller Area Network (S12MSCANV3) . . . . . . . . .341
Chapter 12
Inter-Integrated Circuit (IICV3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395
Chapter 13
Pulse-Width Modulator (S12PWM8B8CV1) . . . . . . . . . . . . . . . . . . . . . . . . . .423
Chapter 14
Serial Communication Interface (S12SCIV5) . . . . . . . . . . . . . . . . . . . . . . . .455
Chapter 15
Serial Peripheral Interface (S12SPIV5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .493
Chapter 16
Timer Module (TIM16B8CV2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .519
MC9S12XHY-Family Reference Manual, Rev. 1.01
6 Freescale Semiconductor
Chapter 17
Liquid Crystal Display (LCD40F4BV2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .547
Chapter 18
256 KByte Flash Module (S12XFTMR256K1V1) . . . . . . . . . . . . . . . . . . . . . .569
Chapter 19
128 KByte Flash Module (S12XFTMR128K1V1) . . . . . . . . . . . . . . . . . . . . . .619
Chapter 20
Motor Controller (MC10B8CV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .667
Chapter 21
Stepper Stall Detector (SSDV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .699
Appendix A
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .717
Appendix B
Package and Die Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .758
Appendix C
PCB Layout Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .765
Appendix D
Derivative Differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .768
Appendix E
Detailed Register Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .768
Appendix F
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .799
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor 7
Chapter 1
Device Overview MC9S12XHY-Family
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3 Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.5 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.6 Part ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.7 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.8 System Clock Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
1.9 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
1.10 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
1.11 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
1.12 COP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
1.13 ATD External Trigger Input Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
1.14 ATD Channel[17] Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
1.15 VREG Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
1.16 Oscillator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
1.17 Documentation Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Chapter 2
Port Integration Module (S12XHYPIMV1)
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
2.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
2.5 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Chapter 3
Memory Mapping Control (S12XMMCV4)
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
3.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
3.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
3.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
3.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Chapter 4
Interrupt (S12XINTV2)
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
4.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
4.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
4.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
MC9S12XHY-Family Reference Manual, Rev. 1.01
8 Freescale Semiconductor
Chapter 5
Background Debug Module (S12XBDMV2)
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
5.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
5.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Chapter 6
S12X Debug (S12XDBGV3) Module
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
6.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
6.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Chapter 7
S12XE Clocks and Reset Generator (S12XECRGV2)
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
7.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
7.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
7.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
7.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Chapter 8
Pierce Oscillator (S12XOSCLCPV2)
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
8.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
8.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Chapter 9
Voltage Regulator (S12VREGL3V3V1)
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
9.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
9.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Chapter 10
Analog-to-Digital Converter (ADC12B12CV1)
Block Description
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
10.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
10.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor 9
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
10.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
10.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Chapter 11
Freescale’s Scalable Controller Area Network (S12MSCANV3)
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
11.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
11.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
11.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Chapter 12
Inter-Integrated Circuit (IICV3) Block Description
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
12.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
12.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
12.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
12.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
12.7 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
Chapter 13
Pulse-Width Modulator (S12PWM8B8CV1)
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
13.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
13.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
13.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
13.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
Chapter 14
Serial Communication Interface (S12SCIV5)
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
14.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
14.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
14.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
Chapter 15
Serial Peripheral Interface (S12SPIV5)
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
15.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
15.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
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15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
Chapter 16
Timer Module (TIM16B8CV2) Block Description
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
16.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
16.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
16.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
16.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
Chapter 17
Liquid Crystal Display (LCD40F4BV2) Block Description
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
17.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
17.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
17.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
17.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
Chapter 18
256 KByte Flash Module (S12XFTMR256K1V1)
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
18.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
18.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
18.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
Chapter 19
128 KByte Flash Module (S12XFTMR128K1V1)
19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
19.2 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
19.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
19.4 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
19.5 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
Chapter 20
Motor Controller (MC10B8CV1)
20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
20.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
20.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
20.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
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20.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
20.7 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
Chapter 21
Stepper Stall Detector (SSDV1) Block Description
21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
21.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
21.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710
Appendix A
Electrical Characteristics
A.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718
A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
A.1.5 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
A.1.6 ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
A.1.8 Power Dissipation and Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
A.2.1 ATD Operating Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
A.2.2 Factors Influencing Accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
A.2.3 ATD Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
A.3 NVM, Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
A.3.1 Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
A.3.2 NVM Reliability Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
A.4 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
A.5 Output Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
A.5.1 Resistive Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
A.5.2 Capacitive Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
A.5.3 Chip Power-up and Voltage Drops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
A.6 Reset, Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746
A.6.1 Startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746
A.6.2 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
A.6.3 Phase Locked Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
A.7 LCD Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
A.8 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
A.9 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754
A.9.1 Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754
A.9.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756
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Appendix B
Package and Die Information
B.1 112-pin LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
B.2 100-Pin LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
Appendix C
PCB Layout Guidelines
C.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765
C.1.1 112-Pin LQFP Recommended PCB Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766
C.1.2 100-Pin QFP Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
Appendix D
Derivative Differences
D.1 Memory Sizes and Package Options 9S12XHY family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768
Appendix E
Detailed Register Address Map
E.1 Detailed Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768
Appendix F
Ordering Information
F.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
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Freescale Semiconductor 13
Chapter 1
Device Overview MC9S12XHY-Family
1.1 Introduction
The MC9S12XHY family is an optimized, automotive, 16-bit microcontroller product line that is
specifically designed for entry level instrument clusters. This family also services generic automotive
applications requiring CAN, LCD, Motor driver control or LIN/SAE J2602. Typical examples of these
applications include instrument clusters for automobiles and 2 or 3 wheelers, HVAC displays, general
purpose motor control and body controllers.
The MC9S12XHY family uses many of the same features found on the MC9S12XS family and
MC9S12HY/HA family, including error correction code (ECC) on flash memory, a separate data-flash
module for diagnostic or data storage, a fast analog-to-digital converter (ATD) and a frequency modulated
phase locked loop (IPLL) that improves the EMC performance. The MC9S12XHY family features a 40x4
liquid crystal display (LCD) controller/driver and a motor pulse width modulator (MC) consisting of up to
16 high current outputs. The device is capable of stepper motor stall detection (SSD) via hardware or
software, please contact Freescale sales office for detailed information on software SSD.
The MC9S12XHY family deliver all the advantages and efficiencies of a 16-bit MCU while retaining the
low cost, power consumption, EMC, and code-size efficiency advantages currently enjoyed by users of
Freescale’s existing 8-bit and 16-bit MCU families. Like the MC9S12HY/HA family, the MC9S12XHY
family run 16-bit wide accesses without wait states for all peripherals and memories. The MC9S12XHY
family is available in 112-pin LQFP and 100-pin LQFP package options. In addition to the I/O ports
available in each module, further I/O ports are available with interrupt capability allowing wake-up from
stop or wait modes.
1.2 Features
This section describes the key features of the MC9S12XHY family.
Device Overview MC9S12XHY-Family
MC9S12XHY-Family Reference Manual, Rev. 1.01
14 Freescale Semiconductor
1.2.1 MC9S12XHY Family Comparison
Table 1-1 provides a summary of different members of the MC9S12XHY family and their proposed
features. This information is intended to provide an understanding of the range of functionality offered by
this microcontroller family.
Table 1-1. MC9S12XHY Family
Feature
MC9S12XHY128 MC9S12XHY256
CPU
HCS12X V1
Flash memory
(ECC)
128Kbytes 256 Kbytes
Data flash (ECC)
8 Kbytes
RAM
8 Kbytes 12kbyte
Pin Quantity
100 112 100 112
CAN
2
SCI
2
SPI
1
IIC
1
Timer 0
8 ch x 16-bit
Timer 1
8 ch x 16-bit
PWM
8 ch x 8-bit or 4ch x16-bit
ADC (10-bit)
8 ch 12ch 8ch 12 ch
Stepper Motor
Controller
4
Stepper Stall
Detecter
4
LCD Driver
(FPxBP)
38x4 40x4 38x4 40x4
Key Wakeup Pins
23 25 23 25
Frequency Modu-
lated PLL
Yes
External osc
(4–16 MHz Pierce
with loop control)
Yes
Device Overview MC9S12XHY-Family
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor 15
1.2.2 Chip-Level Features
On-chip modules available within the family include the following features:
CPU12XV1 CPU core
Up to 256 Kbyte on-chip flash with ECC
8Kbyte data flash with ECC
Up to 12Kbyte on-chip SRAM
Phase locked loop (IPLL) frequency multiplier with internal filter
4–16 MHz amplitude controlled Pierce oscillator
Two timer modules (TIM0 and TIM1) supporting input/output channels that provide a range of 16-
bit input capture, output compare, counter and pulse accumulator functions
Pulse width modulation (PWM) module with up to 8 x 8-bit channels
Up to 12-channel, 10-bit resolution successive approximation analog-to-digital converter (ATD)
Up to 40x4 LCD driver
PWM motor controller (MC) with up to 16 high current drivers
Output slew rate control on Motor driver pad
One serial peripheral interface (SPI) module
One Inter-IC bus interface (IIC) module
Two serial communication interface (SCI) module supporting LIN communications
Two multi-scalable controller area network (MSCAN) module (supporting CAN protocol 2.0A/B)
On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages
Autonomous periodic interrupt (API)
Stepper Motor Controller with up to drivers for up to 4 motors
Four Stepper Stall Detector modules (one for each motor)
Up to 25 key wakup inputs
1.3 Module Features
The following sections provide more details of the modules implemented on the MC9S12XHY family.
Internal 1 MHz RC
osc
No
Supply voltage
4.5 V – 5.5 V
RTI, LVI, CRG,
RST, COP, DBG,
POR, API
Yes
Execution speed
Static-40MHz
Table 1-1. MC9S12XHY Family
Feature
MC9S12XHY128 MC9S12XHY256
Device Overview MC9S12XHY-Family
MC9S12XHY-Family Reference Manual, Rev. 1.01
16 Freescale Semiconductor
1.3.1 S12 16-Bit Central Processor Unit (CPU)
The CPU12X is a high-speed, 16-bit processing unit that has a programming model identical to that of the
industry standard M68HC11 central processor unit (CPU).
Upward compatible with S12 instruction set, with the exception of five Fuzzy instructions (MEM,
WAV, WAVR, REV, REVW) which have been removed
Enhanced indexed addressing
Access to large data segments independent of PPAGE
1.3.2 On-Chip Flash with ECC
On-chip flash memory on the MC9S12XHY features the following:
Up to 256Kbyte of program flash memory
64data bits plus 8 syndrome ECC (error correction code) bits allow single bit error correction
and double fault bit detection
Erase sector size 1024bytes
Automated program and erase algorithm
Protection scheme to prevent accidental program or erase
Security option to prevent unauthorized access
Sense-amp margin level setting for reads
8Kbyte data flash space
16 data bits plus 6 syndrome ECC (error correction code) bits allow single bit error correction
and double fault detection
Erase sector size 256 bytes
Automated program and erase algorithm
1.3.3 On-Chip SRAM
Up to 12Kbytes of general-purpose RAM
1.3.4 Main External Oscillator (XOSC)
Loop control Pierce oscillator using a 4 MHz to 16 MHz crystal
Current gain control on amplitude output
Signal with low harmonic distortion
Low power
Good noise immunity
Eliminates need for external current limiting resistor
Transconductance sized for optimum start-up margin for typical crystals
Device Overview MC9S12XHY-Family
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor 17
1.3.5 Internal Phase-Locked Loop (IPLL)
Phase-locked-loop clock frequency multiplier
No external components required
Reference divider and multiplier allow large variety of clock rates
Automatic bandwidth control mode for low-jitter operation
Automatic frequency lock detector
Configurable option to spread spectrum for reduced EMC radiation (frequency modulation)
1.3.6 Clocks and reset generation(CRG)
COP watchdog
Real time interrupt
Clock monitor
Fast wake up from STOP in self clock mode
1.3.7 System Integrity Support
Power-on reset (POR)
System reset generation
Illegal address detection with reset
Low-voltage detection with interrupt or reset
Real time interrupt (RTI)
Computer operating properly (COP) watchdog
Configurable as window COP for enhanced failure detection
Initialized out of reset using option bits located in flash memory
Clock monitor supervising the correct function of the oscillator
Temperature sensor
1.3.8 Timer (TIM0)
8x 16-bit channels for input capture
8x 16-bit channels for output compare
16-bit free-running counter with 8-bit precision prescaler
1 x 16-bit pulse accumulator
1.3.9 Timer (TIM1)
8x 16-bit channels for input capture
8x 16-bit channels for output compare
Device Overview MC9S12XHY-Family
MC9S12XHY-Family Reference Manual, Rev. 1.01
18 Freescale Semiconductor
16-bit free-running counter with 8-bit precision prescaler
1 x 16-bit pulse accumulator
1.3.10 Liquid crystal display driver (LCD)
Configurable for up to 40 frontplanes and 4 backplanes or general-purpose input or output
5 modes of operation allow for different display sizes to meet application requirements
Unused frontplane and backplane pins can be used as general-purpose I/O
1.3.11 Motor Controller (MC)
PWM motor controller (MC) with up to 16 high current drivers
Each PWM channel switchable between two drivers in an H-bridge configuration
Left, right and center aligned outputs
Support for sine and cosine drive
Dithering
Output slew rate control
1.3.12 Pulse Width Modulation Module (PWM)
8channel x 8-bit or 4channel x 16-bit pulse width modulator
Programmable period and duty cycle per channel
Center-aligned or left-aligned outputs
Programmable clock select logic with a wide range of frequencies
1.3.13 Inter-IC bus Module (IIC)
1 Inter-IC (IIC) bus module which has following feature
Multi-master operation
Soft programming for one of 256 different serial clock frequencies
General Call(Broadcast) mode support
10-bit address support
1.3.14 Controller Area Network Module (MSCAN)
1 Mbit per second, CAN 2.0 A, B software compatible
Standard and extended data frames
0–8 bytes data length
Programmable bit rate up to 1 Mbps
Five receive buffers with FIFO storage scheme
Three transmit buffers with internal prioritization
Flexible identifier acceptance filter programmable as:
Device Overview MC9S12XHY-Family
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor 19
2 x 32-bit
4 x 16-bit
8 x 8-bit
Wakeup with integrated low pass filter option
Loop back for self test
Listen-only mode to monitor CAN bus
Bus-off recovery by software intervention or automatically
16-bit time stamp of transmitted/received messages
1.3.15 Serial Communication Interface Module (SCI)
Full-duplex or single-wire operation
Standard mark/space non-return-to-zero (NRZ) format
Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths
13-bit baud rate selection
Programmable character length
Programmable polarity for transmitter and receiver
Active edge receive wakeup
Break detect and transmit collision detect supporting LIN
1.3.16 Serial Peripheral Interface Module (SPI)
Configurable 8- or 16-bit data size
Full-duplex or single-wire bidirectional
Double-buffered transmit and receive
Master or slave mode
MSB-first or LSB-first shifting
Serial clock phase and polarity options
1.3.17 Analog-to-Digital Converter Module (ATD)
Up to 12-channel, 10-bit analog-to-digital converter
3 us single conversion time
8-/10 bit resolution
Left or right justified result data
Internal oscillator for conversion in stop modes
Wakeup from low power modes on analog comparison > or <= match
Continuous conversion mode
Multiple channel scans
Pins can also be used as digital I/O
Device Overview MC9S12XHY-Family
MC9S12XHY-Family Reference Manual, Rev. 1.01
20 Freescale Semiconductor
1.3.18 On-Chip Voltage Regulator (VREG)
Linear voltage regulator with bandgap reference
Low-voltage detect (LVD) with low-voltage interrupt (LVI)
Power-on reset (POR) circuit
Low-voltage reset (LVR)
1.3.19 Background Debug (BDM)
Background debug module (BDM) with single-wire interface
Non-intrusive memory access commands
Supports in-circuit programming of on-chip nonvolatile memory
1.3.20 Debugger (DBG)
Three comparators A, B, C, and D to monitor CPU buses
Trace buffer with depth of 64 entries
Comparator A and C compares full address bus and 16-bit data bus with mask register
Three modes: simple address/data match, inside address range, or outside address range
1.3.21 SSD
Programmable Full Step State
Programmable Integration polarity
Blanking (recirculation) state
16-bit Integration Accumulator register
16-Bit Modulus Down Counter with interrupt
Multiplex two stepper motors
1.3.22 INT (interrupt module)
Seven levels of nested interrupts
Flexible assignment of interrupt sources to each interrupt level.
External non-maskable high priority interrupt (XIRQ)
The following inputs can act as Wake-up Interrupts
IRQ and non-maskable XIRQ
CAN receive pins
SCI receive pins
Depending on the package option up to 25 pins on ports R, S, T and AD, configurable as rising
or falling edge sensitive
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Freescale Semiconductor MC9S12XHY Series Reference guide

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