NXP MAC7131 Reference guide

MAC7100RM

Rev. 2

02/2009

MAC7100 Microcontroller Family

Reference Manual

Devices Supported:

MAC7101 MAC7106

MAC7111 MAC7112

MAC7116 MAC7121

MAC7122 MAC7126

MAC7131 MAC7136

MAC7141 MAC7142

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MAC7100RM

Rev. 2

02/2009

MAC7100 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor iii

1Introduction

2Signal Description

3Voltage Regulator Module (VREG)

4System Clocks Module (OSC and CRG)

5Resets

6Exceptions

7Modes of Operation

8Device Memory Map

9ARM7TDMI-S™ Processor Core

10Interrupt Controller Module (INTC)

11Miscellaneous Control Module (MCM)

12Enhanced Direct Memory Access Controller Module (eDMA)

13External Interface Module (EIM)

14Cross-Bar Switch Module (XBS)

15Common Flash Module (CFM)

16AMBA to IP Bus Bridge Module (AIPS)

17DMA Channel Multiplexer Module (DMAMux)

18Port Integration Module (PIM)

19Analog-to-Digital Converter Module (ATD)

20Enhanced Modular I/O Subsystem Module (eMIOS)

21Enhanced Serial Communications Interface Module (eSCI)

22Deserial Serial Peripheral Interface Module (DSPI)

23Controller Area Network Module (FlexCAN)

24Inter-Integrated Circuit Bus Module (I

2

C)

25Periodic Interrupt Timer Module (PIT)

26System Services Module (SSM)

ADebug Interface

BA7S Nexus 2 Module

CRegister Memory Map Quick Reference

DMask Set Differences Summary

Tab Pages

MAC7100 Microcontroller Family Reference Manual, Rev. 2

iv Freescale Semiconductor

1 Introduction

2 Signal Description

3 Voltage Regulator Module (VREG)

4 System Clocks Module (OSC and CRG)

5 Resets

6 Exceptions

7 Modes of Operation

8 Device Memory Map

9 ARM7TDMI-S™ Processor Core

10 Interrupt Controller Module (INTC)

11 Miscellaneous Control Module (MCM)

12 Enhanced Direct Memory Access Controller Module (eDMA)

13 External Interface Module (EIM)

14 Cross-Bar Switch Module (XBS)

15 Common Flash Module (CFM)

16 AMBA to IP Bus Bridge Module (AIPS)

17 DMA Channel Multiplexer Module (DMAMux)

18 Port Integration Module (PIM)

19 Analog-to-Digital Converter Module (ATD)

20 Enhanced Modular I/O Subsystem Module (eMIOS)

21 Enhanced Serial Communications Interface Module (eSCI)

22 Deserial Serial Peripheral Interface Module (DSPI)

23 Controller Area Network Module (FlexCAN)

24 Inter-Integrated Circuit Bus Module (I

2

C)

25 Periodic Interrupt Timer Module (PIT)

26 System Services Module (SSM)

A Debug Interface

B A7S Nexus 2 Module

C Register Memory Map Quick Reference

D Mask Set Differences Summary

MAC7100 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor v

Contents

Paragraph

Number

Title

Page

Number

Tables............................................................................................................................. xxix

Figures ......................................................................................................................... xxxix

Preface

Document Structure ............................................................................................................ li

How To Use This Document............................................................................................... li

Conventions ....................................................................................................................... lii

Terminology......................................................................................................................liii

Register Descriptions....................................................................................................... lvii

Revision History

Content Changes by Document Version........................................................................... lix

Chapter 1

Introduction

1.1 Overview.......................................................................................................................... 1-1

1.2 Block Diagram................................................................................................................. 1-2

1.3 Features............................................................................................................................ 1-4

1.4 Modes of Operation ......................................................................................................... 1-9

Chapter 2

Signal Description

2.1 External Signal Description........................................................................................... 2-11

2.1.1 Clocks and Control .................................................................................................... 2-11

2.1.1.1 EXTAL, XTAL — Oscillator ................................................................................ 2-11

2.1.1.2 XFC — PLL Loop Filter ....................................................................................... 2-11

2.1.1.3 RESET — External Reset...................................................................................... 2-11

2.1.1.4 TCK — Test Clock................................................................................................ 2-11

2.1.1.5 TMS — Test Mode................................................................................................ 2-11

2.1.1.6 TDI — Test Data In............................................................................................... 2-11

2.1.1.7 TDO — Test Data Out........................................................................................... 2-12

2.1.1.8 TA / AS — Transfer Acknowledge / Address Strobe............................................ 2-12

2.1.1.9 TEST — Factory Test............................................................................................ 2-12

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2.1.1.10 Configuration and Optional Control Signals......................................................... 2-12

2.1.2 General Purpose / Peripheral I/O............................................................................... 2-12

2.1.2.1 Port A Signal Group .............................................................................................. 2-13

2.1.2.2 Port B Signal Group............................................................................................... 2-15

2.1.2.3 Port C Signal Group............................................................................................... 2-16

2.1.2.4 Port D Signal Group .............................................................................................. 2-16

2.1.2.5 Port E Signal Group............................................................................................... 2-17

2.1.2.6 Port F Signal Group............................................................................................... 2-18

2.1.2.7 Port G Signal Group .............................................................................................. 2-18

2.1.2.8 Port H Signal Group .............................................................................................. 2-20

2.1.2.9 Port I Signal Group................................................................................................ 2-20

2.2 Power Supply, Bypass and Reference............................................................................ 2-20

2.2.1 V

DD

X,V

SS

X — I/O Drivers Power and Ground....................................................... 2-20

2.2.2 V

DD

R, V

SS

R — Internal Voltage Regulator Supply ................................................. 2-20

2.2.3 V

DD

A, V

SS

A — Analog Reference Supply .............................................................. 2-21

2.2.4 V

DD

2.5, V

SS

2.5 — Core Power Supply Bypass........................................................ 2-21

2.2.5 V

DD

PLL, V

SS

PLL — PLL Power Supply Bypass.................................................... 2-21

2.2.6 V

RH

, V

RL

— ATD Reference Voltage....................................................................... 2-21

2.3 Signal Properties Summary ........................................................................................... 2-22

2.4 Packaging Options......................................................................................................... 2-27

Chapter 3

Voltage Regulator Module (VREG)

3.1 Overview........................................................................................................................ 3-29

3.2 Features.......................................................................................................................... 3-29

3.3 Modes of Operation ....................................................................................................... 3-31

3.4 Signal Description.......................................................................................................... 3-31

3.4.1 V

DD

R, V

SS

R — Regulator Power Input.................................................................... 3-32

3.4.2 V

DD

A, V

SS

A — Regulator Reference Input ............................................................. 3-32

3.4.3 V

DD

2.5, V

SS

2.5 — Regulator Output 1 (Core Logic)............................................... 3-32

3.4.4 V

DD

PLL, V

SS

PLL — Regulator Output 2 (PLL)...................................................... 3-32

3.5 Memory Map / Register Definition ............................................................................... 3-32

3.5.1 Register Descriptions................................................................................................. 3-33

3.5.1.1 VREG High Temperature Control Register (VREGHTCL).................................. 3-33

3.5.1.2 VREG Control Register (VREGCTRL)................................................................ 3-33

3.5.1.3 VREG Autonomous Periodic Interrupt Control Register (VREGAPICL)............ 3-34

3.5.1.4 VREG Autonomous Periodic Interrupt Trimming Register (VREGAPITR)........ 3-35

3.6 Functional Description................................................................................................... 3-36

3.6.1 REG – Regulator Core............................................................................................... 3-36

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Freescale Semiconductor vii

3.6.1.1 Full Performance Mode.........................................................................................3-36

3.6.1.2 Reduced Power Mode............................................................................................ 3-37

3.6.2 LVD – Low Voltage Detect........................................................................................ 3-37

3.6.3 POR – Power-On Reset ............................................................................................. 3-37

3.6.4 LVR – Low Voltage Reset ......................................................................................... 3-37

3.6.5 CTRL – Regulator Control........................................................................................ 3-37

3.6.6 API – Autonomous Periodic Interrupt....................................................................... 3-37

3.6.7 Resets......................................................................................................................... 3-38

3.6.7.1 Power-On Reset (POR).......................................................................................... 3-38

3.6.7.2 Low-Voltage Reset (LVR) ..................................................................................... 3-38

3.6.8 Interrupts.................................................................................................................... 3-38

3.6.8.1 LVI – Low Voltage Interrupt.................................................................................. 3-38

3.6.8.2 API – Autonomous Periodic Interrupt................................................................... 3-39

3.7 Initialization / Application Information......................................................................... 3-39

3.7.1 Circuit Board Layout................................................................................................. 3-39

Chapter 4

System Clocks Module (OSC and CRG)

4.1 Overview........................................................................................................................ 4-45

4.2 On-Chip Oscillator (OSC) Module................................................................................ 4-47

4.2.1 OSC Overview........................................................................................................... 4-47

4.2.2 OSC Features............................................................................................................. 4-47

4.2.3 OSC Modes of Operation .......................................................................................... 4-48

4.2.4 OSC Signal Description............................................................................................. 4-48

4.2.4.1 V

DD

PLL, V

SS

PLL................................................................................................. 4-48

4.2.4.2 EXTAL, XTAL...................................................................................................... 4-48

4.2.4.3 CLKOUT / XCLKS

............................................................................................... 4-49

4.2.5 OSC Functional Description...................................................................................... 4-50

4.2.5.1 Gain control........................................................................................................... 4-50

4.2.5.2 Clock Monitor........................................................................................................ 4-50

4.3 Clock and Reset Generator (CRG) Module................................................................... 4-50

4.3.1 CRG Overview .......................................................................................................... 4-50

4.3.2 CRG Features............................................................................................................. 4-51

4.3.3 CRG Modes of Operation.......................................................................................... 4-52

4.3.4 CRG Signal Description ............................................................................................ 4-52

4.3.4.1 XFC........................................................................................................................ 4-52

4.3.4.2 RESET

................................................................................................................... 4-53

4.3.4.3 CLKOUT / XCLKS............................................................................................... 4-53

4.3.5 CRG Memory Map / Register Definition.................................................................. 4-53

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viii Freescale Semiconductor

4.3.5.1 CRG Synthesizer Register (SYNR)....................................................................... 4-54

4.3.5.2 CRG Reference Divider Register (REFDV).......................................................... 4-54

4.3.5.3 CRG Flags Register (CRGFLG)............................................................................ 4-55

4.3.5.4 CRG Interrupt Enable Register (CRGINT)........................................................... 4-56

4.3.5.5 CRG Clock Select Register (CLKSEL)................................................................. 4-57

4.3.5.6 CRG PLL Control Register (PLLCTL)................................................................. 4-58

4.3.5.7 CRG Stop/Doze Control Register (SDMCTL)...................................................... 4-59

4.3.5.8 CRG BDM Control Register (BDMCTL)............................................................. 4-60

4.3.6 CRG Functional Description ..................................................................................... 4-60

4.3.6.1 Phase Locked Loop (PLL)..................................................................................... 4-60

4.3.6.2 System Clocks Generator ......................................................................................4-63

4.3.6.3 Clock Monitor (CM).............................................................................................. 4-64

4.3.6.4 Clock Quality Checker .......................................................................................... 4-64

4.3.6.5 Software Watchdog Timer (SWT)......................................................................... 4-66

4.3.6.6 Real Time Interrupt (RTI)...................................................................................... 4-66

4.3.6.7 Resets..................................................................................................................... 4-66

4.3.6.8 Software Watchdog Timer (SWT) Reset............................................................... 4-69

4.3.6.9 Interrupts................................................................................................................ 4-70

4.3.6.10 CRG Operating Mode Details ...............................................................................4-70

4.4 System Clocks Summary............................................................................................... 4-81

Chapter 5

Resets

5.1 Effects of Reset.............................................................................................................. 5-83

5.1.1 I/O pins ...................................................................................................................... 5-83

5.1.2 Memory...................................................................................................................... 5-83

5.2 Keyboard Wake-up on Port Pins.................................................................................... 5-83

Chapter 6

Exceptions

6.1 Exception Vector Assignments...................................................................................... 6-85

Chapter 7

Modes of Operation

7.1 Chip Hardware Configuration Summary....................................................................... 7-87

7.1.1 MCU Mode Selection................................................................................................ 7-87

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MAC7100 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor ix

7.1.1.1 Expanded Modes ...................................................................................................7-88

7.1.1.2 Single-Chip Modes................................................................................................ 7-88

7.1.1.3 Data Flash Boot Mode........................................................................................... 7-88

7.1.2 Oscillator Type Selection........................................................................................... 7-88

7.1.3 External Bus Interface Configuration........................................................................ 7-88

7.1.4 Nexus Port Configuration.......................................................................................... 7-88

7.2 Security.......................................................................................................................... 7-89

7.2.1 Securing the Microcontroller..................................................................................... 7-89

7.2.2 Operation of the Secured Microcontroller................................................................. 7-89

7.2.2.1 Secured Single-Chip Mode.................................................................................... 7-89

7.2.2.2 Secured Expanded Mode....................................................................................... 7-89

7.2.3 Unsecuring the Microcontroller................................................................................. 7-90

7.2.3.1 Backdoor Access Key............................................................................................ 7-90

7.2.3.2 Lockout Recovery Procedure ................................................................................ 7-90

7.3 Power Consumption Considerations.............................................................................. 7-90

7.3.1 Run Mode .................................................................................................................. 7-91

7.3.2 Doze Mode................................................................................................................. 7-91

7.3.3 Stop Mode.................................................................................................................. 7-91

7.3.4 Pseudo-Stop Mode..................................................................................................... 7-91

7.4 Mode and Configuration Identification ......................................................................... 7-91

Chapter 8

Device Memory Map

8.1 Memory Map Details..................................................................................................... 8-93

8.1.1 Normal Single-Chip Mode......................................................................................... 8-95

8.1.2 Secured Single-Chip Mode........................................................................................ 8-95

8.1.3 Normal Expanded Mode............................................................................................ 8-96

8.1.4 Secured Expanded Mode........................................................................................... 8-97

8.1.5 Normal/Secured Data Flash Boot Mode.................................................................... 8-97

8.1.6 Peripheral Bus Memory Map..................................................................................... 8-99

8.2 Accessing Registers..................................................................................................... 8-100

8.2.1 32-Bit Register Accesses......................................................................................... 8-100

8.2.2 16-Bit Register Accesses......................................................................................... 8-100

8.2.3 8-Bit Register Accesses........................................................................................... 8-100

Chapter 9

ARM7TDMI-S™ Processor Core

9.1 Overview...................................................................................................................... 9-101

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MAC7100 Microcontroller Family Reference Manual, Rev. 2

x Freescale Semiconductor

Chapter 10

Interrupt Controller Module (INTC)

10.1 Overview.................................................................................................................... 10-103

10.2 Features...................................................................................................................... 10-104

10.3 Review of ARM7™ Interrupt Architecture............................................................... 10-104

10.4 Signal Description...................................................................................................... 10-105

10.4.1 XIRQ...................................................................................................................... 10-105

10.4.2 IRQ......................................................................................................................... 10-105

10.5 Memory Map / Register Definition ........................................................................... 10-105

10.5.1 Register Descriptions............................................................................................. 10-108

10.5.1.1 INTC Interrupt Pending Register (IPRH, IPRL)............................................... 10-108

10.5.1.2 INTC Interrupt Mask Register (IMRH, IMRL)................................................. 10-109

10.5.1.3 INTC Force Interrupt Register (INTFRCH, INTFRCL)................................... 10-110

10.5.1.4 INTC Module Configuration Register (ICONFIG)............................................10-111

10.5.1.5 INTC Set Interrupt Mask Register (SIMR)....................................................... 10-112

10.5.1.6 INTC Clear Interrupt Mask Register (CIMR)................................................... 10-112

10.5.1.7 INTC Current Level Mask Register (CLMASK).............................................. 10-113

10.5.1.8 INTC Saved Level Mask Register (SLMASK)................................................. 10-114

10.5.1.9 INTC Interrupt Control Registers (ICRn).......................................................... 10-115

10.5.1.10 INTC IRQ Acknowledge Register (IRQIACK)................................................ 10-115

10.5.1.11 INTC FIQ Acknowledge Register (FIQIACK)................................................. 10-116

10.6 Functional Description............................................................................................... 10-116

10.6.1 Interrupt Recognition............................................................................................. 10-117

10.6.2 Interrupt Prioritization and Level Masking ........................................................... 10-117

10.6.3 Vector Generation During IACK........................................................................... 10-117

10.7 Initialization / Application Information..................................................................... 10-119

10.7.1 Typical Applications.............................................................................................. 10-119

10.7.2 Interrupt Service Routines..................................................................................... 10-119

10.7.3 Performance........................................................................................................... 10-121

Chapter 11

Miscellaneous Control Module (MCM)

11.1 Overview.................................................................................................................... 11-123

11.2 Features...................................................................................................................... 11-123

11.3 Memory Map / Register Definition ........................................................................... 11-123

11.3.1 Register Descriptions............................................................................................. 11-124

11.3.1.1 MCM Processor Core Type Register (PCT)...................................................... 11-124

11.3.1.2 MCM Device Revision Register (REV)............................................................ 11-125

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11.3.1.3 MCM XBS Master Configuration Register (AMC).......................................... 11-126

11.3.1.4 MCM XBS Slave Configuration Register (ASC).............................................. 11-126

11.3.1.5 MCM IPS On-Platform Module Configuration Register (IOPMC).................. 11-126

11.3.1.6 MCM Reset Status Register (MRSR)................................................................ 11-127

11.3.1.7 MCM Wake-up Control Register (MWCR) ...................................................... 11-128

11.3.1.8 MCM Software Watchdog Timer Control Register (MSWTCR)...................... 11-129

11.3.1.9 MCM Software Watchdog Timer Service Register (MSWTSR) ...................... 11-131

11.3.1.10 MCM Software Watchdog Timer Interrupt Register (MSWTIR) ..................... 11-132

11.3.1.11 MCM XBS Address Map Register (AAMR) .................................................... 11-132

11.3.1.12 MCM Core Fault Address Register (CFADR) .................................................. 11-135

11.3.1.13 MCM Core Fault Location Register (CFLOC) ................................................. 11-136

11.3.1.14 MCM Core Fault Attributes Register (CFATR) ................................................ 11-137

11.3.1.15 MCM Core Fault Data Register (CFDTR)........................................................ 11-138

11.4 Initialization / Application Information..................................................................... 11-138

11.4.1 Using The PCT And REV Registers...................................................................... 11-138

Chapter 12

Enhanced Direct Memory Access Controller Module (eDMA)

12.1 Overview.................................................................................................................... 12-141

12.2 Features...................................................................................................................... 12-143

12.3 Memory Map / Register Definition ........................................................................... 12-143

12.3.1 Register Descriptions............................................................................................. 12-144

12.3.1.1 eDMA Control Register (DMACR) .................................................................. 12-144

12.3.1.2 eDMA Error Status Register (DMAES)............................................................ 12-145

12.3.1.3 eDMA Enable Request Register (DMAERQ)................................................... 12-147

12.3.1.4 eDMA Enable Error Interrupt Registers (DMAEEI)......................................... 12-148

12.3.1.5 eDMA Set Enable Request Register (DMASERQ)........................................... 12-149

12.3.1.6 eDMA Clear Enable Request Register (DMACERQ)....................................... 12-149

12.3.1.7 eDMA Set Enable Error Interrupt Register (DMASEEI).................................. 12-150

12.3.1.8 eDMA Clear Enable Error Interrupt Register (DMACEEI).............................. 12-150

12.3.1.9 eDMA Clear Interrupt Request Register (DMACINT)..................................... 12-151

12.3.1.10 eDMA Clear Error Register (DMACERR) ....................................................... 12-152

12.3.1.11 eDMA Set START Bit Register (DMASSRT) .................................................. 12-152

12.3.1.12 eDMA Clear DONE Status Register (DMACDNE)..........................................12-153

12.3.1.13 eDMA Interrupt Request Register (DMAINT) ................................................. 12-153

12.3.1.14 eDMA Error Register (DMAERR).................................................................... 12-154

12.3.1.15 eDMA Channel Priority Registers (DCHPRIn) ................................................12-155

12.3.1.16 Transfer Control Descriptors (TCDn)................................................................ 12-156

12.4 Functional Description............................................................................................... 12-163

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12.4.1 eDMA Microarchitecture....................................................................................... 12-163

12.4.2 eDMA Basic Data Flow......................................................................................... 12-164

12.5 Initialization / Application Information..................................................................... 12-167

12.5.1 eDMA Transfer Control Descriptor Header File Example.................................... 12-167

12.5.2 eDMA Basic Channel Operation........................................................................... 12-168

12.5.3 eDMA Initialization Sequence............................................................................... 12-171

12.5.4 eDMA Programming Errors .................................................................................. 12-173

12.5.5 eDMA Arbitration Mode Considerations.............................................................. 12-173

12.5.5.1 Fixed-Priority Arbitration.................................................................................. 12-174

12.5.5.2 Round-Robin Arbitration................................................................................... 12-174

12.5.6 eDMA Transfers .................................................................................................... 12-174

12.5.6.1 Single Request................................................................................................... 12-174

12.5.6.2 Multiple Requests.............................................................................................. 12-175

12.5.6.3 Modulo Operation.............................................................................................. 12-176

12.5.7 eDMA TCDn Status Monitoring ........................................................................... 12-177

12.5.7.1 Minor Loop Complete ....................................................................................... 12-177

12.5.7.2 Active Channel TCDn Reads............................................................................. 12-178

12.5.7.3 Preemption Status.............................................................................................. 12-178

12.5.8 Channel Linking .................................................................................................... 12-178

12.5.9 Dynamic Channel Linking and Scatter/Gather Operation..................................... 12-180

Chapter 13

External Interface Module (EIM)

13.1 Overview.................................................................................................................... 13-181

13.2 Features...................................................................................................................... 13-182

13.3 Modes of Operation ................................................................................................... 13-182

13.4 Signal Description...................................................................................................... 13-183

13.4.1 CLKOUT............................................................................................................... 13-183

13.4.2 Address Bus (ADDR[21:0]) .................................................................................. 13-183

13.4.3 Data Bus (DATA[15:0])......................................................................................... 13-183

13.4.4 Read/Write Signal (R/W)....................................................................................... 13-184

13.4.5 Address Strobe (AS).............................................................................................. 13-184

13.4.6 Transfer Acknowledge (TA).................................................................................. 13-184

13.4.7 Output Enable (OE)............................................................................................... 13-184

13.4.8 Chip Selects (CS[2:0])........................................................................................... 13-184

13.4.9 Byte Selects (BS[1:0]) ........................................................................................... 13-184

13.5 Memory Map / Register Definition ........................................................................... 13-185

13.5.1 Register Descriptions............................................................................................. 13-185

13.5.1.1 EIM Chip Select Address Registers (CSARn) .................................................. 13-185

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13.5.1.2 EIM Chip Select Mask Registers (CSMRn)...................................................... 13-186

13.5.1.3 EIM Chip Select Control Registers (CSCRn) ................................................... 13-187

13.6 Functional Description............................................................................................... 13-189

13.6.1 Chip Select Operation............................................................................................ 13-189

13.6.1.1 8- and 16-Bit Port Sizing................................................................................... 13-191

13.6.1.2 Global Chip Select............................................................................................. 13-191

13.6.2 External Bus Operation.......................................................................................... 13-192

13.6.2.1 Data Transfers.................................................................................................... 13-192

13.6.2.2 Bus Cycle Execution.......................................................................................... 13-193

13.6.2.3 Data Transfer Cycle States................................................................................. 13-194

13.6.2.4 Read Cycle......................................................................................................... 13-195

13.6.2.5 Write Cycle........................................................................................................ 13-196

13.6.2.6 Fast Termination Cycles .................................................................................... 13-197

13.6.2.7 Back-to-Back Bus Cycles.................................................................................. 13-198

13.6.2.8 Burst Cycles....................................................................................................... 13-198

13.7 Initialization / Application Information..................................................................... 13-201

13.7.1 Using Global Chip Select Mode............................................................................ 13-201

13.7.2 Configuring Chip Selects....................................................................................... 13-201

13.7.3 Dynamic Chip Select Configuration...................................................................... 13-202

Chapter 14

Cross-Bar Switch Module (XBS)

14.1 Overview.................................................................................................................... 14-203

14.2 Features...................................................................................................................... 14-203

14.3 Modes of Operation ................................................................................................... 14-204

14.4 Memory Map / Register Definition ........................................................................... 14-204

14.4.1 Register Descriptions............................................................................................. 14-205

14.4.1.1 XBS Priority Registers (PR_port)..................................................................... 14-205

14.4.1.2 XBS Control Registers (CR_port)..................................................................... 14-206

14.5 Functional Description............................................................................................... 14-207

14.5.1 Arbitration.............................................................................................................. 14-207

14.5.1.1 Fixed-Priority Operation.................................................................................... 14-207

14.5.1.2 Round-Robin Priority Operation ....................................................................... 14-208

14.5.1.3 Priority Assignment........................................................................................... 14-208

14.6 Initialization / Application Information..................................................................... 14-208

Contents

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xiv Freescale Semiconductor

Chapter 15

Common Flash Module (CFM)

15.1 Overview.................................................................................................................... 15-209

15.2 Features...................................................................................................................... 15-211

15.3 Memory Map / Register Definition ........................................................................... 15-212

15.3.1 Register Descriptions............................................................................................. 15-214

15.3.1.1 CFM Module Configuration Register (CFMMCR)........................................... 15-214

15.3.1.2 CFM Clock Divider Register (CFMCLKD)...................................................... 15-216

15.3.1.3 CFM Security Register (CFMSEC)................................................................... 15-217

15.3.1.4 CFM Program Flash Protection Register (CFMPROT) .................................... 15-218

15.3.1.5 CFM Data Flash Protection Register (CFMDFPROT) ..................................... 15-220

15.3.1.6 CFM Program Flash Supervisor Access Register (CFMSACC)....................... 15-221

15.3.1.7 CFM Data Flash Supervisor Access Register (CFMDFSACC)........................ 15-221

15.3.1.8 CFM Program Flash Data Access Register (CFMDACC)................................ 15-222

15.3.1.9 CFM Data Flash Data Access Register (CFMDFDACC)................................. 15-223

15.3.1.10 CFM User Status Register (CFMUSTAT)......................................................... 15-223

15.3.1.11 CFM Command Register (CFMCMD).............................................................. 15-225

15.3.1.12 CFM Data Registers (CFMDATA1/0)............................................................... 15-225

15.3.1.13 CFM Disable Upper Block Register (CFMDISU) ............................................ 15-226

15.3.1.14 CFM Clock Select Register (CFMCLKSEL).................................................... 15-227

15.4 Functional Description............................................................................................... 15-227

15.4.1 Flash Normal Mode............................................................................................... 15-227

15.4.1.1 Read Operation.................................................................................................. 15-228

15.4.1.2 Write Operation .................................................................................................15-228

15.4.1.3 Command Launch Sequence ............................................................................. 15-228

15.4.1.4 Initializing the CFMCLKD Register................................................................. 15-229

15.4.1.5 Program, Erase, and Verify Operations ............................................................. 15-231

15.4.1.6 Flash Normal Mode Illegal Operations ............................................................. 15-246

15.4.1.7 Stop Mode.......................................................................................................... 15-246

15.4.2 Flash Security Operation ....................................................................................... 15-247

15.4.2.1 Backdoor Access Sequence............................................................................... 15-247

15.4.2.2 Blank Check....................................................................................................... 15-248

15.4.2.3 JTAG Lockout Recovery................................................................................... 15-248

15.5 Initialization / Application Information..................................................................... 15-248

15.5.1 Using The Data Signature Command.................................................................... 15-248

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Freescale Semiconductor xv

Chapter 16

AMBA to IP Bus Bridge Module (AIPS)

16.1 Overview.................................................................................................................... 16-251

16.2 Features...................................................................................................................... 16-251

16.3 Modes of Operation ................................................................................................... 16-251

16.4 Memory Map / Register Definition ........................................................................... 16-253

16.4.1 Register Descriptions............................................................................................. 16-255

16.4.1.1 AIPS Master Protection Registers (MPRx) ....................................................... 16-255

16.4.1.2 AIPS Peripheral Access Control Registers (PACRx)........................................ 16-255

16.4.1.3 AIPS Off-Platform Peripheral Access Control Registers (OPACRx)................ 16-256

16.5 Functional Description............................................................................................... 16-257

16.5.1 Access Protections................................................................................................. 16-257

16.5.2 Access Support ...................................................................................................... 16-257

16.5.3 Read Cycles ........................................................................................................... 16-257

16.5.4 Write Cycles........................................................................................................... 16-257

16.5.5 Aborted Cycles ...................................................................................................... 16-257

16.6 Initialization / Application Information..................................................................... 16-258

Chapter 17

DMA Channel Multiplexer Module (DMAMux)

17.1 Overview.................................................................................................................... 17-259

17.2 Features...................................................................................................................... 17-259

17.3 Modes of Operation ................................................................................................... 17-260

17.4 Memory Map / Register Definition ........................................................................... 17-260

17.4.1 Register Descriptions............................................................................................. 17-261

17.4.1.1 DMAMux Channel Configuration Registers (CHCONFIGn)........................... 17-261

17.5 Functional Description............................................................................................... 17-262

17.5.1 eDMA Channels 0 to 7 .......................................................................................... 17-263

17.5.2 eDMA Channels 8 to 15 ........................................................................................ 17-264

17.5.3 Always Enabled DMA Request Sources............................................................... 17-265

17.6 Initialization / Application Information..................................................................... 17-266

17.6.1 Simple Setup.......................................................................................................... 17-266

17.6.1.1 Configure eDMA Channel 0 to Service eSCI_A Transmit Requests................ 17-266

17.6.2 Using the “Always Enabled” Feature to Periodically Drive GPIO Pins ............... 17-267

17.6.3 Disabling a Source................................................................................................. 17-267

17.6.4 Enable Source With Periodic Triggering............................................................... 17-268

17.6.4.1 DSPI Channel Configured For Periodic Service .............................................. 17-268

17.6.5 Enable Source With Transparent Triggering ......................................................... 17-268

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xvi Freescale Semiconductor

17.6.5.1 DSPI Channel Configured for Immediate Service ........................................... 17-269

17.6.6 Switching DMA Request Source to eDMA Channel Assignment........................ 17-269

17.6.6.1 Switch eDMA Channel 9 from DSPI_A Transmit to eSCI_D Transmit........... 17-270

Chapter 18

Port Integration Module (PIM)

18.1 Overview.................................................................................................................... 18-271

18.2 Features...................................................................................................................... 18-273

18.3 Modes of Operation ................................................................................................... 18-273

18.4 Signal Description...................................................................................................... 18-273

18.5 Memory Map / Register Definition ........................................................................... 18-276

18.5.1 Register Descriptions............................................................................................. 18-286

18.5.1.1 PIM Port x Pin Configuration Registers (CONFIGn_x).................................... 18-286

18.5.1.2 PIM Port x Interrupt Flag Register (PORTIFR_x)............................................. 18-287

18.5.1.3 PIM Port x Data Register (PORTDATA_x)....................................................... 18-288

18.5.1.4 PIM Port x Input Register (PORTIR_x)............................................................. 18-288

18.5.1.5 PIM Port x Pin Data Registers (PINDATAn_x)................................................. 18-289

18.5.1.6 PIM Global Interrupt Status Register (GLBINT).............................................. 18-289

18.5.1.7 PIM Global Configuration Register (PIMCONFIG)......................................... 18-290

18.5.1.8 PIM Configure TDI Pin Register (CONFIG_TDI) ...........................................18-291

18.5.1.9 PIM Configure TDO Pin Register (CONFIG_TDO) ........................................ 18-292

18.5.1.10 PIM Configure TMS Pin Register (CONFIG_TMS) ........................................ 18-293

18.5.1.11 PIM Configure TCK Pin Register (CONFIG_TCK)......................................... 18-294

18.5.1.12 PIM Configure TA / AS Pin Register (CONFIG_TA)....................................... 18-294

18.5.1.13 PIM Port x/x 32-bit Input Registers (PORT32IR_xx)........................................ 18-295

18.6 Functional Description............................................................................................... 18-296

18.6.1 Reset....................................................................................................................... 18-296

18.6.2 Peripheral Mode..................................................................................................... 18-296

18.6.3 General Purpose Input Mode................................................................................. 18-298

18.6.3.1 Interrupts............................................................................................................ 18-299

18.6.4 General Purpose Output Mode .............................................................................. 18-301

18.7 Initialization / Application Information..................................................................... 18-303

18.7.1 Using a Pin in Peripheral Mode............................................................................. 18-303

18.7.1.1 PIM Example — Enable the I

2

C module .......................................................... 18-303

18.7.2 Using a Pin in GPIO Mode.................................................................................... 18-304

18.7.2.1 GPIO Mode Initialization.................................................................................. 18-304

18.7.2.2 PIM Example — Use PB[1:0] in GPO/GPI Mode............................................ 18-304

18.7.2.3 Accessing Data .................................................................................................. 18-305

18.7.2.4 Using Port Interrupts.......................................................................................... 18-309

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Freescale Semiconductor xvii

18.7.3 PD2 / CLKOUT Configuration.............................................................................. 18-313

18.7.3.1 Using PD2 GPI Functionality............................................................................ 18-313

18.7.3.2 Using CLKOUT Functionality.......................................................................... 18-313

18.7.4 TA / AS Configuration........................................................................................... 18-314

18.7.5 E-ICE JTAG Port Configuration............................................................................ 18-314

18.7.6 Using the PIMCONFIG Register........................................................................... 18-314

18.7.6.1 Using the PORTHSEL Bit................................................................................. 18-315

18.7.6.2 Using the EIMCLKEN Bit ................................................................................ 18-315

18.7.7 Minimizing Power Consumption........................................................................... 18-315

Chapter 19

Analog-to-Digital Converter Module (ATD)

19.1 Overview.................................................................................................................... 19-317

19.2 Features...................................................................................................................... 19-318

19.3 Modes of Operation ................................................................................................... 19-319

19.4 Signal Description...................................................................................................... 19-319

19.4.1 ANn_x.................................................................................................................... 19-320

19.4.2 V

RH

/ V

RL

.............................................................................................................. 19-320

19.4.3 V

DD

A / V

SS

A......................................................................................................... 19-320

19.5 Memory Map / Register Definition ........................................................................... 19-320

19.5.1 Register Descriptions............................................................................................. 19-321

19.5.1.1 ATD Trigger Control Register (ATDTRIGCTL)............................................... 19-321

19.5.1.2 ATD External Trigger Channel Register (ATDETRIGCH)............................... 19-322

19.5.1.3 ATD Prescaler Register (ATDPRE)................................................................... 19-323

19.5.1.4 ATD Operating Mode Register (ATDMODE)................................................... 19-324

19.5.1.5 ATD Interrupt Register (ATDINT).................................................................... 19-325

19.5.1.6 ATD Flag Register (ATDFLAG) ....................................................................... 19-326

19.5.1.7 ATD Command Word Register (ATDCW)........................................................ 19-328

19.5.1.8 ATD Result Register (ATDRR)......................................................................... 19-330

19.6 Functional Description............................................................................................... 19-333

19.6.1 General................................................................................................................... 19-333

19.6.2 Analog Sub-Module............................................................................................... 19-333

19.6.2.1 Analog Input Multiplexer.................................................................................. 19-333

19.6.2.2 Sample Buffer Amplifier................................................................................... 19-333

19.6.2.3 Sample and Hold Machine................................................................................. 19-334

19.6.2.4 DAC................................................................................................................... 19-334

19.6.2.5 Comparator........................................................................................................ 19-334

19.6.2.6 Schmitt Trigger.................................................................................................. 19-334

19.6.3 Digital Sub-Module ............................................................................................... 19-334

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xviii Freescale Semiconductor

19.6.3.1 Mode / Timing Control...................................................................................... 19-334

19.6.3.2 Clock Prescaler..................................................................................................19-334

19.6.3.3 IPS Bus Interface............................................................................................... 19-335

19.6.3.4 SYSTRIG0, SYSTRIG1, External Trigger Input..............................................19-335

19.6.4 ATD Operating Mode Details................................................................................ 19-335

19.6.4.1 ATD Normal Mode............................................................................................ 19-335

19.6.4.2 ATD Debug Mode.............................................................................................. 19-335

19.6.4.3 ATD Disabled Mode.......................................................................................... 19-336

19.6.4.4 ATD Doze Mode................................................................................................ 19-336

19.6.4.5 ATD Stop Mode................................................................................................. 19-337

19.6.5 Conversion process................................................................................................ 19-337

19.6.6 Reset....................................................................................................................... 19-340

19.6.7 Interrupts................................................................................................................ 19-340

19.7 Initialization / Application Information..................................................................... 19-341

19.7.1 ATD Initialization Sequence.................................................................................. 19-341

19.7.2 ATD Example 1 — Simple Conversion................................................................. 19-341

19.7.3 ATD Example 2 — Three Consecutive Conversions ............................................ 19-342

19.7.4 ATD Example 3 — Interrupted Continuous Conversion....................................... 19-343

19.7.5 ATD Example 4 — Edge Triggered Conversion................................................... 19-343

19.7.6 ATD Example 5 — Level Triggered Conversion.................................................. 19-344

19.7.7 ATD Example 6 — Using External Triggers......................................................... 19-345

19.7.8 ATD Example 7 — Using System Triggers........................................................... 19-345

19.7.9 Conversion Mechanism — CWCH, CWNF, CWGI and CWSC Bits................... 19-346

19.7.10 Conversion Mechanism — CWSL, CWSB and CW8 Bits................................... 19-347

19.7.11 Measuring Internal Reference Voltages................................................................. 19-348

Chapter 20

Enhanced Modular I/O Subsystem Module (eMIOS)

20.1 Overview.................................................................................................................... 20-351

20.2 Features...................................................................................................................... 20-352

20.3 Modes of Operation ................................................................................................... 20-352

20.4 Signal Description...................................................................................................... 20-353

20.4.1 emiosin — eMIOS Unified Channel n Input Signal.............................................. 20-353

20.4.2 emioson — eMIOS Unified Channel n Output Signal.......................................... 20-353

20.5 Memory Map / Register Definition ........................................................................... 20-353

20.5.1 Register Descriptions............................................................................................. 20-354

20.5.1.1 eMIOS Module Configuration Register (MCR)................................................ 20-354

20.5.1.2 eMIOS Global Flag Register (GFLAG)............................................................ 20-355

20.5.1.3 eMIOS Output Update Disable Register (OUDIS) ...........................................20-356

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20.5.1.4 eMIOS Channel Disable Register (UCDIS)...................................................... 20-356

20.5.1.5 eMIOS Channel A Data Registers (UCAn)....................................................... 20-357

20.5.1.6 eMIOS Channel B Data Registers (UCBn) ....................................................... 20-358

20.5.1.7 eMIOS Channel Counter Registers (UCCNTn)................................................ 20-359

20.5.1.8 eMIOS Channel Control Registers (UCCRn).................................................... 20-359

20.5.1.9 eMIOS Channel Status Registers (UCSRn) ...................................................... 20-363

20.6 Functional Description............................................................................................... 20-364

20.6.1 eMIOS Operating Mode Details............................................................................ 20-364

20.6.1.1 eMIOS Normal Mode........................................................................................ 20-364

20.6.1.2 eMIOS Debug Mode.......................................................................................... 20-365

20.6.1.3 eMIOS Disabled Mode...................................................................................... 20-365

20.6.1.4 eMIOS Doze Mode............................................................................................ 20-365

20.6.1.5 eMIOS Stop Mode............................................................................................. 20-365

20.6.2 IP Bus Interface Unit (BIU)................................................................................... 20-365

20.6.2.1 Effect of Debug Mode on the BIU.....................................................................20-366

20.6.3 Global Clock Prescaler (GCP) Submodule............................................................ 20-366

20.6.3.1 Effect of Debug Mode on the GCP.................................................................... 20-366

20.6.4 Unified Channel (UC)............................................................................................ 20-366

20.6.4.1 Effect of Debug Mode on Unified Channels..................................................... 20-366

20.6.5 Clock Prescaler (CP).............................................................................................. 20-367

20.6.6 Input Programmable Filter (IPF) ........................................................................... 20-368

20.6.7 UC Modes of Operation......................................................................................... 20-368

20.6.7.1 General Purpose Input/Output (GPIO) Mode.................................................... 20-369

20.6.7.2 Single Action Input Capture (SAIC) Mode....................................................... 20-369

20.6.7.3 Single Action Output Compare (SAOC) Mode................................................. 20-369

20.6.7.4 Input Pulse Width Measurement (IPWM) Mode............................................... 20-370

20.6.7.5 Input Period Measurement (IPM) Mode............................................................ 20-371

20.6.7.6 Double Action Output Compare (DAOC) Mode............................................... 20-372

20.6.7.7 Pulse/Edge Accumulation (PEA) Mode............................................................ 20-373

20.6.7.8 Pulse/Edge Counting (PEC) Mode.................................................................... 20-375

20.6.7.9 Quadrature Decode (QDEC) Mode................................................................... 20-376

20.6.7.10 Windowed Programmable Time Accumulation (WPTA) Mode........................ 20-378

20.6.7.11 Modulus Counter (MC) Mode........................................................................... 20-379

20.6.7.12 Output Pulse Width and Frequency Modulation (OPWFM) Mode................... 20-380

20.6.7.13 Center Aligned Output Pulse Width Modulation (OPWMC) Mode ................. 20-383

20.6.7.14 Output Pulse Width Modulation (OPWM) Mode.............................................. 20-385

20.6.7.15 Modulus Counter, Buffered (MCB) Mode ........................................................ 20-386

20.6.7.16

Output Pulse Width and Frequency Modulation, Buffered (OPWFMB) Mode

.. 20-389

20.6.7.17

Center Aligned Output Pulse Width Modulation, Buffered (OPWMCB) Mode

. 20-393

20.6.7.18 Output Pulse Width Modulation, Buffered (OPWMB) Mode........................... 20-398

20.7 Initialization / Application Information..................................................................... 20-401

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xx Freescale Semiconductor

20.7.1 Changing UC Mode Considerations...................................................................... 20-402

20.7.2 Correlated Output Signal Generation .................................................................... 20-402

20.7.3 Time Base Generation............................................................................................ 20-402

Chapter 21

Enhanced Serial Communications Interface Module (eSCI)

21.1 Overview.................................................................................................................... 21-405

21.2 Features...................................................................................................................... 21-406

21.2.1 LIN support............................................................................................................ 21-406

21.3 Modes of Operation ................................................................................................... 21-407

21.4 Signal Description...................................................................................................... 21-407

21.4.1 TXD_x — SCI Transmit Data ............................................................................... 21-407

21.4.2 RXD_x — SCI Receive Data................................................................................. 21-407

21.5 Memory Map / Register Definition ........................................................................... 21-407

21.5.1 Register Descriptions............................................................................................. 21-408

21.5.1.1 eSCI Baud Rate Registers (ESCIBDH, ESCIBDH).......................................... 21-408

21.5.1.2 eSCI Control Registers (ESCICR1 through ESCICR4).................................... 21-409

21.5.1.3 eSCI Data Registers (ESCIDRH, ESCIDRL) ...................................................21-414

21.5.1.4 eSCI Status Registers (ESCISR1, ESCISR2).................................................... 21-415

21.5.1.5 LIN Status Registers (LINSTAT1, LINSTAT2)................................................. 21-417

21.5.1.6 LIN Control Registers (LINCTRL1, LINCTRL2, LINCTRL3)....................... 21-418

21.5.1.7 LIN TX Register (LINTX) ................................................................................ 21-420

21.5.1.8 LIN RX Register (LINRX)................................................................................ 21-423

21.5.1.9 LIN CRC Polynomial Registers (LINCRCP1, LINCRCP2)............................. 21-423

21.6 Functional Description............................................................................................... 21-424

21.6.1 Overview................................................................................................................ 21-424

21.6.2 Data Format ........................................................................................................... 21-424

21.6.3 Baud Rate Generation............................................................................................ 21-425

21.6.4 Transmitter............................................................................................................. 21-426

21.6.5 Transmitter Character Length................................................................................ 21-427

21.6.6 Character Transmission .........................................................................................21-427

21.6.7 Break Characters.................................................................................................... 21-428

21.6.8 Idle Characters....................................................................................................... 21-429

21.6.9 Fast Bit Error Detection......................................................................................... 21-429

21.6.10 Receiver................................................................................................................. 21-430

21.6.11 Receiver Character Length .................................................................................... 21-430

21.6.12 Character Reception............................................................................................... 21-431

21.6.13 Data Sampling........................................................................................................ 21-431

21.6.14 Framing Errors....................................................................................................... 21-435

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