Analog Devices ADAR1000-EVALZ User manual

Brand: Analog Devices

Model: ADAR1000-EVALZ

Type: User manual

ADAR1000-EVALZ User Guide

UG-1283

One Technology Way • P. O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

Evaluating the ADAR1000 8 GHz to 16 GHz, 4-Channel, X Band and Ku Band

Beamformer

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT

WARNING AND LEGAL TERMS AND CONDITIONS.

Rev. 0 | Page 1 of 18

FEATURES

Based on the ADAR1000 4-channel beamformer core chip

Controllable through SPI

Multiple forms of digital interface (3.3 V and 1.8 V logic)

On-board logic level translators with 1.8 V low dropout

regulator for supply

Software control from a Windows-based PC through USB

ADDITIONAL EQUIPMENT

PC running Windows XP or a more recent software version

SDP-S or SDP-B USB interface board

Network analyzer

Power supplies: +3.3 V, −5.0 V

DOCUMENTS NEEDED

ADAR1000 data sheet

REQUIRED SOFTWARE

ADAR1000.exe

GENERAL DESCRIPTION

The ADAR1000-EVA LZ evaluation board is designed for

evaluating the performance of the ADAR1000, a 4-channel,

X band and Ku band beamforming core chip for radar systems.

All the radio frequency (RF) input/output channels and detector

inputs are brought out to Subminiature Version A (SMA)

connectors. On-board logic level translators convert the on-chip

1.8 V logic signals to 3.3 V for interfacing to external controllers

running on 3.3 V. Two identical 20-pin, dual row rectangular

headers provide the digital interface signals to allow daisy-

chaining up to four ADAR1000-EVA LZ evaluation boards

together. A 24-pin connector provides control and bias outputs

to interface to four external transmit and receive (T/R) modules

with each ADAR1000-EVA LZ evaluation board.

The ADAR1000-EVA L Z evaluation board can be used with an

Analog Devices, Inc., system demonstration platform (SDP) SDP-S

or SDP-B board (supplied separately), which allows connection

to a Microsoft Windows®-based PC through the USB for

controlling of all the ADAR1000 device functions.

For full details on the ADAR1000, see the ADAR1000

data

sheet, which should be consulted in conjunction with this user

guide when using this evaluation board.

EVALUATION BOARD PHOTOGRAPH

16788-001

Figure 1.

UG-1283 ADAR1000-EVALZ User Guide

Rev. 0 | Page 2 of 18

TABLE OF CONTENTS

Features .......................................................................................... 1

Additional Equipment ................................................................. 1

Documents Needed ...................................................................... 1

Required Software ........................................................................ 1

General Description ..................................................................... 1

Evaluation Board Photograph ..................................................... 1

Revision History ........................................................................... 2

Evaluation Board Hardware ........................................................ 3

Power Supply Requirements ................................................... 3

Radio Frequency Input and Output Signals ......................... 3

Digital Input and Outputs ....................................................... 4

T/R Module Control Signals ................................................... 5

Evaluation Board Software Installation ..................................... 7

Test Procedure ............................................................................... 8

Evaluation Board Software .......................................................... 9

Connection Tab ........................................................................ 9

Tx Control Tab ........................................................................ 10

TX Registers Tab ..................................................................... 10

Rx Control Tab ........................................................................ 11

RX Registers Tab ..................................................................... 11

T/R Control Tab ...................................................................... 12

GPIO Tab ................................................................................. 12

MISC Tab ................................................................................. 13

Beam Sequencer Tab .............................................................. 14

Phase Loop Tab ....................................................................... 14

Manual Register Write Tab .................................................... 15

ReadBack Tab .......................................................................... 15

Evaluation Board Schematics and Artwork ............................ 16

REVISION HISTORY

6/2018—Revision 0: Initial Version

ADAR1000-EVALZ User Guide UG-1283

Rev. 0 | Page 3 of 18

EVALUATION BOARD HARDWARE

Figure 1 shows the ADAR1000-EVA LZ evaluation board, with

thirteen high frequency connectors for the four transmit

outputs, four receive inputs, four detector inputs, and a common

RF input and output. Four on-board banana jacks provide

power supply connections and a connector for an SDP adapter

board that interfaces with the USB on a Windows-based PC.

Dual row, square pin headers allow connections to four T/R

modules, as well as the daisy chaining of up to four ADAR1000-

EVA LZ evaluation boards together.

The ADAR1000-EVA LZ evaluation board requires an SDP-S or

SDP-B adapter board to program the device. The PC control

software and the examples provided in this document both make

use of this SDP connection. The SDP adapters are not included

with the ADAR1000-E VAL Z evaluation board, but these adapters

are available through local Analog Devices distributors, as well as

on the SDP product page.

The interface signals on the ADAR1000 core chip, plus additional

digital interface circuitry, are made available on the ADAR1000-

EVA LZ evaluation board, as shown in Figure 2.

POWER SUPPLY REQUIREMENTS

The ADAR1000-EVA LZ evaluation board is powered via two

external supplies (see Table 1). Connections to the ADAR1000-

EVA LZ evaluation board are described in the Test Procedure

section. The −3.3 V banana jack has no function and this

connection is not needed.

Table 1. External Supply Details

External Supply Capacity

AVDD +3.3 V (600 mA)

AVDD1

−5.0 V (50 mA)

RADIO FREQUENCY INPUT AND OUTPUT SIGNALS

The ADAR1000-EVA LZ evaluation board has 13 edge mounted

SMA connectors for RF inputs and outputs (see Table 2).

Table 2. SMA Connectors

Connector Description

RF_IO

Common RF output

connector in receive mode

and common RF input

connector for transmit mode

RX1 to RX4

Receive channel inputs to

connect to antennas or low

noise amplifiers (LNAs)

TX1 to TX4

Transmit channel outputs to

connect to antennas or

power amplifiers (PAs)

DET1 to DET4

Detector inputs designed for

measuring the sampled level

of each RF output channel.

P10 ADDRESS

SELECTION

P6 1.8V

DIGITAL

INTERFACE

P5 SDP

INTERFACE

POWER

SUPPLIES

THROUGH

LINE

TX4

DET4

DET3

RF_IO

RX2

TX2

DET2

RX1

TX1

DET1

P3 PMOD

INTERFACE

P9 T/R

MODULE INTERFACE

P1/P2 DAISY-CHAIN

DIGITAL INTERFACE

THROUGH LINE

RX4

+3.3V –5V 0VNOT

USED

RX3

TX3

16788-002

Figure 2. ADAR1000-EVALZ Evaluation Board Connections

UG-1283 ADAR1000-EVALZ User Guide

Rev. 0 | Page 4 of 18

USB

SDP

ADAPTER

RF_IO

RX1

NETWORK

ANALYZER

+3.3V –5V GND–3.3V

16788-003

Figure 3. Typical Evaluation Board Setup

DIGITAL INPUT AND OUTPUTS

SDP Connector

The J5 connector interfaces to the SDP adapter that connects

to a Windows-based PC. A detailed description of the SDP

adapter is found in the SDP-S Controller Board user guide.

All internal registers and control functions of the ADAR1000-

EVALZ evaluation board are driven from the PC using the

evaluation software.

Daisy-Chain Interface Connectors

The 20-pin connectors (P1 and P2) also carry the digital signals

for controlling the ADAR1000. The two connectors have

identical pinouts, and the connectors daisy-chain up to four

ADAR1000-EVALZ evaluation boards controlled through a

single USB interface. All signals on these connectors except

Pin 15 operate at 3.3 V logic levels, and these signals pass

through 3.3 V to 1.8 V logic translators before connecting to the

digital pins on the ADAR1000, which operate at 1.8 V logic

levels. The serial data output (SDO) pin from each ADAR1000,

with its 1.8 V logic levels, can be tied together through the daisy

chain (Pin 15 on P1 and P2) by installing a 0 Ω resistor jumper

(R36). The pinout of P1 and P2 is shown in Table 3.

The TR, TX_LOAD, RX_LOAD, and PA_ON pins on the

ADAR1000 are also controlled by software via general purpose

input output (GPIO) lines on the SDP connector and 3.3 V to

1.8 V level shifters.

Table 3. Pinout for Digital Interface Connectors P1 and P2

Signal Name Function

1 AGND Analog ground

2 AGND Analog ground

3 AVDD 3.3 V supply

4 AVDD 3.3 V supply

5 AVDD 3.3 V supply

AGND

Analog ground

7 AVDD1 −5 V supply

8 No Connect Not used

9 GPIO0 RX_LOAD input (3.3 V logic)

10 GPIO1 TX_LOAD input (3.3 V logic)

GPIO2

AD0 (chip Address 0) input (3.3 V logic)

12 GPIO3 AD1 (chip Address 1) input (3.3 V logic)

13 GPIO4 TR input (3.3 V logic)

14 GPIO5 PA_ON input (3.3 V logic)

15 SDO Device serial data output (1.8 V logic)

16 SPI_CLK Serial clock input (3.3 V logic)

SPI_MOSI

Serial data input (3.3 V logic)

18 SPI_SEL_A

Serial enable input, active low (3.3 V

logic)

19 SPI_MISO Serial data output (3.3 V logic)

20 AGND Analog ground

3.3 V logic, unless noted otherwise.

Device Interface with 1.8 V Logic Levels

Logic signals on the ADAR1000 are brought to an optional

connector, P6, to allow direct interface to the device using 1.8 V

logic signals. To operate in this mode, the logic level translators

(U2, U4, and U5) must be disabled using the J4, J5, J7, and J9

jumpers. The pinout for connector P6 is shown in Table 4.

ADAR1000-EVALZ User Guide UG-1283

Rev. 0 | Page 5 of 18

Table 4. Pinout for 1.8 V Logic Connector P6

Pin Signal Name Function

1 CSB Serial port enable input (active low)

2 AGND Analog ground

3 SDIO Serial data input and output

4 AGND Analog ground

5 SDO Serial data output

6 AGND Analog ground

7 SCLK Serial clock input

8 AGND Analog ground

9 TR Transmit and receive switching input

AGND

Analog ground

11 TX_LOAD Load transmit configurations input

12 AGND Analog ground

13 RX_LOAD Load receive configurations input

14 AGND Analog ground

15 PA_ON PA bias enable input

AGND

Analog ground

Board Address Selection

The ADAR1000 supports up to four devices on the same serial

peripheral interface (SPI) connection, with each device

identified by the address bits (AD1 and AD0). Jumper Block

P10 selects the source that determines these two bits, as shown

in Tabl e 5.

Table 5. Jumper Block P10 Selections

Jumper Connection Function

Position 1 to Position 3 AD1 is controlled by SDP GPIO2

Position 3 to Position 5 AD1 = high

Position 3 (Not Connected) AD1 = low

Position 2 to Position 4

AD0 is controlled by SDP GPIO3

Position 4 to Position 6 AD0 = high

Position 4 (Not Connected) AD0 = low

Pmod™ Compatible Interface

The 3.3 V digital interface signals are also repeated on

Connector P3, arranged to be compatible with the Pmod

interface connector available on many field programmable gate

array (FPGA) evaluation kits or modules. Appropriate FPGA

programming is required to use this function. The pinout of the

P3 connector is shown in Table 6.

Table 6. Pmod Compatible Interface (P3)

Pin Signal

1 GPIO0 (RX_LOAD)

2 SPI_SEL_A

3 GPIO1 (TX_LOAD)

4 SPI_MOSI

5 GPIO4 (TR)

6 SPI_MISO

7 GPIO5 (PA_ON)

8 SPI_CLK

9 AGND

AGND

11 No connect

12 No connect

T/R MODULE CONTROL SIGNALS

The ADAR1000 controls the operation of four T/R modules,

which typically contain an LNA, a PA, a T/R selection switch,

and possibly a polarization selection switch. The 24-pin header,

P9, contains signals in groups of six to control the four T/R

modules. The pinout of P9 is shown in Table 7.

Table 7. T/R Module Interface Connector (P9) Pin Out

Pin Signal

TR_SW_NEG

2 LNA_BIAS

3 TR_SW_POS

4 TR_POL

5 PA_BIAS4

6 AGND

7 TR_SW_NEG

8 LNA_BIAS

9 TR_SW_POS

10 TR_POL

11 PA_BIAS3

AGND

13 TR_SW_NEG

14 LNA_BIAS

15 TR_SW_POS

16 TR_POL

17 PA_BIAS2

AGND

19 TR_SW_NEG

20 LNA_BIAS

21 TR_SW_POS

22 TR_POL

PA_BIAS1

24 AGND

UG-1283 ADAR1000-EVALZ User Guide

Rev. 0 | Page 6 of 18

The ADAR1000-EVA LZ evaluation board has eight signals for

driving switches and biasing amplifiers on T/R modules available

on Connector P9 (see Tabl e 8). Switch driver outputs as well as

LNA bias output are common to all four channels, while each

PA has its own bias output.

Table 8. T/R Module Interface Signal Descriptions

Signal Description

TR_SW_NEG 0 V to −5 V output to drive an external T/R switch

TR_SW_POS 0 V to 3.3 V output to drive an external T/R switch

TR_POL 0 V to −5 V output to drive an external antenna polarization switch

LNA_BIAS Provides a common bias control voltage (0 V to −4.8 V) for external LNAs

PA1_BIAS to PA4_BIAS Provide individual bias control voltage (0 V to −4.8 V) for each of four PAs

ADAR1000-EVALZ User Guide UG-1283

Rev. 0 | Page 7 of 18

EVALUATION BOARD SOFTWARE INSTALLATION

To install the ADAR1000-EVA LZ evaluation board software,

take the following steps:

1. The evaluation software archive is available for download

on the ADAR1000 evaluation kit product page.

2. Save the adar1000_eb_sw_2p1p0.zip to the Downloads

folder or any other convenient location (see Figure 4).

Navigate to that location using File Manager, and double-

click the file name to open it.

16788-104

Figure 4. Saving Downloaded Control Software Archive

3. File Manager then shows the content of the archive, as

shown in Figure 5.

16788-105

Figure 5. Unpacking Software Archive

4. Double-click on the filename EV-ADAR1000_2p1p0.exe

to start installation. Click Yes when asked to allow the

program to make modifications to the PC. Administrator

privileges may be required to complete the step.

5. After the application is installed, ADAR1000 is available

from the Start menu under the Analog Devices folder.

UG-1283 ADAR1000-EVALZ User Guide

Rev. 0 | Page 8 of 18

TEST PROCEDURE

To use the ADAR1000-EVALZ evaluation board, take the

following steps:

1. Plug the SDP adapter into the P5 connector on the

ADAR1000-EVALZ evaluation board.

2. Connect the +3.3 V and −5 V power supplies to the

corresponding banana jacks on the ADAR1000-EVALZ

evaluation board.

3. Connect the SDP adapter through a USB cable to the PC

with the evaluation software.

4. Connect one port of the network analyzer to the RF_IO

connector and another port to the RX1 input connector.

5. Use the Start menu to run the ADAR1000 evaluation

software (see the Evaluation Board Software Installation

section for more information), as shown in Figure 6.

16788-106

Figure 6. Run Control Software from the Start Menu

6. Once the ADAR1000 evaluation software starts up, click

the Connection tab and then click Connect.

7. Ensure that SDP board connected appears on the status bar.

8. Use the File dropdown menu to select Load Configuration,

and load the ADAR1000_software_settings_v0.1.0.txt file

to initialize all program settings.

9. Select the Manual Register Write tab, and click Use Input

File to select the RX1_MaxG_45.txt file for the register

values.

10. Click Write All to send the register values to the ADAR1000.

Receive Channel 1 is now turned on at full gain.

11. Measure the gain and return loss on the network analyzer. A

typical response is shown in Figure 7.

6 7 8 9 10 11 12

FREQUENCY (GHz)

13 14 15 16 17 18

GAINAND RETURN LOSSES (dB)

–5

–10

–15

–20

MEASURED GAIN

RX1 RETURN LOSS

RF_IO RETURN LOSS

16788-004

Figure 7. Receive Mode Gain and Return Loss Measurement Results

12. For transmit mode operation, disconnect the RX1 port and

connect the RX1 port to the TX1 output connector.

13. Click the T/R Control tab, under the TX Enable section,

select CH1 TX EN, TX DRV EN, TX VM EN, and TX

VGA EN, and then click Write Enable Values to load the

settings.

14. In the Switch Control section of the T/R Control tab,

select TX EN and TR SPI, and then click Write Switch

Values to load settings.

ADAR1000-EVALZ User Guide UG-1283

Rev. 0 | Page 9 of 18

EVALUATION BOARD SOFTWARE

The ADAR1000-EVAL Z evaluation board control software is

organized as a number of tabs, each for a different set of

functions, to control the ADAR1000-EVA LZ evaluation board.

Beneath the content area of the current tab, a log of each

hardware control instruction that the software sends to the

ADAR1000-EVA LZ evaluation board is shown near the bottom

of the window. The last line of the window is used to display the

status of the connection between the control software and the

evaluation board hardware.

CONNECTION TAB

The Connection tab displays the two different SDP adapters

that may be used to provide the USB interface to the

ADAR1000-EVA LZ evaluation board {see Figure 8).

The Connect button is used for initializing communication

between the control software and the ADAR1000-EVA L Z

evaluation board. Once communication is established, the SDP

board connected message displays on the status line at the

bottom of the window.

The ADDR0 and ADDR1 check boxes in Figure 8 allow setting

or unsetting of these two corresponding address bits on the

ADAR1000 device. These two bits determine which one out of

four ADAR1000-EVA LZ evaluation boards on the same serial

bus responds to programming information from the bus.

16788-005

Figure 8. Connection Tab

UG-1283 ADAR1000-EVALZ User Guide

Rev. 0 | Page 10 of 18

Tx CONTROL TAB

The Tx Control tab (see Figure 9) allows the user to set the gain

and phase of each of the four transmit channels.

To us e t he Tx Control tab, take the following steps:

1. Click Tx Initalise.

2. Select the Attenuation check box for each channel to add

in or remove the 15 dB step attenuation.

3. Adjust the Gain Index and Phase Angle settings of each

channel using the corresponding dropdown menus.

4. After adjustments, click Load All to write the settings to

the device registers.

TX REGISTERS TAB

The TX Registers tab provides control for all the transmit

function registers in the device (see Figure 10).

In the Tx Gain Control section, the user sets the gain register

for each transmit channel.

In the Tx Phase Control section, the user sets the in-phase (I)

and quadrature phase (Q) gain registers, as well as polarity bits

for each channel in the corresponding vector modulator (VM).

In the Memory Index section, if the SPI Ctrl check box is

selected, the beam position settings for the corresponding

channel are recalled from memory into the channel work

registers, according to the value (the memory address) in the

RAM INDEX field for each channel. If the SPI Ctrl check box

under TX CHX RAM INDEX is checked, data for all four

channels are pulled according to the value in the TX CHX

RAM INDEX window.

In the Bias Current section, the user selects a bias setting for

each of the three transmit stages (the settings are common to all

four transmit channels).

Click Write Gain Values, Write Phase Values, and Wri te

Memory Values to send the corresponding bias register setting

to the ADAR1000-EVALZ evaluation board.

16788-006

Figure 9. Tx Control Tab

16788-007

Figure 10. TX Registers Tab

ADAR1000-EVALZ User Guide UG-1283

Rev. 0 | Page 11 of 18

Rx CONTROL TAB

The Rx Control tab (see Figure 11) allows setting the gain and

phase of each of the four receive channels.

To us e t he Rx Control tab, take the following steps:

1. Click the Rx Initalise.

2. Select the Attenuation check box for each channel to add

in or remove the 15 dB step attenuation.

3. Adjust the Gain Index and Phase Angle settings of each

channel using the corresponding dropdown menus.

4. After adjustments, click Load All to write the settings to

the device registers.

RX REGISTERS TAB

The RX Registers tab provides control for all the receive

function registers in the device (see Figure 12).

In the Rx Gain Control section, the user sets the gain register

for each receive channel.

In the Rx Phase Control section, the user sets the in-phase (I)

and quadrature phase (Q) gain registers for each channel in the

corresponding vector modulator (VM).

In the Memory Index section, if the SPI Ctrl check box is

selected, the beam position settings for the corresponding

channel are recalled from memory into the channel work

registers, according to the value (the memory address) in the

RAM INDEX window for each channel. If the SPI Ctrl check

box under RX CHX RAM INDEX is selected, data for all four

channels are pulled according to the value in the RX CHX

RAM INDEX window.

In the Bias Current section, the user selects a bias setting for

each of three receive stages (the settings are common to all four

receive channels).

Click Write Gain Values, Write Phase Values, and Wri te

Memory Values to send the corresponding register setting to

the ADAR1000-EVALZ evaluation board.

16788-008

Figure 11. Rx Control Tab

16788-009

Figure 12. RX Registers Tab

UG-1283 ADAR1000-EVALZ User Guide

Rev. 0 | Page 12 of 18

T/R CONTROL TAB

The T/R Control tab controls the enabling of the transmit and

receive channels (see Figure 13).

If the TX EN check box (under Switch Control) is selected, the

TX Enable functions are enabled, and RX Enable functions are

disabled.

If the RX EN check box (under Switch Control) is selected, the

RX Enable functions are enabled, and TX Enable functions are

disabled.

After selecting or clearing the check boxes, click Write Enable

Values or Write Switch Values in each section to write the

GPIO TAB

In the GPIO tab (see Figure 14), select check boxes to set the

corresponding digital control signals on the ADAR1000-EVA LZ

evaluation board to Logic 1 (selected) or Logic 0 (cleared).

16788-010

Figure 13. T/R Control Tab

16788-011

Figure 14. GPIO Tab

ADAR1000-EVALZ User Guide UG-1283

Rev. 0 | Page 13 of 18

MISC TAB

In the MISC tab, configuration of miscellaneous functions is

available (see Figure 15).

Two sets of registers are on the ADAR1000 device to control

the LNA and PA bias outputs and to set the DACs when the

corresponding bias outputs are in the on and off states. The

sections. Each set of register values is transferred to the

ADAR1000-EVA LZ evaluation board when clicking the

respective Write Bias Values.

Under the Enables section, if the BIAS CTRL check box is

cleared, the bias digital-to-analog converter (DAC) outputs use

the Bias ON register values only.

If the BIAS CTRL check box is selected, in receive mode, PA

DACs follow the Bias OFF register values, and the LNA DAC

follows the Bias ON register value. For transmit mode, the

opposite is true, and the PA DACs follow the Bias ON register

values, and the LNA DAC follows the Bias OFF register value.

Use the MUX SEL dropdown menu to select the temperature

sensor or the power detector, one through four, for analog to

digital conversion.

Select ADC EN, CLK EN, and ST CONV and then click Write

ADC Va lues to initiate analog to digital conversion.

Click Read AD C Word to access the conversion result.

The Memory Control section allows setting or clearing the

corresponding bits in Register 0x038 for various memory

control functions.

16788-012

Figure 15. MISC Tab

UG-1283 ADAR1000-EVALZ User Guide

Rev. 0 | Page 14 of 18

BEAM SEQUENCER TAB

The Beam Sequencer tab (see Figure 16) contains a script to

automatically step through a range of memory locations, each

of which contains the gain and phase setting of all four transmit

or receive channels in the device.

Click Select File to select a user file containing a list of memory

locations and values, and click Load File to load values into

beam memory. Each line of the beam position file contains two

values, separated by a comma. The first entry is the decimal

equivalent value, and the second entry is the hexadecimal value.

These two values make the string, which is formed by joining

together the memory address and data for each memory location.

Typical entries in a beam position file are the following:

• 1573119, 0x1800FF

• 1573174, 0x180136

• 1573429, 0x180235

The starting and ending memory locations (Start Point and

End Point, respectively), as well as the time delay between steps

(Time Delay), is entered into the corresponding fields. The

stepping operation is controlled by Start and Stop.

PHASE LOOP TAB

The Phase Loop tab (see Figure 17) provides control to increase

the phase setting of a channel with a predefined step size (Phase

Step) while dwelling at each step for a specified time (Dwell Time).

The ADI Logo Loop moves the phase in a triangular manner

around the circle, as displayed on a network analyzer.

16788-013

Figure 16. Beam Sequencer Tab

16788-014

Figure 17. Phase Loop Tab

ADAR1000-EVALZ User Guide UG-1283

Rev. 0 | Page 15 of 18

MANUAL REGISTER WRITE TAB

The Manual Register Write tab (see Figure 18) allows manual

writes to the ADAR1000 registers, either individually (Values to

write) or grouped (Load and Write). Under Load and Write,

click Choose Input File to load a list of register writes from a

file or paste into the field directly. Click Write Al l to send the

list to the ADAR1000-EVALZ evaluation board.

When the device is initially powered up, enter 00099 into

Values to write . Entering 00099 performs a full register reset

and enables the 4-wire SPI SDO function.

READBACK TAB

The ReadBack tab allows direct writing and reading of the

content of a register (see Figure 19).

Click Manual Write to write a string of hexadecimal digits

containing the address and data of a register into the register.

Enter the register address in the Register field and click Manual

Read for the content of the register to display in the Data field.

16788-015

Figure 18. Manual Register Write Tab

16788-016

Figure 19. ReadBack Tab

UG-1283 ADAR1000-EVALZ User Guide

Rev. 0 | Page 16 of 18

EVALUATION BOARD SCHEMATICS AND ARTWORK

PLACE RES ON BACK

HIGH

ADDR SEL

SDP

F13

F12

CREG1

AVDD3

32K243-40ML5

CREG2

32K243-40ML5

1UF

TX2

TR_SW_POS

TX3

AVDD1

R75

A12

J13

H13

A11

DNI

R31

R32

200

CREG4

32K243-40ML5

DET2

RX2

SDO

32K243-40ML5

DET4

PA_B4

RF_IO

PA_B2

SDIO

RF_IO

TX2

DET4

CREG2

32K243-40ML5

DET2

RF_IO

AVDD3

C33

C35

AGND3

AVDD1

AVDD3

ADDR0

RX_LOAD

CREG4

1UF

TX1

DET1

CREG2

TX1

DET2

RX1

TX1

DET1

RX1

DET2

RX1

32K243-40ML5

RX2

32K243-40ML5

RX2

TX2

RX4

TX4

DET4

TX3

N12

N13

PAD

DET3

1UF

TBD0402

C27

C25

ADAR1000ACCZ

L12

RX4

TX1

N11

N10

M13

RX1

CSB

K12

K13

J12

C12

C13

D12

TX4

E12

E13

G12

G13

RX2

TX3

AVDD3

C31

AVDD3

ADDR1

ADDR0

ADDR1

RX3

RX4

P9A

AGND4

R24

R33

R30

R29

R28

R27

R25

R16

200

R23

R21

R20

R19

R18

R17

R10

R15

R14

R13

R12

200

22.1K

DNI

200

C21

0.01UF

C19

4.7PF

100PF

61302421121

P9A

LNA_B1

TR_SW_NEG

TR_POL

200

TR_SW_NEG

200

C20

AD0

AD1

DVDD

C23

200

10K

P10

SPC20500

RX_LOAD

TX_LOAD

SCLK

SDO

SDIO

CSB

SW-108-14-T-D

DNI

22.1K

DNI

200

LNA_B1

TR_SW_POS

PA_B4

22.1K

TR_POL

LNA_B1

100PF

C29

AVDD1

C24

C22

C26

C30

22.1K

R11

AVDD3

PA_B1

TR_SW_POS

TR_SW_NEG

PA_B2

200

R26

TX2

TBD0402

L13

D13

B11

B10

A13

H12

TR_SW_NEG

PA_B3

A10

TR_POL

200

R35

R22

TR_SW_POS

PA_B3

TR_SW_NEG

TR_SW_POS

200

R34

B12

TR_POL

PA_B1

PA_ON

B13

1UF

DNI

CREG3

DNI

ADDR0

TX_LOAD

DUT

DVDD

RX3

32K243-40ML5

C28

0.01UF

4.7PF

DET3

DNI

AVDD2

RF_IO

32K243-40ML5

DNI

TX4

DET3

TX3

32K243-40ML5

RX3

32K243-40ML5

DET4

32K243-40ML5

TX4

32K243-40ML5

RX4

DET3

TBD0402

ADDR1

M12

M10

M11

CREG3

DET1

LNA_B

SCLK

CREG1

CREG2

AVDD3

CREG4

TBD0402

4.7PF

0.01UF

100PF

C32

C34

AGND

AGNDAGNDAGNDAGNDAGNDAGND

AGND

AGNDAGND

AGND

AGND AGND AGND AGND AGND

AGND

AGND AGND

AGND

PAD

DET1

GND

AVDD3

CREG3

CREG4

GND

ADDR1

ADDR0

TX_LOAD

RX_LOAD

GND

AVDD3

CREG2

CREG1

GND

SCLK

SDIO

SDO

CSB

GND

TX1

GND

RX4

GND

RX1

GND

TX4

GND

DET2

GND

DET4

GND

TX2

GND

RX3

GND

RX2

GND

TX3

GND

AVDD1

GND

TR_SW_POS

TR_POL

PA_ON

GND

LNA_BIAS

PA_BIAS1

PA_BIAS2

GND

RF_IO

GND

PA_BIAS3

PA_BIAS4

TR_SW_NEG

GND

DET3

AGND

DNI

16788-017

Figure 20. ADAR1000-EVALZ Evaluation Board Schematic (Page 1)

ADAR1000-EVALZ User Guide UG-1283

Rev. 0 | Page 17 of 18

1.8V

LEVSHTR ENBL

-3.3V

DNI

+3.3V

-5V

3.3V

1.8V

EEPROM

LEVSHTR ENBL

3.3V

1.8V

0.1UF

AGND

SPI_CLK

GPIO5

SPI_MISO

GPIO4

SPI_MOSI

SPI_SEL_A

DNI

GPIO5

R36

+3.3V

AGND

SN74AVC4T245PW

R67

RX_LOAD

PA_ON

N5V

-5V

AGND

TSW-106-14-T-D

CSB

SCLK

10K

SDIO

SDO

10K

AVDD3

GPIO2

AVDD

GPIO1

DVDD

AVDD

GPIO0

C14

0.1UF

GPIO3

PEC10DAAN

SPI_CLK

SPI_MOSI

SPI_SEL_A

10K

GPIO2

10PF

10K

AVDD

PEC10DAAN

AVDD1

N3V3

1N5337BG

DVDD

AGND1

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

119

120

FX8-120S-SV(21)

RED1

VIO

0.1UF

C15

10PF

0.1UF

C13

100K

RED

1UF

RAVDD

RV15

LED1

10UF

DNI

10K

DNI

FX8-120S-SV(21)

0.1UF

10K

AGND2

DNI

AVDD

SPI_MISO

SPI_CLK

GPIO5

GPIO1

SPI_MOSI

VIO

GPIO4

GPIO2

GPIO0

DVDD

GPIO5

AVDD

PA_ON

AVDD

10PF

GPIO0

10K

10PF

AVDD

C11

SDO

24LC32A-I/MS

GPIO3

SPI_SEL_A

118

69157-102HLF

TX_LOAD

AD1

0.1UF

C12

69157-102HLF

AVDD

AVDD2

AVDD1

GPIO0

GPIO4

GPIO5

AVDD

AVDD2

GPIO1

SN74AVC4T245PW

10K

AD0

TBD0603

69157-102HLF

10PF

69157-102HLF

10PF

GPIO4

GPIO5

SPI_MISO

SPI_MOSI

SN74AVC2T245RSWR

10K

AVDD

GPIO1

SPI_MISO

ADP150AUJZ-1.8-R7

AVDD3

SPI_MISO

SPI_SEL_A

SPI_MOSI

SPI_CLK

GPIO4

GPIO1

GPIO0

AVDD1

GPIO3

GPIO2

10K

AVDD

R37

R38

R39

R40

R41

R42

R43

R44

R45

R46

R47

R48

R49

R50

R51

R52

-3.3V

R53

DVDD

10K

1UF

R55

R56

R57

R54

DNI

100K

R59

R60

R61

R62

R63

R64

R65

R66

C10

R58

10K

R68

R69

R70

R71

R72

R73

R74

AGND

VCCBVCCA

GND

DIR2

DIR1

OE_N

AGND

VSS

VCC

SCL

SDA

AGND

VCCB

1OE_N

2OE_N

1B1

1B2

2B1

2B2

GNDGND

2A2

2A1

1A2

1A1

2DIR

1DIR

VCCA

AGND

GNDNC

VOUT

VIN

AGND

VCCB

1OE_N

2OE_N

1B1

1B2

2B1

2B2

GNDGND

2A2

2A1

1A2

1A1

2DIR

1DIR

VCCA

AGND

DNI

0402

16788-018

Figure 21. ADAR1000-EVALZ Evaluation Board Schematic (Page 2)

UG-1283 ADAR1000-EVALZ User Guide

Rev. 0 | Page 18 of 18

16788-019

Figure 22. Layer 1 (Component Side)

16788-020

Figure 23. Layer 4 (Bottom Side)

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UG16788-0-6/18(0)

Analog Devices ADAR1000-EVALZ User manual

Analog Devices ADAR1000-EVALZ User manual

Analog Devices ADAR1000-EVALZ User manual

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