ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ
Evaluation Board User Guide
UG-1759
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Evaluating the ADMV4530 Dual-Mode, Ka Band Upconverter With Integrated
Fractional-N PLL and VCO
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.
Rev. A | Page 1 of 21
FEATURES
Fully featured evaluation board for the ADMV4530
On-board system demonstration platform (SDP-S) connector
for SPI
5 V operation through LDO
ACE software interface for SPI control
EQUIPMENT NEEDED
5 V dc power supply
Baseband signal generator(s)
Spectrum analyzer
USB cable
SDP-S controller board
DOCUMENTS NEEDED
ADMV4530 data sheet
SOFTWARE NEEDED
ACE software
GENERAL DESCRIPTION
The ADMV4530IQ-EVALZ and the ADMV4530IF-EVALZ are
the two evaluation boards available for the ADMV4530 that
work in inphase/quadrature (I/Q) mode and intermediate
frequency (IF) mode, respectively. Both boards incorporate the
ADMV4530 Ka band upconverter with low dropout (LDO)
regulators and an interface to the EVAL-SDP-CS1Z (SDP-S)
controller board to allow the simple and efficient evaluation of
the ADMV4530. The on-board LDO regulators allow the
ADMV4530 to be powered on by a single supply.
The ADMV4530 is a highly integrated upconverter with an
I/Q mixer that is ideally suited for next generation Ka band
satellite communications. The chip can be programmed using a
4-wire serial port interface (SPI). The SDP-S controller allows the
user to interface with the ADMV4530 SPI through the Analog
Devices, Inc., Analysis, Control Evaluation (ACE) software.
EVALUATION BOARD PHOTOGRAPHS
23154-001
Figure 1. ADMV4530IQ-EVALZ
23154-002
Figure 2. ADMV4530IF-EVALZ
For full details on the ADMV4530, see the ADMV4530 data
sheet, which must be consulted in conjunction with this user
guide when using the ADMV4530IQ-EVALZ and the
ADMV4530IF-EVALZ.
UG-1759 ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide
Rev. A | Page 2 of 21
TABLE OF CONTENTS
Features .............................................................................................. 1
Equipment Needed ........................................................................... 1
Documents Needed .......................................................................... 1
Software Needed ............................................................................... 1
General Description ......................................................................... 1
Evaluation Board Photographs ....................................................... 1
Revision History ............................................................................... 2
Evaluation Board Hardware ........................................................... 3
Evaluation Board Software .............................................................. 5
Installing the ACE Software, ADMV4530 Plug-Ins, and
Drivers ........................................................................................... 5
Plug-In Overview ......................................................................... 6
Plug-In Details .............................................................................. 7
Performing Evaluation .................................................................. 10
ADMV4530IQ-EVALZ OR ADMV4530IF-EVALZ Quick
Start .............................................................................................. 10
Signal Generator Settings .......................................................... 10
RF Gain Control ......................................................................... 11
IF Gain Control .......................................................................... 11
Automated Chip Reset .............................................................. 11
Manual Chip Reset ..................................................................... 11
Loss of Board Communication ................................................ 11
Regulator Bypass ........................................................................ 11
Evaluation Board Schematics and Artwork ................................ 12
ADMV4530IQ-EVALZ ............................................................. 12
ADMV4530IF-EVALZ .............................................................. 16
Ordering Information.................................................................... 20
Bill of Materials .......................................................................... 20
REVISION HISTORY
3/2020—Rev. 0 to Rev. A
Change to User Guide Title ............................................................ 1
3/2020—Revision 0: Initial Version
ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide UG-1759
Rev. A | Page 3 of 21
EVALUATION BOARD HARDWARE
Both the ADMV4530IQ-EVALZ and the ADMV4530IF-EVALZ
evaluation boards have on-board ADMV4530 chips. Figure 3
and Figure 4 show lab bench setups for both boards.
For each setup, connect the SDP-S board to the on-board, 120-pin
connector and then to the PC through the mini USB connector.
A 5 V dc power supply must be connected to the 5V and GND1
test points. Alternatively, the power supply can be connected to
the VSUPPLY Subminiature Version A (SMA) port.
Two signal generators must be connected to the
ADMV4530IQ-EVALZ or the ADMV4530IF-EVALZ
evaluation board. One signal generator provides the reference
input signal, and the other signal generator provides either the
IF input or the I/Q inputs. The IF input is a single-ended
configuration, whereas the I/Q inputs are a differential
configuration.
To observe the output signal from the ADMV4530IQ-EVALZ
or the ADMV4530IF-EVALZ board, connect a spectrum analyzer
(or similar instrument) to the RF output (RFOUT) port.
SIGNAL GENERATOR
REFERENCE INPUTRF OUTPUT
IQ INPUTS
BASEBAND
SIGNAL GENERATOR
SPECTRUM
A
N
A
LYZ E R
23154-003
Figure 3. ADMV4530IQ-EVALZ Lab Bench Setup for I/Q Mode
ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide UG-1759
Rev. A | Page 5 of 21
EVALUATION BOARD SOFTWARE
INSTALLING THE ACE SOFTWARE, ADMV4530
PLUG-INS, AND DRIVERS
The ADMV4530IQ-EVALZ and the ADMV4530IF-EVALZ use
the Analog Devices Analysis|Control|Evaluation (ACE)
software. For instructions on how to install and use the ACE
software, go to www.analog.com/ACE.
If the ACE software is already installed on the PC, ensure that
the installed software is the latest version, as shown on the
www.analog.com/ACE page. If the previously installed software
is not the latest version, take the following steps to install the
updated ACE software:
1. Uninstall the current version of the ACE software on the PC.
2. Delete the ACE folder found in C:\ProgramData\Analog
Devices.
3. Install the latest version of the ACE software. During
installation, ensure that the .Net 40 Client, SDP Drivers,
the LRF Drivers installations are checked off as well (see
Figure 5).
23154-005
Figure 5. Required Driver Installations with the ACE Software
Once the installation finishes, the ADMV4530 evaluation board
plug-in appears when the ACE software is open (see Figure 6).
Note that both the ADMV4530IQ-EVALZ and the ADMV4530IF-
EVALZ evaluation boards use the same ACE plug-in, which
displays on the main ACE screen as the ADMV4530 Board.
23154-006
Figure 6. ADMV4530 Board Plug-In Window after Opening the
ACE Software
UG-1759 ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide
Rev. A | Page 6 of 21
PLUG-IN OVERVIEW
When either the ADMV4530IQ-EVALZ or the ADMV4530IQ-
EVALZ is connected to the PC, the ADMV4530 Board appears
in the Attached Hardware section. Double-clicking on the
plug-in opens two tabs, the board level plug-in and the chip level
plug-in, which are the ADMV4530 Board (see Figure 7) and the
ADMV4530 (see Figure 8), respectively.
The ADMV4530 plug-in has the following functions and
features:
Device initialization
Mode selection
Block power downs
Phase-locked loop (PLL) synthesizer settings
Mixer settings
Temperature sensor readback
VCO core and band readback
Note that the ACE software provides a simple tutorial for
testing the ADMV4530. For a more customized and detailed
implementation, refer to ADMV4530 data sheet for a full
description of each block, register, and the corresponding
settings.
23154-007
Figure 7. ADMV4530 Board Plug-In View
23154-008
Figure 8. ADMV4530 Chip Block Diagram
ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide UG-1759
Rev. A | Page 7 of 21
PLUG-IN DETAILS
The full screen ADMV4530 user interface with labels is shown
in Figure 9. The labels correspond to items listed in Table 1,
which describes the functionality of each block. For additional
detailed programming, refer to the ADMV4530 data sheet.
23154-009
Figure 9. ADMV4530 Block Diagram with Labels
Table 1. ADMV4530 Block Diagram Label Functions (See Figure 9)
Label Function
A
Use the Initial Configuration to initialize the ADMV4530IQ-EVALZ or the ADMV4530IQ-EVALZ evaluation board. Set the
following under the Initial Settings section:
Mixer Mode Selection: select IF, I/Q, or user defined mode.
Requested LO Frequency: enter the requested local oscillator (LO) frequency.
Reference Frequency Input: enter the reference input frequency.
Reference Doubler: use the dropdown menu to disable or enable the reference doubler.
R Word: enter the R word value.
Reference Divide-by-2: use the dropdown menu to disable or enable the reference divide by 2.
CP Current: use the dropdown menu to select the charge pump (CP) current.
Summary: click this button to review the settings for the initial setup.
Apply: click this button to apply the initial settings. The settings are reflected in the right sections. Note that clicking Apply
Changes (Label K1) does not update the changes in this section.
UG-1759 ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide
Rev. A | Page 8 of 21
Label Function
B
Use the Frequency & N Parameters section to change settings for the LO frequency after applying the initial settings in the
Initial Configuration (Label A) section. This section includes the following:
Requested LO Frequency and VCO Frequency: enter values in these two text boxes to trigger the INT, FRAC1, FRAC2, and
MOD2 calculations.
INT, FRAC1, FRAC2, and MOD2: calculations based on the requested LO or VCO frequency. Changing these values directly
changes the actual LO and VCO frequency accordingly but does not change the requested LO and VCO frequency text boxes.
PFD Frequency: calculation based on the Reference Path (Label C) section.
Actual LO Frequency and VCO Frequency: the actual LO frequency and the actual VCO frequency are calculated from the PFD
frequency, INT, FRAC1, FRAC2, MOD1, and MOD2 parameters shown on the right side of the equation (see Figure 9).
Delta LO Frequency and VCO Frequency: the delta is computed from the difference between the requested and actual
frequencies, which is useful for detecting if there is any residual frequency error due to limitations caused by synthesizer resolution.
Lock Detect Readback: click the check button next to this option to check whether the PLL is locked.
Integer and Fractional indication light: indicates if the chip is in integer or fractional mode.
C
Use the Reference Path section to change the reference parameters and PFD frequency after applying the initial settings in the
Initial Configuration (Label A) section. This section includes the following:
PFD Frequency: the calculated PFD frequency based on the equation on right (see Figure 9).
REF Frequency: enter the reference input frequency.
Doubler: click this button to enable or disable the doubler.
R Word: scroll up and down to change the R word values, ranging from 1 to 32.
Div-by-2: click this button to enable or disable the reference divide by 2 function.
D
Click the Read button in the Core & Band section to read back the chip core and band values.
E
Click the Read button in the Temp ADC section to read back the chip temperature sensor values.
F
I and Q: scroll up and down to adjust the I and Q phase value in the LO Phase section.
G
Use the Power Downs section to configure the different blocks power conditions in the chip. This section includes the following:
RF BIAS PD, PLL PD, and VCO PD: scroll up and down to power up or power down these blocks in the chip.
PD pin: scroll up and down to select normal operation or to power down the chip.
RESET_N Pin: scroll up and down to select normal operation or to reset the power-on state.
H
Use the Mode Selection section to select the mixer mode and configure the automatic gain control (AGC).
I
Use the Baseband Settings section to configure the dc settings for both IF and I/Q mode and the mixer common-mode
settings. This section includes the following:
DC Offset Target: scroll up and down to set the target dc offset. Changing the values result in changes in DC Offset I and DC
Offset Q values accordingly.
DC Offset I, DC Offset Q: bidirectional calculation associated with DC Offset Target. Scroll up and down to change these
values. The DC Offset Target changes accordingly.
MIXER_VCM: scroll up and down to change the mixer common-mode voltage. The hexadecimal value is shown to the right.
IQ Mode: scroll up and down to change the I/Q mode common-mode voltage (VCM).
Calc Error light: this light illuminates if there is a calculation error when MIXER_VCM is changed to a value outside of the
nominal equations. Refer to the ADMV4530 data sheet and Register 0x103 for more details.
J
The Other PLL Settings section consists of the following:
ΣΔ PD: click the dropdown menu to power down or power up the Σ-Δ function. For integer mode, power ΣΔ PD down. For
fractional mode, power ΣΔ PD up.
Aux ΣΔ: click the dropdown menu to enable or disable this function.
AUTOCAL: click the dropdown menu to enable or disable the auto calibration function.
Prescaler: click the dropdown menu to select the prescaler.
PD Polarity: click the dropdown menu to select the PD polarity.
CP Current: click the dropdown menu to select the charge pump current.
CP Bleed: click the dropdown menu to enable or disable the charge pump bleed.
MUXOUT: click the dropdown menu to configure the MUXOUT signal, which can output to the SDO pin.
ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide UG-1759
Rev. A | Page 9 of 21
Label Function
Lock Detect: click the dropdown menu to change the counting cycles for lock detect.
Loss of Lock: click the dropdown menu to enable or disable the loss of lock function.
VCO_BAND_DIV, SYTNTH_LOCK_TIMEOUT, TIMEOUT, and VCO_ALC_TIMEOUT: use these text boxes to configure the
parameters.
K1
All changes, except within the Initial Configuration section, do not take effect until the Apply Changes button is clicked. If Auto
Apply is highlighted in the ADMV4530 Board tab, the Apply Changes feature continuously runs every few seconds, and the
Apply Changes button does not need to be clicked to apply or read back the block diagram settings.
K2
To read back all of the SPI registers of the device, click Read All.
K3
Click Reset Chip to reset the device.
K4
Click Diff to show registers that are different on the device.
K5
Click Software Defaults to restore the software defaults to the device, and then click Apply Changes.
K6
Click Memory Map Side-By-Side to enable the side by side memory map view.
L
Click Proceed to Memory Map to open the ADMV4530 memory map (see Figure 10)
23154-010
Figure 10. ADMV4530 Memory Map in the ACE Software
UG-1759 ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide
Rev. A | Page 10 of 21
PERFORMING EVALUATION
ADMV4530IQ-EVALZ OR ADMV4530IF-EVALZ
QUICK START
To set up the ADMV4530IQ-EVALZ or the ADMV4530IF-
EVALZ evaluation board, take the following steps:
1. Connect the SDP-S to the 120-pin connector on the
ADMV4530IQ-EVALZ or the ADMV4530IF-EVALZ
evaluation board.
2. Connect a USB cable to the PC and then to the SDP-S.
3. Connect a 5 V dc power supply to the 5V and GND1 test
points. Alternatively, the power supply can be connected
to the VSUPPLY SMA port. The power supply current
limit must be set to 800 mA.
4. Connect the reference input signal generator to the
REF_IN port on the ADMV4530IQ-EVALZ or the
ADMV4530IF-EVALZ evaluation board. Ensure that the
board is set to the desired reference input frequency and
power level.
5. Depending on which board is being evaluated, connect the
signal generator for either IF input or I/Q inputs.
6. Connect a spectrum analyzer (or similar instrument) to
the RFOUT port.
7. Open the ACE software. The ADMV4530 Board appears
in the Attached Hardware section. Double-click on the
plug-in to see the chip plug-in ADMV4530 on screen.
8. Use the Initial Configuration in the ACE software to
initialize the chip. Be sure to select the correct mixer mode
of operation, either IF or I/Q mode. Additionally, set the
desired PLL configuration settings, and then click Apply in
the Initial Configuration section (see Figure 11).
SIGNAL GENERATOR SETTINGS
When evaluating the ADMV4530IQ-EVALZ, a good starting
point for configuring the signal generator inputs is as follows:
Reference input frequency = 200 MHz
Reference input power = 8 dBm
I/Q input frequency = 25 MHz
I/Q common mode voltage = 0.5 V
In-phase (negative) IN input power = −16 dBm
In-phase (positive) IP input power = −16 dBm
Quadrature (positive) QP input power = −16 dBm
Quadrature (negative) QP input power = −16 dBm
When evaluating the ADMV4530IF-EVALZ, a good starting
point for configuring the signal generator inputs is as follows:
Reference input frequency = 200 MHz
Reference input power = 8 dBm
IF input frequency = 2.5 GHz
IF input power = −40 dBm
23154-011
Figure 11. ADMV4530 Initial Configuration Section
ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide UG-1759
Rev. A | Page 11 of 21
RF GAIN CONTROL
To adjust the RF gain control on either the ADMV4530IQ-
EVALZ or the ADMV4530IF-EVALZ evaluation board, take
the following steps:
1. Connect a power supply to the RF_GAIN_TP test point
and one ground test point on the ADMV4530IQ-EVALZ
or ADMV4530IF-EVALZ evaluation board. Alternatively,
the power supply can be connected to the RF_GAIN SMA
port. The power supply current limit must be set to 1 mA.
2. Adjust the power supply voltage as desired from 0 V to
1.8 V. The maximum gain corresponds to 1.8 V, and the
minimum gain corresponds to 0 V. Refer to the
ADMV4530 data sheet for more information regarding
gain performance.
IF GAIN CONTROL
To adjust the IF gain control on ADMV4530IF-EVALZ
evaluation board, take the following steps:
1. Connect a power supply to the IF_GAIN_TP test point
and one ground test point on the ADMV4530IF-EVALZ
evaluation board. Alternatively, the power supply can be
connected to the IF_GAIN SMA port. The power supply
current limit must be set to 1 mA.
2. Adjust the power supply voltage as desired from 0 V to
3.3 V. The maximum gain corresponds to 0 V, and the
minimum gain corresponds to 3.3 V. Refer to the
ADMV4530 data sheet for more information regarding
gain performance.
AUTOMATED CHIP RESET
If a reset of the ADMV4530 chip is required on the
ADMV4530IQ-EVALZ or ADMV4530IF-EVALZ evaluation
board, it is recommended to use the automated reset sequence.
Click Reset Chip (see Figure 9, Label K3 and Table 1 for
additional information). This automated sequence performs
the following actions:
Toggles all SDP-S general-purpose input/outputs (GPIOs)
to a low state, which sets both the
RST
and PD pins of the
ADMV4530 low.
Toggles the
RST
pin high to bring the ADMV4530 chip
back to the normal operating state.
Programs Register 0x00 to 0x81, which also resets the
ADMV4530. This step covers legacy boards that did not
have the
RST
pin connected.
Programs Register 0x00 to 0x18 to enable the SDO pin on
the ADMV4530.
Programs the recommended mixer settings for IF mode.
Programs the PLL for a 28 GHz LO frequency anticipating
a 200 MHz reference input frequency.
Reads back the register settings of the ADMV4530.
MANUAL CHIP RESET
For manual reset operations, the following outlines various
ways to perform a reset.
There is a reset button (S1) on the ADMV4530IQ-EVALZ
or the ADMV4530IF-EVALZ evaluation board. Pressing
this button pulls the
RST
pin low to initiate a reset to the
factory power-up state.
The
RST
pin can also be pulled low from within the ACE
software by using the dropdown menu in the lower left
corner of Figure 9 (see Label G). When using this option,
be sure to return the dropdown menu back to Normal
Operation after resetting the device.
Register 0x00 can be programmed to 0x81 to initiate a
reset of the ADMV4530.
Regardless of the manual reset option used, it is recommended
to perform the following after the device resets:
Program Register 0x00 to 0x18 to enable the SDO pin on
the ADMV4530.
Read back all registers on the ADMV4530.
LOSS OF BOARD COMMUNICATION
When the ADMV4530 is turned off and then on, or if the USB
cable is unplugged and plugged back in while the ACE software
is open, communication with the ADMV4530 may be lost. To
regain communication, click the System tab, click the USB
symbol in the SDP-S Controller subsystem, and then click
Acquire. If this step does not work, restart the ACE software to
reinitiate communication with the ADMV4530IQ-EVALZ or the
ADMV4530IF-EVALZ evaluation board.
REGULATOR BYPASS
Both the ADMV4530IQ-EVALZ and the ADMV4530IF-
EVALZ evaluation boards have voltage regulators that allow
the user to operate these evaluation boards from a single 5 V dc
power supply. The on-board voltage regulators supply several
bias voltages to the various supply pins on the chip. If desired,
these voltage regulators can be bypassed by removing the 0 Ω
registers (R25 to R28) from the ADMV4530IQ-EVALZ or the
ADMV4530IF-EVALZ evaluation board and then by injecting
each voltage independently by using the corresponding test points.
See the schematics for details (see Figure 13 and Figure 19).
UG-1759 ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide
Rev. A | Page 12 of 21
EVALUATION BOARD SCHEMATICS AND ARTWORK
ADMV4530IQ-EVALZ
DNI
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DNI
142-0701-851
142-0701-851
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IF_GAIN
C36
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C33
C16
C17
C15
C14
C13
R42
R16
C11
R44
R15
C35
C34
C12
R12
C44
C23
R24
C24
C43
R41
R51
C19
C20
R17R14
C52
C21 C41
C42C22
R22
R21
C54
R53
C37
C80
C18
C55
R43
R54
R52
R20
C60
U1
C51
C4
RF_GAIN
R2
R1
C2C1
C3
REF_IN
C5
R5
R4
R3
RFOUT
R23
R45
S1
C53
C39
C40
R19
R18
C38
IFIN
R13
IF_GAIN_TP
QP
QN
C32
RF_GAIN_TP
R11
C31
REF_IN
EXT_VT
IF_GAIN
IFIN
VCC_1.8V
VCC_3.3V
IF_GAIN
RF_GAIN
VCC_4.0V
VCC_4.0V
VCC_1.8V
QP
QN CPOUT
PD
VCC_4.0V
IFIN
VTUNE
SCLK
CSB
VCC_3.3V_VCO
VCC_3.3V
VTUNE
IP
SDI
SDO
IP
RF_GAIN
VCC_3.3V
IN
VCC_3.3V
VCC_3.3V
RFOUT
VCC_3.3V
CPOUT
EXT_VT
IN
QN
RFOUT
QP
VCC_3.3V
VCC_3.3V
REF_IN
RESET_N VCC_3.3V
243
1
1
3
PAD4
2
PAD6
10
PAD2
14
15
16
17
40
PAD15
1
PAD12PAD1
24
25
26
27
28
29
PAD7
PAD8
8
20
22
4
13
23
12
36
32
7
33
21
30
34
38
35
6
5
PAD16
PAD14
PAD13
PAD11
PAD10
PAD9
PAD5
PAD3
3
2
9
18
11
31
19
39
37
1
1
432
432
432
432
432
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32
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1
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AGND
AGNDAGND
A
GND
AGND
AGND AGND
AGND AGND
AGND AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
VCC2_DRV_4V
AGND
RFOUT
AGND
VCC_REF_1P8V
REF_IN
RST
VCC_CP_PFD_3P3V
VCC_LDO_3P3V
CREG
SDO
SCLK
SDI
SEN
CP_OUT
PD
VCC_DIV_3P3V
VCC_VCO_3P3V
VG_VCO
VCC_BG_3P3V
VTUNE
BG_RBIAS_1P1K
IFIN
VCC_DOUBLER_3P3V
VCC2_IF_3P3V
VCC_MIXER_3P3V
NC
VCC_VVA_1P8V
VCC_RFAMP_4V
EXT_CAP_P
EXT_CAP_N
IN
IP
VCC_IF_3P3V
QP
QN
VCTR_RF
NC
NC
VCC_DRV_4V
AGND AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND AGND
AGNDAGND
AGND
AGND
AGND AGND
AGND
AGND AGND
AGND
AGND AGND
AGND
23154-018
Figure 12. ADMV4530IQ-EVALZ Evaluation Board Schematic, Page 1
ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide UG-1759
Rev. A | Page 13 of 21
4
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142-0701-851
100K
TBD0402
1UF
1000PF
10UF
1000PF
10UF
10UF
RED
E014160
JEDEC_TYPE=MSOP8
330
330
DNI
03-053057
0
0
0
330
24LC32A-I/MS
R0402
RED
0
100K
BLK
BLK
RED
RED
0
FX8-120S-SV(21)
0
DNI
DNI
RED
BLK
10UF
2.1K
DNI
TBD0402
TBD0402
DNI
0
BLK
10UF
R50
VCC_3.3V
C69
U2
C62
C67
R27
C82
C83
C81
R29
C84
R63
R62
R61
P1
P2
VSUPPLY
R31
R30
R25
C66
C64
C65
C63
C61
C71
C70
GND4
GND5
M1
U3
VCC_4.0V
GND1
GND 2
GND 3
VCC_1.8V
VCC_3.3V_VCO
C50
R46
U6
R48
R47
R49
R26
R28
5V
C73
C68
U5
C72
U4
SDI
PD
SCLK
SDO
CSB
RESET_N
VCC_4.0V
PD
5V
SDA_SDP
TWI_A0
SPARE
VCC_3.3V_VCO
3V3USB
SCL_SDP
SPARE
3P3VUSB
SDA_SDP
SCL_SDP
SCL
K
SDI
CSB
3P3VUSB
RESET_N
VCC_3.3V
TWI_A0
SDO
VCC_1.8V
4
5
6
17
30
19
104
103
102
101
100
99
90
21
38
39
81
88
94
96
65
116
1
5
6259
7249
7348
87
89
29 92
32
31
91
37
85
84
83
34
33
82
64
35
41 80
42 79
57
60
26 95
27
7 114
8 113
9 112
10 111
110
12
13 108
14 107
15 106
16 105
18
20
22
24 97
25
120
119
70
68
67
6655
54
53
51
50
2
7447
7645
7744
7843
118
117
115
109
98
93
86
75
69
6358
52
46
40
36
28
23
11
6
4
3
56
71
61
10
9
8
7
3
2
1
43
2
1
1
1
PAD
2
1
7
8
4
3
PAD
6
5
1
1
1
1
1
1
1
7
4
8
5
6
3
2
1
1
1
2
8
5
6
4
PAD
7
3
2
1
7
8
4
3
PAD 6
5
2
1
7
8
4
36
PAD
5
EP
VIN
VIN
GND
EN
SS
SENSE
VOUT
VOUT
AGND
AGND
AGND
AGND
AGND
AGND
VSS
VCC
WP
A2
A1
A0
SCL
SDA
AGND
AGND
EP
VIN
VIN
GND
ENSS
SENSE
VOUT
VOUT
AGND
AGND
AGND
AGND
AGND
AGND
EP
VIN
EN
REF
REF_SENSE
BYP
GND
VOUT
VREG
AGND
AGND
AGND
AGND
AGND
EP
VIN
VIN
GND
EN
SS
SENSE
VOUT
VOUT
AGND
AGND
AGND
AGND
AGND
AGND
AGND
SPI_SEL_A_N
CLKOUT
NC
NC
GND
GND
VIO
GND
PAR_D22
PAR_D20
PAR_D18
PAR_D16
PAR_D15
GND
PAR_D12
PAR_D10
PAR_D8
PAR_D6
GND
PAR_D4
PAR_D2
PAR_D0
PAR_WR_N
PAR_INT
GND
PAR_A2
PAR_A0
PAR_FS2
PAR_CLK
GND
SPORT_RSCLK
SPORT_DR0
SPORT_RFS
SPORT_TFS
SPORT_DT0
SPORT_TSCLK
GND
SPI_MOSI
SPI_MISO
SPI_CLK
GND
SDA_0
SCL_0
GPIO1
GPIO3
GPIO5
GND
GPIO7
TMR_B
TMR_D
NC
GND
NC
NC
NC
WAKE_N
SLEEP_N
GND
UART_TX
BMODE1RESET_IN_N
UART_RX
GND
RESET_OUT_N
EEPROM_A0
NC
NC
NC
GND
NC
NC
TMR_C
TMR_A
GPIO6
GND
GPIO4
GPIO2
GPIO0
SCL_1
SDA_1
GND
SPI_SEL1/SPI_SS_N
SPI_SEL_C_N
SPI_SEL_B_N
GND
SERIAL_INT
SPI_D3
SPI_D2
SPORT_DT1
SPORT_DR1
SPORT_TDV1
SPORT_TDV0
GND
PAR_FS1
PAR_FS3
PAR_A1
PAR_A3
GND
PAR_CS_N
PAR_RD_N
PAR_D1
PAR_D3
PAR_D5
GND
PAR_D7
PAR_D9
PAR_D11
PAR_D13
PAR_D14
GND
PAR_D17
PAR_D19
PAR_D21
PAR_D23
GND
USB_VBUS
GND
GND
NC
VIN
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
23154-019
Figure 13. ADMV4530IQ-EVALZ Evaluation Board Schematic, Page 2
UG-1759 ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide
Rev. A | Page 16 of 21
ADMV4530IF-EVALZ
0
ORG
TBD0402
HK-LR-SR2(12)
0.01UF
10K
100K
DNI
DNI
TBD0402
B3S-1000
33
0
910
DNI
0
15NF
910
150PF
DNI
TBD0402
20PF 20PF
0
DNI
0
142-0701-851
DNI
0
0
0
TBD0402
TBD0402
33
1.1K
0
0.1UF
TBD0402
ADMV4530ACCZ
33
33
10UF
1UF
1UF
0
TBD0402
TBD0402
1UF
TBD0402
TBD0402
1UF
1UF
1000PF
4.7UF0.1UF
1.1K
1UF
0
0
1UF
TBD0402
0
0
0
TBD0402
0
142-0701-851
1UF
680
TBD0402
1UF
1UF
1UF
1UF
1UF
TBD0402
TBD0402
ORG
142-0701-851
1.1K
HK-LR-SR2(12)
TBD0402
142-0701-851
DNI
DNI
DNI
1UF
C55
C60
C52
U1
C51
R42
R43
R14
C34 C14
C4
EXT_VT
R51
R52
R53
R54
IF_GAIN
RF_GAIN
R44
R2
R1
C2C1
C3
REF_IN
C35 C16
R15
C5
R5
R4
R3
RFOUT
R24
C44 C24
C23C43
R23
C80
R45
S1
C22 C42
R22
C21
C53
C41
C54
R21
C19 C39
C20 C40
R19
R20
R18
C38C18
IFIN
C15
C17
C36
C37
R16
R17
R13
C33 C13
IF_GAIN_TP
R12
C32 C12
R41
RF_GAIN_TP
R11
C31 C11
VCC_3.3VRESET_N
REF_IN
VCC_3.3V
VCC_3.3V
RFOUT
EXT_VT
CPOUT
VCC_3.3V
RFOUT
VCC_3.3V
VCC_3.3V
VCC_3.3V
RF_GAIN
SDO
SDI
VTUNE
VCC_3.3V
VCC_3.3V_VCO
CSB
SCLK
VTUNE
IFIN
VCC_4.0V
PD
CPOUT
VCC_1.8V
VCC_4.0V
VCC_4.0V
RF_GAIN
IF_GAIN
VCC_3.3V
VCC_1.8V
IFIN
IF_GAIN
EXT_VT
REF_IN
20
22
4
13
23
12
36
15
32
7
1
17
24
33
21
16
40
27
30
28
29
34
38
35
6
5
25
PAD16
PAD15
PAD14
PAD13
PAD12
PAD11
PAD10
PAD9
PAD8
PAD7
PAD6
PAD5
PAD4
PAD3
PAD2
PAD1
14
3
2
8
9
18
11
10
31
26
19
39
37
1
1
1
432
432
432
432
32
32
1
1
3
42
1
1
1
1
AGND
AGNDAGND
AGND
AGND
AGND AGND
AGND AGND
AGND AGND
AGND
AGND
AGND
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
VCC2_DRV_4V
AGND
RFOUT
AGND
VCC_REF_1P8V
REF_IN
RST
VCC_CP_PFD_3P3V
VCC_LDO_3P3V
CREG
SDO
SCLK
SDI
SEN
CP_OUT
PD
VCC_DIV_3P3V
VCC_VCO_3P3V
VG_VCO
VCC_BG_3P3V
VTUNE
BG_RBIAS_1P1K
IFIN
VCC_DOUBLER_3P3V
VCC2_IF_3P3V
VCC_MIXER_3P3V
NC
VCC_VVA_1P8V
VCC_RFAMP_4V
EXT_CAP_P
EXT_CAP_N
IN
IP
VCC_IF_3P3V
QP
QN
VCTR_RF
NC
NC
VCC_DRV_4V
AGND AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND AGND
AGNDAGND
AGND
AGND
AGND AGND
AGND
AGND AGND
AGND
AGND AGND
AGND
23154-012
Figure 18. ADMV4530IF-EVALZ Evaluation Board Schematic, Page 1
ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide UG-1759
Rev. A | Page 17 of 21
1.8V, 3MA
3.3V,45MA
3.3V,440MA
4.0V,240MA
1UF
ADM7154ARDZ-3.3
M20-9980546
10K
ADM7171ACPZ-3.3
0.001UF
ADM7170ACPZ-1.8
DNI
TBD0402
TBD0402
10UF
10UF
10UF
BLK
ADM7170ACPZ-3.3
0.1UF
142-0701-851
100K
TBD0402
1UF
1000PF
10UF
1000PF
10UF
10UF
RED
E014160
JEDEC_TYPE=MSOP8
330
330
DNI
03-053057
0
0
0
330
24LC32A-I/MS
R0402
RED
0
100K
BLK
BLK
RED
RED
0
FX8-120S-SV(21)
0
DNI
DNI
RED
BLK
10UF
2.1K
DNI
TBD0402
TBD0402
DNI
0
BLK
10UF
C67
C69
C82
C83
C81
R29
C84
R63
R62
R61
P1
P2
VSUPPLY
R31
R30
R25
C66
C64
C62
C65
C63
C61
C71
C70
GND4
GND5
M1
U3
VCC_4.0V
GND1
VCC_3.3V
GND2
GND3
VCC_1.8V
VCC_3.3V_VCO
C50
R46
U6
R48
R47
R50
R49
R27
R26
R28
5V
C73
C68
U5
C72
U4
U2
SDI
PD
SCLK
SDO
CSB
RESET_N
VCC_4.0V
PD
5V
SDA_SDP
TWI_A0
SPARE
VCC_3.3V_VCO
3V3USB
SCL_SDP
SPARE
3P3VUSB
SDA_SDP
SCL_SDP
SCL
K
SDI
CSB
3P3VUSB
RESET_N
VCC_3.3V
TWI_A0
SDO
VCC_1.8V
65
116
1
5
6259
7249
7348
87
89
30
29 92
90
32
88
31
91
38
37
85
39
84
83
34
33
82
64
35
41 80
42 79
57
60
10021
99
26 95
27
7114
8113
9112
10 111
110
12
13 108
14 107
15 106
16 105
18 103
19 102
20 101
22
94
24 97
25 96
120
119
70
68
67
6655
54
53
51
50
2
7447
7645
7744
7843
118
117
115
109
104
98
93
86
81
75
69
6358
52
46
40
36
28
23
17
11
6
4
3
56
71
61
10
9
8
7
6
5
4
3
2
1
43
2
1
1
1
PAD
2
1
7
8
4
3
PAD
PAD
6
5
1
1
1
1
1
1
1
7
4
8
5
6
3
2
1
1
1
2
8
5
6
4
PAD
7
3
2
1
7
8
4
3
6
5
2
1
7
8
4
36
PAD
5
EP
VIN
VIN
GND
EN
SS
SENSE
VOUT
VOUT
AGND
AGND
AGND
AGND
AGND
AGND
VSS
VCC
WP
A2
A1
A0
SCL
SDA
AGND
AGND
EP
VIN
VIN
GND
ENSS
SENSE
VOUT
VOUT
AGND
AGND
AGND
AGND
AGND
AGND
EP
VIN
EN
REF
REF_SENSE GND
BYP
VOUT
VREG
AGND
AGND
AGND
AGND
AGND
EP
VIN
VIN
GND
EN
SS
SENSE
VOUT
VOUT
AGND
AGND
AGND
AGND
AGND
AGND
AGND
SPI_SEL_A_N
CLKOUT
NC
NC
GND
GND
VIO
GND
PAR_D22
PAR_D20
PAR_D18
PAR_D16
PAR_D15
GND
PAR_D12
PAR_D10
PAR_D8
PAR_D6
GND
PAR_D4
PAR_D2
PAR_D0
PAR_WR_N
PAR_INT
GND
PAR_A2
PAR_A0
PAR_FS2
PAR_CLK
GND
SPORT_RSCLK
SPORT_DR0
SPORT_RFS
SPORT_TFS
SPORT_DT0
SPORT_TSCLK
GND
SPI_MOSI
SPI_MISO
SPI_CLK
GND
SDA_0
SCL_0
GPIO1
GPIO3
GPIO5
GND
GPIO7
TMR_B
TMR_D
NC
GND
NC
NC
NC
WAKE_N
SLEEP_N
GND
UART_TX
BMODE1RESET_IN_N
UART_RX
GND
RESET_OUT_N
EEPROM_A0
NC
NC
NC
GND
NC
NC
TMR_C
TMR_A
GPIO6
GND
GPIO4
GPIO2
GPIO0
SCL_1
SDA_1
GND
SPI_SEL1/SPI_SS_N
SPI_SEL_C_N
SPI_SEL_B_N
GND
SERIAL_INT
SPI_D3
SPI_D2
SPORT_DT1
SPORT_DR1
SPORT_TDV1
SPORT_TDV0
GND
PAR_FS1
PAR_FS3
PAR_A1
PAR_A3
GND
PAR_CS_N
PAR_RD_N
PAR_D1
PAR_D3
PAR_D5
GND
PAR_D7
PAR_
D9
PAR_D11
PAR_D13
PAR_D14
GND
PAR_D17
PAR_D19
PAR_D21
PAR_D23
GND
USB_VBUS
GND
GND
NC
VIN
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
23154-013
Figure 19. ADMV4530IF-EVALZ Evaluation Board Schematic, Page 2
UG-1759 ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide
Rev. A | Page 20 of 21
ORDERING INFORMATION
BILL OF MATERIALS
The ADMV4530IQ-EVALZ bill of materials is identical to the ADMV4530IF-EVALZ except for one row (see Note 1 of Table 2).
Table 2. ADMV4530IQ-EVALZ
Quantity Reference Designator Description Manufacturer Part Number
5 5V, VCC_1.8V, VCC_3.3V,
VCC_3.3V_VCO, VCC_4.0V
Test points, red Components Corporation TP-104-01-02
1 C1 Capacitor, 150 pF, 50 V, 5%, 0402 Murata GRM1555C1H151JA01D
14 C11 to C24 Capacitors, 1 μF, 16 V, 10%, 0402 Yageo CC0402KRX5R7BB105
1 C2 Capacitor, 15 nF, 35 V, 10%, 0402 TDK CGA2B3X7R1V153K050BB
1 C3 Capacitor, 20 pF, 16 V, 5%, 0402 AVX Corporation 0402YA200JAT2A
3 C50 to C52 Capacitors, 0.1 μF, 16 V, 10%, 0402 Kemet C0402C104K4RACTU
1 C55 Capacitor, 10 μF, 6.3 V, 20%, 0402 Samsung CL05A106MQ5NUNC
1 C60 Capacitor, 0.01 μF, 50 V, 10%, 0402 Murata GCM155R71H103KA55D
8 C61 to C68 Capacitors, 10 μF, 16 V, 10%, 0603 Murata GRM188R61C106KAALD
1 C69 Capacitor, 1 nF, 50 V, 5%, 0603 Murata GRM1885C1H102JA01D
2 C70, C71 Capacitors, 1 nF, 50 V, 5%, 0402 Murata GRM1555C1H102JA01
2 C72, C73 Capacitors, 1 μF, 16 V, 10%, 0603 TDK CGA3E1X7R1C105K080AC
5 GND1 to GND5 Test points, black Components Corporation TP-104-01-00
1 RFOUT Connector, 2.92 mm, 40 GHz Hirose Electric Co. HK-LR-SR2(12)
2 IF_GAIN_TP, RF_GAIN_TP Test points, orange Components Corporation TP-104-01-03
6 IN, IP, QN, QP, REF_IN, VSUPPLY
1
Connectors, edge launch, SMA Cinch Connectivity 142-0701-851
1 P1 Connector, vertical, surface-mount
technology (SMT), 120-pin
Hirose Electric Co. FX8-120S-SV(21)
1 P2 Connector, vertical, header, 10-pin Harwin Inc. M20-9980546
2 R1, R2 Resistors, 910 Ω, 1/16 W, 0.1%, 0402 Panasonic ERA-2AEB911X
20 R3, R4, R11 to R25, R28 to R30 Resistors, 0 Ω, 1/10 W, 0402 Panasonic ERJ-2GE0R00X
2 R26, R27 Resistors, 0 Ω, 1/10 W, 0603 Panasonic ERJ-3GEY0R00V
3 R41 to R43 Resistors, 1.1 kΩ, 1/16 W, 1%, 0402 Yageo RC0402FR-071K1L
1 R44 Resistor, 680 Ω, 1/16 W, 0.1%, 0402 Panasonic ERA-2ARB681X
2 R45, R50 Resistors, 10 kΩ, 1/10 W, 1%, 0402 Panasonic ERJ-2RKF1002X
2 R46, R47 Resistors, 100 kΩ, 1/16 W, 1%, 0402 Panasonic ERJ-2RKF1003X
1 R49 Resistor, 2.1 kΩ, 1/16 W, 1%, 0402 Panasonic ERJ-2RKF2101X
4 R51 to R54 Resistors, 33 Ω, 1/10 W, 5%, 0402 Panasonic ERJ-2GEJ330X
3 R61 to R63 Resistors, 330 Ω, 1/16 W, 5%, 0402 Panasonic ERJ-2GEJ331X
1 S1 Switch, mechanical, push button Omron Electronics Inc. B3S1000
1 U1 IC, Ka band upconverter Analog Devices ADMV4530ACCZ
1 U2 IC, LDO regulator, 1.8 V Analog Devices ADM7170ACPZ-1.8-R7
1 U3 IC, LDO regulator, 3.3 V Analog Devices ADM7171ACPZ-3.3-R7
1 U4 IC, LDO regulator, 3.3 V Analog Devices ADM7170ACPZ-3.3-R7
1 U5 IC, LDO regulator, 3.3 V Analog Devices ADM7154ARDZ-3.3-R7
1 U6 IC, 24LC32A, EEPROM, I
2
C Microchip Technology 24LC32A-I/MS
20 C5, C31 to C44, C80 to C84 Capacitors, 0402, do not install (DNI) Not applicable Not applicable
1 C4 Capacitor, 20 pF, 16 V, 5%, 0402, DNI AVX Corporation 0402YA200JAT2A
1 C53 Capacitor, 1 nF, 50 V, 5%, 0402, DNI Murata GRM1555C1H102JA01
1 C54 Capacitor, 4.7 μF, 16 V, 10%, 0603, DNI TDK C1608X5R1C475K080AC
3 EXT_VT, IF_GAIN, RF_GAIN Connectors, edge launch, SMA, DNI Cinch Connectivity 142-0701-851
1 R31 Resistor, 0 Ω, 1/10 W, 0402, DNI Panasonic ERJ-2GE0R00X
1 R48 Resistor, 0402, DNI Not applicable Not applicable
1 R5 Resistor, 100 kΩ, 1/16 W, 0402, DNI Panasonic ERJ-2RKF1003X
1
For the ADMV4530IF-EVALZ, only REF_IN and VSUPPLY are applicable for this row.
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