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NXP QorIQ® T4240/T4160/T4080 Multicore Communications Processors Reference guide

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e6500 Core Reference Manual
Supports
e6500
E6500RM
Rev 0
06/2014
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e6500 Core Reference Manual, Rev 0
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Contents
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Number Title
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Co nt ents
About this book
Audience ........................................................................................................................xxxv
Organization...................................................................................................................xxxv
Suggested reading........................................................................................................ xxxvi
General information................................................................................................. xxxvi
Related documentation ............................................................................................ xxxvi
Conventions ................................................................................................................ xxxvii
Terminology conventions........................................................................................... xxxviii
Chapter 1
e6500 Overview
1.1 Overview.......................................................................................................................... 1-1
1.2 Feature summary..............................................................................................................1-5
1.3 Instruction flow.............................................................................................................. 1-10
1.4 Programming model overview....................................................................................... 1-13
1.4.1 Register model overview ........................................................................................... 1-13
1.4.2 Instruction model overview ....................................................................................... 1-15
1.5 Summary of differences between previous e500 family cores ...................................... 1-15
1.5.1 Changes from e500v2 to e500mc .............................................................................. 1-15
1.5.2 Changes from e500mc to e5500 ................................................................................ 1-17
1.5.3 Changes from e5500 to e6500 ................................................................................... 1-18
Chapter 2
Register Model
2.1 Overview.......................................................................................................................... 2-1
2.2 e6500 register model........................................................................................................ 2-2
2.2.1 64-bit registers ............................................................................................................. 2-3
2.2.2 Special-purpose registers (SPRs)................................................................................. 2-5
2.2.2.1 Register mapping in the guest–supervisor state..................................................... 2-11
2.2.3 Memory-mapped registers (MMRs) .......................................................................... 2-12
2.2.3.1 Synchronization requirements for memory-mapped registers............................... 2-15
2.2.4 Thread management registers (TMRs) ...................................................................... 2-15
2.3 Registers for integer operations ..................................................................................... 2-16
2.3.1 General-purpose registers (GPRs) ............................................................................. 2-16
2.3.2 Integer Exception (XER) register .............................................................................. 2-16
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2.4 Registers for floating-point operations .......................................................................... 2-16
2.4.1 Floating-point registers (FPRs).................................................................................. 2-17
2.4.2 Floating-Point Status and Control (FPSCR) register................................................. 2-17
2.5 Registers for vector operations ...................................................................................... 2-17
2.5.1 Vector registers (VRs)................................................................................................ 2-17
2.5.2 Vector Status and Control (VSCR) register ............................................................... 2-17
2.6 Registers for branch operations ..................................................................................... 2-18
2.6.1 Condition (CR) register ............................................................................................. 2-18
2.6.2 Link (LR) register ...................................................................................................... 2-18
2.6.3 Count (CTR) register ................................................................................................. 2-18
2.7 Processor control registers ............................................................................................. 2-18
2.7.1 Machine State (MSR) register ................................................................................... 2-19
2.7.2 Machine State Register Protect (MSRP) register....................................................... 2-20
2.7.3 Embedded Processor Control (EPCR) register .......................................................... 2-21
2.7.4 Branch Unit Control and Status (BUCSR) register ................................................... 2-21
2.7.5 Hardware Implementation-Dependent 0 (HID0) register .......................................... 2-22
2.7.6 Core Device Control and Status (CDCSR0) register................................................. 2-23
2.7.7 Power Management Control 0 (PWRMGTCR0) register.......................................... 2-24
2.7.8 Processor Version (PVR) register .............................................................................. 2-24
2.7.9 System Version (SVR) register .................................................................................. 2-25
2.7.10 Chip Identification (CIR) register.............................................................................. 2-25
2.7.11 Shifted CCSRBAR (SCCSRBAR) register ............................................................... 2-25
2.8 Timer registers ............................................................................................................... 2-26
2.8.1 Timer Control (TCR) register .................................................................................... 2-27
2.8.2 Timer Status (TSR) register ....................................................................................... 2-27
2.8.2.1 Watchdog Timer Reset Status (WRS) field ........................................................... 2-27
2.8.2.2 Watchdog Interrupt Status (WIS) and Enable Next Watchdog (ENW) fields ....... 2-27
2.8.3 Time base registers (TBU and TBL).......................................................................... 2-27
2.8.4 Decrementer (DEC) register ...................................................................................... 2-28
2.8.5 Decrementer Auto-Reload (DECAR) register........................................................... 2-28
2.8.6 Alternate time base registers (ATBL and ATBU)...................................................... 2-28
2.9 Interrupt registers........................................................................................................... 2-29
2.9.1 Save/restore registers (xSRR0/xSRR1) ..................................................................... 2-29
2.9.2 (Guest) Data Exception Address (DEAR/GDEAR) registers.................................... 2-30
2.9.3 Logical Page Exception (LPER/LPERU) register ..................................................... 2-30
2.9.4 (Guest) Interrupt Vector Prefix (IVPR/GIVPR) registers.......................................... 2-31
2.9.5 (Guest) Interrupt Vector Offset (IVORs/GIVORs) registers...................................... 2-31
2.9.6 (Guest) External Proxy (EPR/GEPR) registers ......................................................... 2-32
2.9.7 (Guest) Exception Syndrome (ESR/GESR) registers................................................ 2-33
2.9.8 (Guest) Processor ID (PIR/GPIR) registers ............................................................... 2-35
2.9.9 Machine-check address registers (MCAR/MCARU/MCARUA).............................. 2-35
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2.9.10 Machine Check Syndrome (MCSR) register ............................................................. 2-36
2.10 Software-use SPRs (SPRGs, GSPRGs, and USPRG0) ................................................. 2-39
2.11 L1 cache registers ..........................................................................................................2-40
2.11.1 L1 Cache Control and Status 0 (L1CSR0) register.................................................... 2-40
2.11.2 L1 Cache Control and Status 1 (L1CSR1) register.................................................... 2-40
2.11.3 L1 Cache Control and Status 2 (L1CSR2) register.................................................... 2-41
2.11.4 L1 Cache Configuration 0 (L1CFG0) register........................................................... 2-41
2.11.5 L1 Cache Configuration 1 (L1CFG1) register........................................................... 2-42
2.12 L2 cache registers ..........................................................................................................2-43
2.12.1 L2 Configuration 0 (L2CFG0) register...................................................................... 2-43
2.12.2 L2 Cache Control and Status 0 (L2CSR0) register.................................................... 2-44
2.12.3 L2 Cache Control and Status 1 (L2CSR1) register.................................................... 2-47
2.12.4 L2 cache partitioning registers................................................................................... 2-48
2.12.4.1 L2 cache partitioning identification registers (L2PIRn) ........................................ 2-50
2.12.4.2 L2 cache partitioning allocation registers (L2PARn) ............................................ 2-51
2.12.4.3 L2 cache partitioning way registers (L2PWRn) .................................................... 2-53
2.12.5 L2 error registers........................................................................................................2-54
2.12.5.1 L2 Cache Error Disable (L2ERRDIS) register ...................................................... 2-54
2.12.5.2 L2 Cache Error Detect (L2ERRDET) register ...................................................... 2-55
2.12.5.3 L2 Cache Error Interrupt Enable (L2ERRINTEN) register................................... 2-57
2.12.5.4 L2 Cache Error Control (L2ERRCTL) register..................................................... 2-58
2.12.5.5 L2 cache error capture address registers (L2ERRADDR and L2ERREADDR)... 2-59
2.12.5.6 L2 cache error capture data registers (L2CAPTDATALO
and L2CAPTDATAHI) ...................................................................................... 2-59
2.12.5.7 L2 Cache Capture ECC Syndrome (L2CAPTECC) register ................................. 2-59
2.12.5.8 L2 Cache Error Attribute (L2ERRATTR) register ................................................ 2-59
2.12.5.9 L2 Cache Error Injection Control (L2ERRINJCTL) register................................ 2-60
2.12.5.10 L2 cache error injection mask registers (L2ERRINJLO and L2ERRINJHI) ........ 2-61
2.13 MMU registers ...............................................................................................................2-62
2.13.1 Logical Partition ID (LPIDR) register ....................................................................... 2-62
2.13.2 Process ID (PID) register........................................................................................... 2-62
2.13.3 MMU Control and Status 0 (MMUCSR0) register ................................................... 2-62
2.13.4 MMU Configuration (MMUCFG) register................................................................ 2-63
2.13.5 TLB configuration registers (TLBnCFG).................................................................. 2-64
2.13.6 TLB page size registers (TLBnPS) ............................................................................ 2-66
2.13.7 Embedded Page Table Configuration (EPTCFG) register......................................... 2-66
2.13.8 Logical to Real Address Translation Configuration (LRATCFG) register................ 2-67
2.13.9 Logical to Real Address Translation Page Size (LRATPS) register .......................... 2-69
2.13.10 MMU assist registers (MAS0–MAS8) ...................................................................... 2-69
2.13.10.1 MMU Assist 0 (MAS0) register ............................................................................ 2-70
2.13.10.2 MMU Assist 1 (MAS1) register ............................................................................ 2-71
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2.13.10.3 MMU Assist 2 (MAS2) register ............................................................................ 2-72
2.13.10.4 MMU Assist 3 (MAS3) register ............................................................................ 2-73
2.13.10.5 MMU Assist 4 (MAS4) register ............................................................................ 2-75
2.13.10.6 MMU Assist 5 (MAS5) register ............................................................................ 2-76
2.13.10.7 MMU Assist 6 (MAS6) register ............................................................................ 2-76
2.13.10.8 MAS Register 7 (MAS7) ....................................................................................... 2-77
2.13.10.9 MMU Assist 8 (MAS8) register ............................................................................ 2-78
2.13.10.10 64-bit access to MAS register pairs ....................................................................... 2-79
2.13.11 External PID registers................................................................................................ 2-79
2.13.11.1 External PID Load Context (EPLC) register ......................................................... 2-79
2.13.11.2 External PID Store Context (EPSC) register ......................................................... 2-80
2.14 Internal debug registers.................................................................................................. 2-81
2.14.1 Unimplemented internal debug registers ................................................................... 2-82
2.14.2 Debug Resource Request 0 (DBRR0) register........................................................... 2-82
2.14.3 External Debug Resource Allocation Control 0 (EDBRAC0) register...................... 2-83
2.14.4 Debug Control 0 (DBCR0) register ........................................................................... 2-85
2.14.5 Debug Control 1 (DBCR1) register ........................................................................... 2-88
2.14.6 Debug Control 2 (DBCR2) register ........................................................................... 2-91
2.14.7 Debug Control 4 (DBCR4) register ........................................................................... 2-93
2.14.8 Debug Control 5 (DBCR5) register ........................................................................... 2-94
2.14.9 Debug Status (DBSR/DBSRWR) register ................................................................. 2-96
2.14.10 Instruction address compare registers (IAC1–IAC8)................................................. 2-99
2.14.11 Data address compare registers (DAC1–DAC2)...................................................... 2-100
2.14.12 Nexus SPR access registers ..................................................................................... 2-100
2.14.12.1 Nexus SPR Configuration (NSPC) register ......................................................... 2-100
2.14.12.2 Nexus SPR Data (NSPD) register........................................................................ 2-101
2.14.13 Debug Event Select (DEVENT) register ................................................................ 2-101
2.14.14 Debug Data Acquisition Message (DDAM) register............................................... 2-102
2.14.15 Nexus Process ID (NPIDR) register ........................................................................ 2-102
2.15 Multi-threaded operation management registers ......................................................... 2-103
2.15.1 Thread (processor) management SPRs .................................................................... 2-103
2.15.1.1 Thread Identification (TIR) register .................................................................... 2-103
2.15.1.2 Thread Enable (TEN) register.............................................................................. 2-104
2.15.1.3 Thread Enable Set (TENS) register ..................................................................... 2-104
2.15.1.4 Thread Enable Clear (TENC) register ................................................................. 2-105
2.15.1.5 Thread Enable Status (TENSR) register.............................................................. 2-106
2.15.1.6 Processor Priority (PPR32) register..................................................................... 2-107
2.15.2 Thread management registers (TMRs) .................................................................... 2-108
2.15.2.1 Thread Management Configuration 0 (TMCFG0) register ................................. 2-108
2.15.2.2 Thread Initial Next Instruction Address n (INIAn) registers............................... 2-109
2.15.2.3 Thread Initial Machine State Register n (IMSRn) registers ................................ 2-109
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2.15.2.4 Thread Priority n (TPRIn) registers ..................................................................... 2-110
2.16 Performance monitor registers (PMRs) ....................................................................... 2-110
2.16.1 Performance Monitor Global Control 0 (PMGC0) and User
Performance Monitor Global Control 0 (UPMGC0) registers ............................ 2-112
2.16.2 Local control A registers (PMLCa0–PMLCa5/UPMLCa0–UPMLCa5) ................ 2-112
2.16.3 Local control b registers (PMLCb0–PMLCb5/UPMLCb0–UPMLCb5) ................ 2-114
2.16.4 Performance monitor counter registers (PMC0–PMC5/UPMC0–UPMC5) ........... 2-118
Chapter 3
Instruction Model
3.1 Overview.......................................................................................................................... 3-1
3.1.1 Supported Power ISA categories and unsupported instructions .................................. 3-1
3.2 Computation mode........................................................................................................... 3-3
3.3 Instruction set summary................................................................................................... 3-3
3.3.1 Instruction decoding .................................................................................................... 3-4
3.3.2 Definition of boundedly undefined .............................................................................. 3-4
3.3.3 Synchronization requirements ..................................................................................... 3-5
3.3.3.1 Shared resource synchronization ............................................................................. 3-8
3.3.3.2 Synchronization with tlbwe, tlbivax, and tlbilx instructions .................................. 3-9
3.3.3.3 Context synchronization .......................................................................................... 3-9
3.3.3.4 Execution synchronization..................................................................................... 3-10
3.3.3.5 Instruction-related interrupts ................................................................................. 3-10
3.4 Instruction set overview ................................................................................................. 3-10
3.4.1 Record and overflow forms........................................................................................ 3-10
3.4.2 Effective address computation ................................................................................... 3-11
3.4.3 User-level instructions ............................................................................................... 3-11
3.4.3.1 Integer instructions ................................................................................................ 3-11
3.4.3.1.1 Integer arithmetic instructions ........................................................................... 3-12
3.4.3.1.2 Integer compare instructions.............................................................................. 3-13
3.4.3.1.3 Integer logical instructions ................................................................................ 3-13
3.4.3.1.4 Integer rotate and shift instructions ................................................................... 3-14
3.4.3.2 Load and store instructions.................................................................................... 3-15
3.4.3.2.1 Update forms of load and store instructions ...................................................... 3-16
3.4.3.2.2 General integer load instructions ....................................................................... 3-16
3.4.3.2.3 Integer store instructions.................................................................................... 3-17
3.4.3.2.4 Integer load and store with byte-reverse instructions ........................................ 3-18
3.4.3.2.5 Integer load and store multiple instructions....................................................... 3-18
3.4.3.2.6 Floating-point load instructions......................................................................... 3-19
3.4.3.2.7 Floating-point store instructions........................................................................ 3-19
3.4.3.2.8 AltiVec load instructions ................................................................................... 3-20
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3.4.3.2.9 AltiVec store instructions................................................................................... 3-21
3.4.3.2.10 Decorated load and store instructions................................................................ 3-21
3.4.4 Floating-point execution model ................................................................................. 3-22
3.4.4.1 Floating-point instructions..................................................................................... 3-23
3.4.4.1.1 Floating-point arithmetic instructions ............................................................... 3-24
3.4.4.1.2 Floating-point multiply-add instructions ........................................................... 3-24
3.4.4.1.3 Floating-point rounding and conversion instructions ........................................ 3-25
3.4.4.1.4 Floating-point compare instructions.................................................................. 3-25
3.4.4.1.5 Floating-Point Status and Control (FPSCR) register instructions ..................... 3-25
3.4.4.1.6 Floating-point move instructions ....................................................................... 3-26
3.4.5 AltiVec instructions.................................................................................................... 3-26
3.4.5.1 AltiVec integer instructions ................................................................................... 3-27
3.4.5.2 AltiVec integer compare instructions..................................................................... 3-29
3.4.5.3 AltiVec integer logical instructions ....................................................................... 3-29
3.4.5.4 AltiVec integer rotate and shift instructions .......................................................... 3-30
3.4.5.5 AltiVec floating-point instructions ........................................................................ 3-30
3.4.5.5.1 AltiVec floating-point behavior for special case data........................................ 3-31
3.4.5.5.2 Floating-point division and square root ............................................................. 3-35
3.4.5.5.3 AltiVec floating-point arithmetic instructions ................................................... 3-35
3.4.5.5.4 AltiVec floating-point multiply-add instructions............................................... 3-35
3.4.5.5.5 Floating-point rounding and conversion instructions ........................................ 3-35
3.4.5.5.6 AltiVec floating-point compare instructions...................................................... 3-36
3.4.5.5.7 AltiVec floating-point estimate instructions ...................................................... 3-37
3.4.5.6 AltiVec compatibility instructions ......................................................................... 3-37
3.4.5.7 AltiVec permutation and formatting instructions .................................................. 3-37
3.4.5.7.1 AltiVec pack instructions................................................................................... 3-37
3.4.5.7.2 AltiVec unpack instructions............................................................................... 3-38
3.4.5.7.3 AltiVec merge instructions ................................................................................ 3-39
3.4.5.7.4 AltiVec splat instructions................................................................................... 3-39
3.4.5.7.5 AltiVec Permute instruction............................................................................... 3-39
3.4.5.7.6 AltiVec Select instruction .................................................................................. 3-40
3.4.5.7.7 AltiVec shift instructions ................................................................................... 3-40
3.4.5.7.8 AltiVec status and control register instructions ................................................. 3-40
3.4.5.7.9 GPR to AltiVec move instructions..................................................................... 3-40
3.4.6 Branch and flow control instructions......................................................................... 3-41
3.4.6.1 Conditional branch control .................................................................................... 3-41
3.4.6.2 Branch instructions ................................................................................................ 3-42
3.4.6.3 Integer Select (isel) instruction.............................................................................. 3-43
3.4.6.4 Condition register logical instructions ................................................................... 3-43
3.4.6.5 Trap instructions .................................................................................................... 3-43
3.4.6.6 System linkage instruction..................................................................................... 3-44
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3.4.6.7 Hypervisor privilege instruction ............................................................................ 3-44
3.4.7 Processor control instructions.................................................................................... 3-44
3.4.7.1 Move to/from Condition Register instructions ...................................................... 3-44
3.4.7.2 Wait for Interrupt instruction ................................................................................. 3-45
3.4.8 Performance monitor instructions (user level)........................................................... 3-45
3.4.9 Memory synchronization instructions ....................................................................... 3-46
3.4.9.1 mbar (MO = 1)...................................................................................................... 3-50
3.4.10 Reservations............................................................................................................... 3-51
3.4.11 Memory control instructions...................................................................................... 3-51
3.4.11.1 User-level cache instructions ................................................................................. 3-52
3.4.11.1.1 CT field values................................................................................................... 3-52
3.4.11.2 Cache locking instructions..................................................................................... 3-54
3.4.12 Hypervisor- and supervisor-level instructions ........................................................... 3-56
3.4.12.1 System linkage and MSR access instructions........................................................ 3-56
3.4.12.2 Thread management instructions ........................................................................... 3-57
3.4.12.3 External PID load and store instructions ............................................................... 3-58
3.4.12.4 Supervisor-level memory control instructions....................................................... 3-59
3.4.12.4.1 Supervisor-level cache instruction..................................................................... 3-59
3.4.12.4.2 Supervisor-level TLB management instructions ............................................... 3-60
3.4.12.5 Message Clear and Message Send instructions ..................................................... 3-62
3.4.12.6 Performance monitor instructions (supervisor level)............................................. 3-63
3.4.13 Recommended simplified mnemonics....................................................................... 3-63
3.4.14 Context synchronization ............................................................................................ 3-64
3.5 Debug instruction model................................................................................................ 3-64
3.6 Instruction listing ........................................................................................................... 3-64
Chapter 4
Interrupts and Exceptions
4.1 Overview.......................................................................................................................... 4-1
4.2 e6500 implementation of interrupt architecture............................................................... 4-2
4.3 Directed interrupts ........................................................................................................... 4-4
4.4 Recoverability and MSR[RI] ........................................................................................... 4-4
4.5 Interrupt registers ............................................................................................................. 4-5
4.6 Exceptions........................................................................................................................ 4-6
4.6.1 Interrupt ordering and masking.................................................................................... 4-7
4.7 Interrupt classification .....................................................................................................4-7
4.8 Interrupt processing .........................................................................................................4-8
4.9 Interrupt definitions ......................................................................................................... 4-8
4.9.1 Partially executed instructions ................................................................................... 4-12
4.9.2 Critical input interrupt—IVOR0................................................................................ 4-13
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4.9.3 Machine check interrupt—IVOR1............................................................................. 4-14
4.9.3.1 General machine check, error report, and NMI mechanism.................................. 4-14
4.9.3.2 NMI exceptions ..................................................................................................... 4-17
4.9.3.3 Machine check error report synchronous exceptions ............................................ 4-17
4.9.3.4 Asynchronous machine check exceptions ............................................................. 4-19
4.9.4 Data storage interrupt (DSI)—IVOR2/GIVOR2 ....................................................... 4-20
4.9.5 Instruction storage interrupt (ISI)—IVOR3/GIVOR3............................................... 4-23
4.9.6 External input interrupt—IVOR4/GIVOR4............................................................... 4-25
4.9.6.1 External proxy ....................................................................................................... 4-26
4.9.7 Alignment interrupt—IVOR5.................................................................................... 4-27
4.9.8 Program interrupt—IVOR6 ....................................................................................... 4-28
4.9.9 Floating-point unavailable interrupt—IVOR7........................................................... 4-29
4.9.10 System call/hypervisor system call interrupt—IVOR8/GIVOR8/IVOR40............... 4-30
4.9.11 Decrementer interrupt—IVOR10 .............................................................................. 4-31
4.9.12 Fixed-interval timer interrupt—IVOR11 ................................................................... 4-31
4.9.13 Watchdog timer interrupt—IVOR12 ......................................................................... 4-32
4.9.14 Data TLB error interrupt—IVOR13/GIVOR13......................................................... 4-33
4.9.15 Instruction TLB error interrupt—IVOR14/GIVOR14............................................... 4-34
4.9.16 Debug interrupt—IVOR15 ........................................................................................ 4-35
4.9.16.1 Suppressing debug events in hypervisor mode...................................................... 4-36
4.9.17 AltiVec unavailable interrupt—IVOR32.................................................................... 4-36
4.9.18 AltiVec assist interrupt—IVOR33 ............................................................................. 4-37
4.9.19 Performance monitor interrupt—IVOR35/GIVOR35 ............................................... 4-37
4.9.20 Doorbell interrupts—IVOR36–IVOR39.................................................................... 4-38
4.9.20.1 Doorbell interrupt definitions ................................................................................ 4-39
4.9.20.1.1 Processor doorbell interrupt (IVOR36) ............................................................. 4-39
4.9.20.1.2 Processor doorbell critical interrupt—IVOR37................................................. 4-39
4.9.20.1.3 Guest processor doorbell interrupts—IVOR38 ................................................. 4-40
4.9.20.1.4 Guest processor doorbell critical interrupts—IVOR39 ..................................... 4-40
4.9.20.1.5 Guest processor doorbell machine check interrupts—IVOR39 ........................ 4-41
4.9.21 Hypervisor privilege interrupt—IVOR41 .................................................................. 4-42
4.9.22 LRAT error interrupt—IVOR42 ................................................................................ 4-45
4.10 Guidelines for system software...................................................................................... 4-46
4.11 Interrupt priorities .......................................................................................................... 4-46
4.12 Exception priorities........................................................................................................4-47
Chapter 5
Core Caches and Memory Subsystem
5.1 Overview.......................................................................................................................... 5-1
5.2 The cache programming model ....................................................................................... 5-4
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5.2.1 Cache identifiers ..........................................................................................................5-4
5.2.2 Cache stashing .............................................................................................................5-4
5.3 Core memory subsystem block diagram.......................................................................... 5-5
5.3.1 Dual Load/Store Unit (LSU)........................................................................................ 5-5
5.3.1.1 Caching-allowed loads and the LSU ....................................................................... 5-6
5.3.1.2 L1 Load Miss Queue (LMQ)................................................................................... 5-6
5.3.1.3 Store Queue ............................................................................................................. 5-6
5.3.1.4 Store Gather Buffer.................................................................................................. 5-6
5.3.1.5 Data Reload Data Buffer (DRLDB) ........................................................................ 5-6
5.3.2 Instruction Unit ............................................................................................................ 5-6
5.3.3 Core/Cluster interface .................................................................................................. 5-7
5.4 L1 cache structure............................................................................................................ 5-7
5.4.1 L1 data cache organization .......................................................................................... 5-8
5.4.2 Write-through cache .................................................................................................... 5-9
5.4.3 L1 instruction cache organization................................................................................ 5-9
5.4.4 L1 cache parity........................................................................................................... 5-11
5.4.5 L1 cache parity error injection................................................................................... 5-11
5.5 L1 cache coherency support and memory access ordering............................................ 5-12
5.5.1 Data cache coherency model ..................................................................................... 5-12
5.5.2 Instruction cache coherency model............................................................................ 5-12
5.5.3 Snoop signaling.......................................................................................................... 5-12
5.5.4 WIMGE settings and the effect on caches................................................................. 5-12
5.5.4.1 Write-back stores ................................................................................................... 5-12
5.5.4.2 Write-through stores .............................................................................................. 5-13
5.5.4.3 Caching-inhibited loads and stores........................................................................ 5-13
5.5.4.4 Misaligned accesses and the Endian (E) bit .......................................................... 5-13
5.5.4.5 Speculative accesses and guarded memory ........................................................... 5-13
5.5.5 Load/store operation ordering.................................................................................... 5-14
5.5.5.1 Architecture ordering requirements....................................................................... 5-15
5.5.5.2 Forcing load and store ordering (memory barriers)............................................... 5-15
5.5.5.2.1 Simplified memory barrier recommendations................................................... 5-17
5.5.5.3 Memory access ordering........................................................................................ 5-17
5.5.5.4 msgsnd ordering..................................................................................................... 5-18
5.5.5.5 Atomic memory references.................................................................................... 5-18
5.6 L1 cache control.............................................................................................................5-19
5.6.1 Cache control instructions ......................................................................................... 5-19
5.6.2 Enabling and disabling the L1 caches........................................................................ 5-19
5.6.3 L1 cache flash invalidation ........................................................................................ 5-20
5.6.4 Instruction and data cache line locking and unlocking.............................................. 5-20
5.6.4.1 Effects of other cache instructions on locked lines................................................ 5-21
5.6.4.2 Flash clearing of lock bits...................................................................................... 5-21
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5.6.5 L1 data cache flushing ............................................................................................... 5-22
5.7 L1 cache operation......................................................................................................... 5-22
5.7.1 Cache miss and reload operations.............................................................................. 5-22
5.7.1.1 Data cache reloads ................................................................................................. 5-22
5.7.1.2 Instruction cache reloads ....................................................................................... 5-22
5.7.1.3 Cache allocation on misses.................................................................................... 5-23
5.7.2 L1 cache block replacement ...................................................................................... 5-23
5.7.2.1 FIFO replacement .................................................................................................. 5-23
5.7.2.2 PLRU replacement................................................................................................. 5-23
5.7.2.3 PLRU bit updates................................................................................................... 5-25
5.8 Cluster shared L2 cache................................................................................................. 5-26
5.8.1 Cluster memory subsystem block diagram................................................................ 5-27
5.8.1.1 Core/Cluster interface............................................................................................ 5-27
5.8.1.2 L2 cache.................................................................................................................5-27
5.8.1.3 CoreNet Bus Interface Unit (BIU)......................................................................... 5-28
5.8.2 L2 cache structure...................................................................................................... 5-28
5.8.3 L2 cache coherency support and memory access ordering........................................ 5-29
5.8.3.1 L2 cache coherency model .................................................................................... 5-29
5.8.3.2 Snoop signaling ..................................................................................................... 5-29
5.8.3.3 Dynamic Harvard implementation......................................................................... 5-29
5.8.4 L2 cache control......................................................................................................... 5-30
5.8.4.1 Cache control instructions ..................................................................................... 5-30
5.8.4.2 Enabling and disabling the L2 cache ..................................................................... 5-31
5.8.4.3 L2 cache flash invalidation .................................................................................... 5-31
5.8.4.4 L2 cache line locking and unlocking ..................................................................... 5-32
5.8.4.5 L2 cache partitioning ............................................................................................. 5-32
5.8.4.6 L2 cache flushing................................................................................................... 5-33
5.8.5 L2 cache operation..................................................................................................... 5-33
5.8.5.1 L2 cache block replacement .................................................................................. 5-33
5.8.5.1.1 PLRU replacement............................................................................................. 5-33
5.8.5.1.2 SPLRU and SPLRU with Aging replacement ................................................... 5-34
5.8.5.1.3 FIFO replacement .............................................................................................. 5-34
5.8.5.2 Special scenarios for L2 cache .............................................................................. 5-34
5.8.5.2.1 Instruction Cache Block Invalidate (icbi).......................................................... 5-35
5.8.6 L2 cache errors........................................................................................................... 5-35
5.8.6.1 L2 cache ECC error injection ................................................................................ 5-36
5.8.7 L2 cache performance monitor events ....................................................................... 5-36
5.9 CoreNet Bus Interface Unit (BIU)................................................................................. 5-37
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Chapter 6
Memory Management Units (MMUs)
6.1 e6500 MMU overview ..................................................................................................... 6-1
6.1.1 MMU features.............................................................................................................. 6-1
6.1.2 TLB entry maintenance features.................................................................................. 6-2
6.2 Effective-to-real address translation ................................................................................ 6-3
6.2.1 Address translation ...................................................................................................... 6-3
6.2.2 Page table translation ................................................................................................... 6-5
6.2.2.1 Locating a hardware page table and PTE ................................................................ 6-5
6.2.2.2 Translation and TLB update using a PTE................................................................ 6-7
6.2.3 Page table entry (PTE)................................................................................................. 6-9
6.2.4 Address translation using external PID addressing ................................................... 6-10
6.2.5 Variable-sized pages .................................................................................................. 6-12
6.2.5.1 Checking for TLB entry hit ................................................................................... 6-13
6.2.6 Checking for access permissions ............................................................................... 6-13
6.3 Translation lookaside buffers (TLBs) ............................................................................ 6-14
6.3.1 L1 TLB arrays............................................................................................................ 6-15
6.3.2 L2 TLB arrays............................................................................................................ 6-16
6.3.2.1 Invalidation protection (IPROT) in TLB1 ............................................................. 6-17
6.3.2.2 Replacement algorithms for L2 MMU entries....................................................... 6-18
6.3.2.2.1 Round-robin replacement for TLB0 .................................................................. 6-19
6.3.3 Consistency between L1 and L2 TLBs...................................................................... 6-19
6.3.4 TLB entry field definitions ........................................................................................ 6-21
6.4 LRAT concept ................................................................................................................ 6-21
6.4.1 LRAT entries.............................................................................................................. 6-22
6.4.2 LRAT entry page size ................................................................................................ 6-23
6.4.3 Reading and writing LRAT entries ............................................................................ 6-24
6.4.4 Invalidating LRAT entries.......................................................................................... 6-25
6.4.5 LRAT translation........................................................................................................ 6-25
6.4.5.1 LRAT translation during tlbwe .............................................................................. 6-25
6.4.5.2 LRAT translation during page table translation..................................................... 6-26
6.5 TLB instructions—implementation ............................................................................... 6-26
6.5.1 TLB Read Entry (tlbre) instruction........................................................................... 6-27
6.5.1.1 Reading TLB1 and TLB0 array entries ................................................................. 6-27
6.5.2 TLB Write Entry (tlbwe) instruction......................................................................... 6-27
6.5.2.1 Writing to the TLB1 array ..................................................................................... 6-28
6.5.2.2 Writing to the TLB0 array ..................................................................................... 6-29
6.5.3 TLB Search (tlbsx) instruction—searching TLB1 and TLB0 arrays ........................ 6-29
6.5.4 TLB Invalidate Local Indexed (tlbilx) instruction..................................................... 6-29
6.5.5 TLB Invalidate (tlbivax) instruction.......................................................................... 6-30
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6.5.6 TLB Synchronize (tlbsync) Instruction..................................................................... 6-31
6.6 TLB entry maintenance—details ................................................................................... 6-31
6.7 TLB and LRAT states after reset ................................................................................... 6-32
6.8 The G bit (of WIMGE) .................................................................................................. 6-33
6.9 MMU parity detection and injection.............................................................................. 6-34
6.9.1 TLB0 parity detection................................................................................................ 6-34
6.9.2 TLB0 parity injection................................................................................................. 6-34
6.10 MMU registers ...............................................................................................................6-35
6.10.1 MAS register updates................................................................................................. 6-35
Chapter 7
Timer Facilities
7.1 Timer facilities ................................................................................................................. 7-1
7.2 Timer registers ................................................................................................................. 7-2
7.3 Watchdog timer implementation...................................................................................... 7-2
7.4 Performance monitor time base event.............................................................................. 7-3
Chapter 8
Power Management
8.1 Overview.......................................................................................................................... 8-1
8.2 Power management signals.............................................................................................. 8-2
8.3 Core power management states ....................................................................................... 8-3
8.4 Cluster power management states.................................................................................. 8-10
8.5 Power management protocol.......................................................................................... 8-11
8.6 AltiVec power down and power up................................................................................ 8-13
8.6.1 AltiVec power down—software controlled entry ...................................................... 8-13
8.6.2 AltiVec power down—hardware triggered entry ....................................................... 8-13
8.6.3 AltiVec low power state retention.............................................................................. 8-13
8.6.4 AltiVec power up—hardware triggered ..................................................................... 8-14
8.6.5 AltiVec power up sequence—software controlled..................................................... 8-14
8.7 e6500 cluster power management sequence .................................................................. 8-14
8.7.1 Cluster state PCL10 entry sequence .......................................................................... 8-14
8.7.2 Cluster PCL10 exit sequence ..................................................................................... 8-14
8.8 Interrupts and power management................................................................................. 8-15
Chapter 9
Debug and Performance Monitor Facilities
9.1 Overview.......................................................................................................................... 9-1
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9.1.1 Terminology................................................................................................................. 9-2
9.2 Debug resource sharing.................................................................................................... 9-2
9.2.1 Debug resource sharing between threads..................................................................... 9-2
9.2.2 Debug resource request—software debug agent.......................................................... 9-3
9.2.3 Debug resource request—external host debugger ....................................................... 9-3
9.2.4 Debug resource allocation—external host debugger ................................................... 9-3
9.2.5 Debug resource protection ........................................................................................... 9-4
9.2.5.1 Debug resource protection—from software debug agent’s perspective .................. 9-5
9.2.5.2 Debug resource protection—from external host debugger’s perspective ................ 9-5
9.3 Internal debug registers.................................................................................................... 9-6
9.4 External debug registers................................................................................................... 9-6
9.4.1 External Debug Control 0 (EDBCR0) register ............................................................ 9-6
9.4.2 External Debug Resource Request 0 (EDBRR0) register............................................ 9-8
9.4.3 External Debug Status 0 (EDBSR0) register ............................................................. 9-10
9.4.4 External Debug Status Mask 0 (EDBSRMSK0) register .......................................... 9-12
9.4.5 External Debug Status 1 (EDBSR1) register ............................................................. 9-13
9.4.6 External Debug Exception Syndrome (EDESR) register .......................................... 9-14
9.4.7 Processor Run Status (PRSR) register ....................................................................... 9-15
9.4.8 Extended External Debug Control 0 (EEDCR0) register .......................................... 9-17
9.4.9 Processor Debug Information (PDIR) register .......................................................... 9-17
9.4.10 Next Instruction Address (NIA) register.................................................................... 9-18
9.5 Nexus registers............................................................................................................... 9-18
9.5.1 Nexus Development Control 1 (DC1) register .......................................................... 9-18
9.5.2 Nexus Development Control 2 (DC2) register .......................................................... 9-20
9.5.3 Nexus Development Control 3 (DC3) register .......................................................... 9-21
9.5.4 Nexus Development Control 4 (DC4) register .......................................................... 9-22
9.5.5 Nexus Watchpoint Trigger Control 1 (WT1) register ................................................ 9-23
9.5.6 Nexus Watchpoint Trigger Control 2 (WT2) register ................................................ 9-25
9.5.7 Nexus Watchpoint Mask (WMSK) register............................................................... 9-26
9.5.8 Nexus Overrun Control (OVCR) register .................................................................. 9-27
9.5.9 Reloadable Counter Configuration (RCCR) register................................................. 9-28
9.5.10 Reloadable Counter Value (RCVR) register.............................................................. 9-29
9.5.11 Performance Monitor Snapshot Configuration (PMSCR) register............................ 9-30
9.6 Instruction Jamming (IJAM) registers ........................................................................... 9-31
9.6.1 IJAM Configuration (IJCFG) register........................................................................ 9-32
9.6.2 IJAM Instruction (IJIR) register ................................................................................ 9-33
9.6.3 IJAM data registers 0–3 (IJDATA0, IJDATA1, IJDATA2, IJDATA3) ....................... 9-33
9.7 Performance monitor registers (PMRs) ......................................................................... 9-33
9.8 Capture registers ............................................................................................................9-33
9.8.1 Performance monitor counter capture registers (PMCC0–PMCC5) ......................... 9-33
9.8.1.1 Program Counter Capture (PCC) register.............................................................. 9-34
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9.9 Debug events.................................................................................................................. 9-34
9.9.1 Embedded hypervisor ................................................................................................ 9-35
9.9.2 Internal and external debug modes ............................................................................ 9-35
9.9.3 Changing the debug facility state in internal debug mode......................................... 9-35
9.9.4 IAC, DAC, ICMP, BRT, IRPT, RET, CIRPT, CRET
debug condition response table.............................................................................. 9-36
9.9.5 Instruction address compare debug condition ........................................................... 9-36
9.9.6 Data address compare debug condition ..................................................................... 9-37
9.9.7 Instruction complete debug condition........................................................................ 9-38
9.9.8 Branch taken debug condition ................................................................................... 9-39
9.9.9 Interrupt taken debug condition................................................................................. 9-39
9.9.10 Interrupt return debug condition ................................................................................ 9-40
9.9.11 Critical interrupt taken debug condition .................................................................... 9-40
9.9.12 Critical return debug condition .................................................................................. 9-41
9.9.13 Unconditional debug event condition ........................................................................ 9-41
9.9.14 TRAP debug condition .............................................................................................. 9-42
9.9.15 Debugger Notify Interrupt (DNI) debug condition.................................................... 9-43
9.9.16 Dedicated debug halt request events.......................................................................... 9-44
9.9.16.1 Debug Halt Request (corex_dbg_halt_thrdn) input............................................... 9-45
9.9.16.2 Debugger Notify Halt (dnh) instruction................................................................. 9-45
9.9.16.3 Cross-thread debug halt requests ........................................................................... 9-46
9.9.17 Simultaneous debug event priorities.......................................................................... 9-46
9.9.17.1 Simultaneous debug event handing—events within same owner .......................... 9-47
9.9.17.2 Simultaneous debug event handing—events of different owners .......................... 9-48
9.10 External debug interface ................................................................................................ 9-48
9.10.1 Processor run states.................................................................................................... 9-48
9.10.1.1 Halt ........................................................................................................................ 9-48
9.10.1.1.1 Watchdog timer during debug halted state ........................................................ 9-49
9.10.1.2 Stop (freeze)...........................................................................................................9-49
9.10.1.3 Wait........................................................................................................................ 9-50
9.10.1.4 Thread disabled...................................................................................................... 9-50
9.10.1.5 Entering/exiting processor run states..................................................................... 9-50
9.10.2 Single-step ................................................................................................................. 9-52
9.10.3 Resource access ......................................................................................................... 9-52
9.10.3.1 Memory-mapped access ........................................................................................ 9-52
9.10.3.2 Special-purpose register access (Nexus only) ....................................................... 9-58
9.10.4 Instruction jamming................................................................................................... 9-58
9.10.4.1 Debug storage space (IJCFG[IJMODE] = 1) ........................................................ 9-59
9.10.4.2 Instruction jamming input...................................................................................... 9-61
9.10.4.3 Supported instruction jamming instructions.......................................................... 9-62
9.10.4.4 Instructions supported only during instruction jamming....................................... 9-64
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9.10.4.5 Exception conditions and affected architectural registers ..................................... 9-65
9.10.4.6 Instruction jamming status..................................................................................... 9-66
9.10.4.7 Special note on jamming store instructions........................................................... 9-66
9.10.4.8 Instruction jamming output.................................................................................... 9-67
9.10.4.9 IJAM procedure ..................................................................................................... 9-67
9.10.4.9.1 IJAM of instructions with input data ................................................................. 9-67
9.10.4.9.2 IJAM of instructions with output data ............................................................... 9-68
9.10.4.9.3 IJAM of instructions with no associated data.................................................... 9-68
9.10.4.9.4 IJAM of instructions to read or write SPRs, PMRs, CR, FPSCR, and MSR .... 9-68
9.10.4.10 Instruction jamming error conditions .................................................................... 9-69
9.11 Nexus trace..................................................................................................................... 9-69
9.11.1 Nexus features............................................................................................................9-70
9.11.2 Enabling Nexus operations on the processor ............................................................. 9-71
9.11.3 Modes of operation .................................................................................................... 9-71
9.11.4 Supported TCODEs ................................................................................................... 9-71
9.11.5 Nexus message fields................................................................................................. 9-78
9.11.5.1 TCODE field.......................................................................................................... 9-78
9.11.5.2 Source ID field (SRC)............................................................................................ 9-78
9.11.5.3 Relative Address field (U-ADDR)......................................................................... 9-79
9.11.5.4 Full Address field (F-ADDR)................................................................................ 9-79
9.11.5.5 Timestamp field (TSTAMP) .................................................................................. 9-79
9.11.6 Nexus message queues............................................................................................... 9-80
9.11.6.1 Message queue overrun ......................................................................................... 9-81
9.11.6.2 CPU stall ................................................................................................................ 9-81
9.11.6.3 Message suppression ............................................................................................. 9-81
9.11.7 Nexus message priority.............................................................................................. 9-81
9.11.7.1 Data Acquisition Message priority loss response and retry................................... 9-82
9.11.7.2 Ownership Trace message priority loss response and retry................................... 9-82
9.11.7.3 Program Trace Message priority loss response and retry ...................................... 9-83
9.11.8 Timestamp Correlation Message priority loss response and retry............................. 9-83
9.11.9 Performance Profile Message priority loss response and retry.................................. 9-83
9.11.10 Data Trace Message priority loss response and retry ................................................ 9-83
9.11.11 Debug Status messages .............................................................................................. 9-83
9.11.12 Error messages...........................................................................................................9-83
9.11.13 Resource full messages.............................................................................................. 9-84
9.11.14 Program Trace............................................................................................................9-84
9.11.14.1 Program Trace—enable and disable ...................................................................... 9-85
9.11.14.2 Lite Program Trace mode ...................................................................................... 9-86
9.11.14.2.1 Lite Program Trace mode—enabling ................................................................ 9-86
9.11.14.2.2 Lite Program Trace mode—how it works ......................................................... 9-86
9.11.14.2.3 Lite Program Trace mode—example................................................................. 9-88
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9.11.14.3 Sequential instruction count field .......................................................................... 9-89
9.11.14.4 Branch/predicate history events ............................................................................. 9-89
9.11.14.5 Indirect Branch message events............................................................................. 9-90
9.11.14.6 Resource Full events.............................................................................................. 9-90
9.11.14.7 Program Correlation events ................................................................................... 9-90
9.11.14.8 Synchronization conditions ................................................................................... 9-91
9.11.15 Data Trace .................................................................................................................. 9-92
9.11.15.1 Data Trace—enable and disable ............................................................................ 9-92
9.11.15.2 Data Trace range control........................................................................................ 9-93
9.11.15.3 Data Trace Size (DSZ) field .................................................................................. 9-94
9.11.15.4 Data Trace address field......................................................................................... 9-94
9.11.15.5 Data Trace data field.............................................................................................. 9-95
9.11.15.6 Data Trace message events .................................................................................... 9-95
9.11.16 Ownership Trace........................................................................................................ 9-95
9.11.16.1 Ownership Trace—enable and disable .................................................................. 9-95
9.11.16.2 Ownership Trace Process field .............................................................................. 9-96
9.11.16.3 Standard Ownership Trace message events........................................................... 9-96
9.11.16.4 “Sync” Ownership Trace message events.............................................................. 9-97
9.11.17 Data Acquisition Trace .............................................................................................. 9-97
9.11.17.1 Data Acquisition Trace—enable and disable......................................................... 9-97
9.11.17.2 Data Acquisition ID Tag field................................................................................ 9-98
9.11.17.3 Data Acquisition Data field ................................................................................... 9-98
9.11.17.4 Data Acquisition Trace event................................................................................. 9-98
9.11.18 Watchpoint Trace ....................................................................................................... 9-98
9.11.18.1 Watchpoint events.................................................................................................. 9-98
9.11.18.2 Watchpoint Trace—enable and disable ............................................................... 9-100
9.11.18.3 Watchpoint Hit field............................................................................................. 9-100
9.11.18.4 Watchpoint Trace message events ....................................................................... 9-101
9.11.19 Timestamp Correlation messages ............................................................................ 9-101
9.11.20 Performance Profile messages ................................................................................. 9-101
9.11.20.1 Performance Profile messages—enable and disable ........................................... 9-101
9.11.20.2 Performance Profile message events ................................................................... 9-102
9.11.20.3 Performance Profile message configuration ........................................................ 9-102
9.11.20.4 Performance Profile Sync field............................................................................ 9-102
9.12 Performance monitor ................................................................................................... 9-102
9.12.1 Overview.................................................................................................................. 9-103
9.12.2 Performance monitor instructions............................................................................ 9-105
9.12.3 Performance monitor interrupt................................................................................. 9-105
9.12.4 Event counting ......................................................................................................... 9-106
9.12.4.1 Processor context configurability ........................................................................ 9-106
9.12.4.2 Processor performance monitor and program counter capture function ............. 9-107
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9.12.5 Examples.................................................................................................................. 9-108
9.12.5.1 Chaining counters ................................................................................................ 9-108
9.12.6 Event selection ......................................................................................................... 9-109
Chapter 10
Execution Timing
10.1 Terminology and conventions........................................................................................ 10-1
10.2 Instruction timing overview ........................................................................................... 10-3
10.3 General timing considerations ....................................................................................... 10-6
10.3.1 General instruction flow ............................................................................................ 10-7
10.3.2 Instruction fetch timing considerations...................................................................... 10-8
10.3.2.1 L1 and L2 TLB access times ................................................................................. 10-8
10.3.2.2 Interrupts associated with instruction fetching ...................................................... 10-9
10.3.2.3 Cache-related latency............................................................................................. 10-9
10.3.3 Dispatch, issue, and completion considerations ...................................................... 10-10
10.3.3.1 Instruction serialization ....................................................................................... 10-11
10.3.4 Memory synchronization timing considerations...................................................... 10-12
10.3.4.1 sync instruction timing considerations ................................................................ 10-12
10.3.4.2 mbar instruction timing considerations .............................................................. 10-13
10.4 Execution ..................................................................................................................... 10-13
10.4.1 Branch execution unit .............................................................................................. 10-14
10.4.1.1 Branch instructions and completion .................................................................... 10-14
10.4.1.2 Branch prediction and resolution......................................................................... 10-15
10.4.1.2.1 Branch predictor structure and operation ........................................................ 10-16
10.4.1.2.2 Global History (GHR) register and Pattern History Table (PHT) ................... 10-17
10.4.1.2.3 Segment Target Address Cache (STAC), Segment Target Index
Cache (STIC), and link stack....................................................................... 10-17
10.4.1.2.4 Branch predictor operations controlled by BUCSR ........................................ 10-18
10.4.1.2.5 Branch prediction special cases: multiple matches and phantom branches .... 10-19
10.4.1.3 Changing LR and CTR in branch instructions .................................................... 10-19
10.4.2 Complex and simple unit execution......................................................................... 10-19
10.4.2.1 CFX divide execution .......................................................................................... 10-20
10.4.2.2 CFX multiply execution....................................................................................... 10-20
10.4.2.3 CFX bypass path.................................................................................................. 10-21
10.4.3 AltiVec (vector) execution ....................................................................................... 10-22
10.4.4 Load/store execution................................................................................................ 10-23
10.4.4.1 Effect of operand placement on performance...................................................... 10-23
10.5 Instruction latency summary........................................................................................ 10-24
10.6 Instruction scheduling guidelines ................................................................................ 10-45
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Chapter 11
Core and Cluster Software Initialization Requirements
11.1 Core and cluster state and software initialization after reset ......................................... 11-1
11.2 MMU state ..................................................................................................................... 11-1
11.3 Thread state.................................................................................................................... 11-1
11.4 Core register state .......................................................................................................... 11-2
11.4.1 GPRs .......................................................................................................................... 11-2
11.4.2 FPRs........................................................................................................................... 11-2
11.4.3 VRs ............................................................................................................................ 11-3
11.4.4 SPRs........................................................................................................................... 11-3
11.4.5 MSR, FPSCR, and VSCR.......................................................................................... 11-4
11.5 Timer state...................................................................................................................... 11-5
11.6 L1 cache state................................................................................................................. 11-5
11.7 L2 cache state................................................................................................................. 11-6
11.8 Branch target buffer state ............................................................................................... 11-7
Appendix A
Simplified Mnemonics
A.1 Overview......................................................................................................................... A-1
A.2 Subtract simplified mnemonics....................................................................................... A-1
A.2.1 Subtract immediate ..................................................................................................... A-1
A.2.2 Subtract ....................................................................................................................... A-2
A.3 Rotate and shift simplified mnemonics........................................................................... A-2
A.3.1 Operations on words ................................................................................................... A-2
A.3.2 Operations on doublewords ........................................................................................ A-3
A.4 Branch instruction simplified mnemonics ...................................................................... A-4
A.4.1 Key facts about simplified branch mnemonics ........................................................... A-5
A.4.2 Eliminating the BO operand ....................................................................................... A-6
A.4.3 Incorporating the BO branch prediction ..................................................................... A-7
A.4.4 The BI operand—CR bit and field representations .................................................... A-8
A.4.4.1 BI operand instruction encoding............................................................................. A-8
A.4.4.1.1 Specifying a CR bit............................................................................................. A-9
A.4.4.1.2 The crS operand ............................................................................................... A-11
A.4.5 Simplified mnemonics that incorporate the BO operand.......................................... A-11
A.4.5.1 Examples that Eliminate the BO Operand............................................................ A-12
A.4.6 Simplified mnemonics that incorporate CR conditions (eliminate BO
and replace BI with crS)....................................................................................... A-15
A.4.6.1 Branch simplified mnemonics that incorporate CR conditions:
examples ........................................................................................................... A-17
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