NXP LPC4078FBD144 User guide

Type
User guide
UM10562
LPC408x/407x User manual
Rev. 3 — 12 March 2014 User manual
Document information
Info Content
Keywords ARM, ARM Cortex-M4, 32-bit, USB, Ethernet, LCD, CAN, I
2
C, I
2
S, Flash,
EEPROM, Microcontroller
Abstract LPC408x/407x user manual
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Contact information
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For sales office addresses, please send an email to: [email protected]
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LPC408x/407x User Manual
Revision history
Rev Date Description
3 20140312
Figure 16 “EMC block diagram updated and CCLK renamed to EMCCLK throughout the
chapter.
Update Section 9.11.1 “Mode register setup.
Function SSP2_SCK added to pin P5[2]. See Table 75 and Table 90.
Function SSP2_SSEL added to pin P5[3]. See Table 75 and Table 90.
Updated the description of the ROM_LAT bit in Table 7 “Matrix Arbitration register (MATRIXARB
- 0x400F C188) bit description. This bit should be 1 for normal operation.
Figure 23 “Ethernet packet fields updated with the correct order of octets in the MAC address.
Description of FLASHTIM bit values 0x11 and 0x100 corrected in Table 50 “Flash Accelerator
Configuration register (FLASHCFG - address 0x400F C000) bit description.
IRCCTRL register added. See Table 34IRC control register (IRCCTRL - address
0x400F C1A4) bit description.
Incorrect reference to VREFN removed in Table 684 “D/A Pin Description and Table 686 “D/A
Converter Register (CR - address 0x4008 C000) bit description.
Description of the SPIFI software library removed. The description is available on
LPCWare.com
.
Description of the SPIFI hardware and register interface added. See Section 15.7.
Description of the SLEW bit improved. See Table 83Type D IOCON registers bit description.
2 20130306
Added LQFP100.
Minor updates and corrections.
1 20120913
Initial LPC408x/407x User manual version.
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1.1 Introduction
The LPC408x/407x is an ARM Cortex-M4 based microcontroller for embedded
applications requiring a high level of integration and low power dissipation.
The Cortex-M4 processor is a high-performance 32-bit processor with a 3-stage pipeline
Harvard architecture with separate local instruction and data buses, as well as a third bus
with slightly lower performance for peripherals. The Cortex-M4 uses the Thumb®
instruction set, providing high code density and reduced program memory requirements.
The Cortex-M4 CPU also includes an internal prefetch unit that supports speculative
branches. The LPC408x/407x adds a specialized flash memory accelerator to give
optimal performance when executing code from flash. The LPC408x/407x is targeted to
operate at up to a 120 MHz CPU frequency under worst case commercial conditions.
The peripheral complement of the LPC408x/407x includes up to 512 kB of Flash memory,
up to 96 kB of data memory, 4,032 bytes of EEPROM memory, an External Memory
Controller for SDRAM and static memory access, an LCD panel controller, an Ethernet
MAC, a high speed SPI flash memory interface (SPIFI), a General Purpose DMA
controller, a USB device/host/OTG interface, 5 UARTs, 3 SSP controllers, 3 I
2
C
interfaces, an I
2
S serial audio interface, a 2-channel CAN interface, an SD card interface,
an 8 channel 12-bit ADC, a 10-bit DAC, analog comparators, a Motor Control PWM, a
Quadrature Encoder Interface, 4 general purpose timers, a 6-output general purpose
PWM, an ultra-low power RTC with separate battery supply and event monitor/recorder, a
windowed watchdog timer, a CRC calculation engine, up to 165 general purpose I/O pins,
and more.
See Section 41.2 “References”
for additional documentation related to the LPC408x/407x
parts.
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Chapter 1: Introductory information
Rev. 3 — 12 March 2014 User manual
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Chapter 1: Introductory information
1.2 Features
Refer to Section 1.4 for details of features for specific part numbers.
Functional replacement for LPC23xx and 24xx family devices.
ARM Cortex-M4 processor, running at frequencies of up to 120 MHz. The Cortex-M4
executes the Thumb®-2 instruction set for optimal performance and code size,
including hardware division, single cycle multiply, and bit-field manipulation. A
Memory Protection Unit (MPU) supporting eight regions is included.
Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).
Cortex-M4 Floating Point Unit (FPU), supporting single-precision floating-point
computation functionality in compliance with the ANSI/IEEE Standard 754-2008. The
FPU provides add, subtract, multiply, divide, multiply and accumulate, and square root
operations. It also performs a variety of conversions between fixed-point,
floating-point, and integer data formats. The FPU is not available on LPC4074
devices.
Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. The combination of an enhanced flash
memory accelerator and location of the flash memory on the CPU local code/data bus
provides high code performance from flash.
Up to 96 kB on-chip SRAM includes:
Up to 64 kB of Main SRAM on the CPU code/data bus for high-performance CPU
access.
Up to two 16 kB SRAM blocks with separate access paths for higher throughput.
These SRAM blocks may be used for Ethernet, USB, LCD, and DMA memory, as
well as for general purpose instruction and data storage.
Up to 4,032 bytes of on-chip EEPROM.
External Memory Controller provides support for asynchronous static memory devices
such as RAM, ROM and Flash up to 64 MB, as well as dynamic memories such as
Single Data Rate SDRAM.
Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer
matrix that can be used with the SSP, I
2
S, UART, SD/MMC, CRC engine,
Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals,
GPIO, and for memory-to-memory transfers.
Multilayer AHB matrix interconnect provides a separate bus for each AHB master.
AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, LCD
controller, and the USB interface. This interconnect provides communication with no
arbitration delays unless two masters attempt to access the same slave at the same
time.
Split APB bus allows for higher throughput with fewer stalls between the CPU and
DMA. A single level of write buffering allows the CPU to continue without waiting for
completion of APB writes if the APB was not already busy.
LCD controller, supporting both Super-Twisted Nematic (STN) and Thin-Film
Transistor (TFT) displays. The LCD controller is not available on LPC407x devices.
Dedicated DMA controller.
Selectable display resolution (up to 1024 × 768 pixels).
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Supports up to 24-bit true-color mode.
Serial interfaces:
Ethernet MAC with MII/RMII interface and dedicated DMA controller.
USB 2.0 full-speed controller that can be configured for either device, Host, or
OTG operation with an on-chip PHY for device and Host functions and a dedicated
DMA controller. USB Host and OTG are not available on LPC4074 devices.
Five UARTs with fractional baud rate generation, internal FIFOs, IrDA, DMA
support, and RS-485/EIA-485 support on most LPC408x/407x devices. UART1
also has a full set of modem handshaking signals. UART4 includes a synchronous
mode and a smart card mode supporting ISO 7816-3. UART4 is not available on
LPC4074 devices.
Three SSP controllers with FIFO and multi-protocol capabilities. The SSP
interfaces can be used with the GPDMA controller.
Three enhanced I
2
C-bus interfaces, one with an open-drain output supporting the
full I
2
C specification and Fast mode Plus with data rates of 1Mbit/s, two with
standard port pins. Enhancements include multiple address recognition and
monitor mode.
Two-channel CAN controller.
I
2
S (Inter-IC Sound) interface for digital audio input or output, with fractional rate
control. The I
2
S interface can be used with the GPDMA. The I
2
S interface supports
3-wire data transmit and receive or 4-wire combined transmit and receive
connections, as well as master clock output.
SPIFI (SPI Flash Interface). This interface uses an SPI bus superset with 4 data
lines to access off-chip Quad SPI Flash memory at a much higher rate than is
possible using standard SPI or SSP interfaces. The SPIFI function allows memory
mapping the contents of the off-chip SPI Flash memory such that it can be
executed as if it were on-chip code memory. Supports SPI memories with 1 or 4
data lines.
Other peripherals:
SD card interface that also supports MMC cards. The SD card interface is not
available on LPC4074 devices.
General Purpose I/O (GPIO) pins with configurable pull-up/down resistors, open
drain mode, and repeater mode. All GPIOs are located on an AHB bus for fast
access, and support Cortex-M4 bit-banding. GPIOs can be accessed by the
General Purpose DMA Controller. Any pin of ports 0 and 2 can be used to generate
an interrupt. There are 165 GPIOs on 208-pin packages, 141 GPIOs on 180-pin
packages, and 109 GPIOs on 144-pin packages.
12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins,
conversion rates up to 400 kHz, and multiple result registers. The 12-bit ADC can
be used with the GPDMA controller.
10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA
support.
Dual analog comparator with multiple selectable inputs, selectable internal
reference voltages, and versatile interrupt generation. The comparators are not
available on LPC4074 devices.
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Four general purpose timers/counters, with a total of eight capture inputs and ten
compare outputs. Each timer block has an external count input. Specific timer
events can be selected to generate DMA requests.
One motor control PWM with support for three-phase motor control.
Quadrature encoder interface that can monitor one external quadrature encoder.
The QEI is not available on LPC4074 devices.
Two standard PWM/timer blocks with external count input option.
Real-Time Clock (RTC) with a separate power domain. The RTC is clocked by a
dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered
backup registers, allowing system status to be stored when the rest of the chip is
powered off. Battery power can be supplied from a standard 3 V Lithium button
cell. The RTC will continue working when the battery voltage drops to as low as
2.1 V. An RTC interrupt can wake up the CPU from any reduced power mode.
Event Monitor/Recorder that can capture the RTC value when an event occurs on
any of 3 inputs. The event identification and the time it occurred are stored in
registers. The Event Monitor/Recorder is in the RTC power domain, and can
therefore operate as long as there is RTC power.
Windowed Watchdog Timer (WWDT). Windowed operation, dedicated internal
oscillator, watchdog warning interrupt, and safety features.
CRC Engine block can calculate a CRC on supplied data using 1 of 3 standard
polynomials. The CRC engine can be used in conjunction with the DMA controller
to generate a CRC without CPU involvement in the data transfer.
Cortex-M4 system tick timer, including an external clock input option.
Standard JTAG test/debug interface as well as Serial Wire Debug and Serial Wire
Trace Port options.
Emulation trace module supports real-time trace.
Single 3.3 V power supply (2.4 V to 3.6 V). Temperature range of -40 °C to 85 °C.
Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
Power-down.
Power savings for operation at or below 100 MHz by reducing on-chip regulator
output.
Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0
and PORT2 can be used as edge sensitive interrupt sources.
Non-maskable Interrupt (NMI) input.
Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock,
CPU clock, USB clock, SPIFI clock, or the watchdog timer clock.
The Wakeup Interrupt Controller (WIC) allows the CPU to automatically wake up from
any priority interrupt that can occur while the clocks are stopped in deep sleep,
Power-down, and Deep Power-down modes.
Processor wake-up from Power-down mode via any interrupt able to operate during
Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet
wake-up interrupt, CAN bus activity, PORT0/2 pin interrupt, and NMI).
Brownout detect with separate threshold for interrupt and forced reset.
On-chip Power-On Reset (POR).
On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.
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12 MHz Internal RC oscillator (IRC) trimmed to 1% accuracy that can optionally be
used as a system clock.
An on-chip PLL allows CPU operation up to the maximum CPU rate without the need
for a high-frequency crystal. May be run from the main oscillator or the internal RC
oscillator.
A second, dedicated PLL may be used for the USB and/or SPIFI interfaces in order to
allow added flexibility for the Main PLL settings.
Versatile pin function selection feature allows many possibilities for using on-chip
peripheral functions.
Boundary scan for simplified board testing.
Unique device serial number for identification purposes.
Available as 208-pin LQFP, 208-pin TFBGA, 180-pin TFBGA, 144-pin LQFP, 80-pin
LQFP packages.
1.3 Applications
Communications
Point-of-sale terminals, Web servers, multi-protocol bridges
Industrial/Medical
Automation controllers, application control, robotic controls, HVAC, PLC, inverters,
circuit breakers, medical scanning, security monitoring, motor drive, video intercom
Consumer/Appliance
Audio, MP3 decoders, alarm systems, displays, printers, scanners, small
appliances, fitness equipment
Automotive
Aftermarket, car alarms, GPS/Fleet Monitor
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Chapter 1: Introductory information
1.4 Ordering information
1.4.1 Part options summary
Table 1. Ordering information
Type number Package
Name Description Version
LPC4088
LPC4088FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1
LPC4088FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body
15 15 0.7 mm
SOT950-1
LPC4088FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 12 0.8 mm SOT570-2
LPC4088FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC4078
LPC4078FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1
LPC4078FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body
15 15 0.7 mm
SOT950-1
LPC4078FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 12 0.8 mm SOT570-2
LLPC4078FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC4078FBD80 LQFP80 plastic low-profile quad package; 80 leads; body 12 12 1.4 mm SOT315-1
LPC4078FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1
LPC4076
LPC4076FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 12 0.8 mm SOT570-2
LPC4076FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC4074
LPC4074FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC4074FBD80 LQFP80 plastic low-profile quad package; 80 leads; body 12 12 1.4 mm SOT315-1
LPC4072
LPC4072FBD80 LQFP80 plastic low-profile quad package; 80 leads; body 12 12 1.4 mm SOT315-1
Table 2. Ordering options
Type number
Flash (kB)
SRAM (kB)
EEPROM (B)
EMC bus
width (bit)
LCD
Ethernet
USB
UART
QEI
SD/MMC
Comparator
FPU
Package
LPC4088
LPC4088FBD208 512 96 4032 32 yes yes H/O/D 5 yes yes yes yes LQFP208
LPC4088FET208 512 96 4032 32 yes yes H/O/D 5 yes yes yes yes TFBGA208
LPC4088FET180 512 96 4032 16 yes yes H/O/D 5 yes yes yes yes TFBGA180
LPC4088FBD144 512 96 4032 8 yes yes H/O/D 5 yes yes yes yes LQFP144
LPC4078
LPC4078FBD208 512 96 4032 32 no yes H/O/D 5 yes yes yes yes LQFP208
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LPC4078FET208 512 96 4032 32 no yes H/O/D 5 yes yes yes yes TFBGA208
LPC4078FET180 512 96 4032 16 no yes H/O/D 5 yes yes yes yes TFBGA180
LPC4078FBD144 512 96 4032 8 no yes H/O/D 5 yes yes yes yes LQFP144
LPC4078FBD100 512 96 4032 - no yes H/O/D 5 yes yes yes yes LQFP100
LPC4078FBD80 512 96 4032 - no yes H/O/D 5 yes yes yes yes LQFP80
LPC4076
LPC4076FET180 256 80 2048 16 no yes H/O/D 5 yes yes yes yes TFBGA180
LPC4076FBD144 256 80 2048 8 no yes H/O/D 5 yes yes yes yes LQFP144
LPC4074
LPC4074FBD144 128 40 2048 - no no D 4 no no no no LQFP144
LPC4074FBD80 128 40 2048 - no no D 4 no no no no BGA80
LPC4072
LPC4072FBD80 64 24 2048 - no no D 4 no no no no LQFP80
Table 2. Ordering options
Type number
Flash (kB)
SRAM (kB)
EEPROM (B)
EMC bus
width (bit)
LCD
Ethernet
USB
UART
QEI
SD/MMC
Comparator
FPU
Package
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1.5 Simplified block diagram
Fig 1. LPC408x/407x simplified block diagram
ARM Cortex-M4
with FPU
JTAG
interface
TEST/DEBUG
INTERFACE
General
Purpose
DMA
controller
System
bus
D-code
bus
I-code
bus
clock generation,
power control,
and other
system functions
SRAM
Up to 96 kB
Boot ROM
8 kB
Flash
Up to 512 kB
RST
Xtalin
Xtalout
clocks
and
controls
Flash
Accelerator
Ethernet
10/100
MAC
USB
OTG/
Host/
Device
LCD
panel
interface
Ethernet PHY
interface
USB bus or
tranceiver
LCD
panel
CRC
engine
General Purpose
I/O ports
EEPROM
Up to 4 kB
120229
Multilayer AHB Matrix
Static / Dynamic
Memory Controller
Ethernet
registers
USB
registers
LCD
registers
26-bit addr
32-bit data
APB slave group 0
Capture/Match timer 0 & 1
Watchdog oscillator Windowed Watchdog
SSP1
UARTs 0 & 1
CAN 1 & 2
12-bit ADC
Pin connect block
GPIO interrupt control
I
2
C 0 & 1
PWM0 & 1
APB slave group 1
Note:
- Orange shaded peripheral blocks
support General Purpose DMA.
- Yellow shaded peripheral blocks
include a dedicated DMA controller.
UARTs 2, 3, & 4
SSP0 & 2
System control
DAC
External interrupts
Motor control PWM
I
2
S
I
2
C 2
SD card interface
Capture/Match timer 2 & 3
Quadrature Encoder i/f
RTC Power Domain
32 kHz oscillator
Backup registers
(20 bytes)
ultra-low power
regulator
Vbat
ALARM
Real Time Clock
Event Inputs
Event Monitor/
Recorder
SPI Flash
Interface
Analog comparators
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1.6 Architectural overview
The ARM Cortex-M4 includes three AHB-Lite buses, one system bus and the I-code and
D-code buses which are faster and are used similarly to Tightly Coupled Memory
interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access
(D-code). The use of two core buses allows for simultaneous operations if concurrent
operations target different devices.
The LPC408x/407x uses a multi-layer AHB matrix to connect the Cortex-M4 buses and
other bus masters to peripherals in a flexible manner that optimizes performance by
allowing peripherals on different slaves ports of the matrix to be accessed simultaneously
by different bus masters. Details of the multilayer matrix connections are shown in
Figure 2
.
APB peripherals are connected to the CPU via two APB buses using separate slave ports
from the multilayer AHB matrix. This allows for better performance by reducing collisions
between the CPU and the DMA controller. The APB bus bridges are configured to buffer
writes so that the CPU or DMA controller can write to APB devices without always waiting
for APB write completion.
1.7 ARM Cortex-M4 processor
The ARM Cortex-M4 is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The Cortex-M4 offers a Thumb-2
instruction set, low interrupt latency, interruptible/continuable multiple load and store
instructions, automatic state save and restore for interrupts, tightly integrated interrupt
controller, and multiple core buses capable of simultaneous accesses.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
Information about Cortex-M4 configuration options can be found in Section 40.1
.
1.8 On-chip flash memory system
The LPC408x/407x contains up to 512 kB of on-chip flash memory. A flash memory
accelerator maximizes performance for CPU accesses. This memory may be used for
both code and data storage. Programming of the flash memory may be accomplished in
several ways. It may be programmed In System via the serial port. The application
program may also erase and/or program the flash while the application is running,
allowing a great degree of flexibility for data storage field firmware upgrades, etc.
1.9 On-chip Static RAM
The LPC408x/407x contains up to 96 kB of on-chip static RAM memory. Up to 64 kB of
SRAM, accessible by the CPU and the General Purpose DMA controller, is on a
higher-speed bus. Up to 32 kB SRAM is provided in up to two additional 16 kB SRAM
blocks for use primarily for peripheral data. When both SRAMs are present, they are
situated on separate slave ports on the AHB multilayer matrix.
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This architecture allows the possibility for CPU and DMA accesses to be separated in
such a way that there are few or no delays for the bus masters. It also allows separation of
data for different peripherals functions, in order to improve system performance. For
example, LCD DMA can be occurring in one SRAM while Ethernet DMA is occurring in
another, all while the CPU is using the Main SRAM for data and/or instruction access.
1.10 On-chip EEPROM
The LPC408x/407x contains up to 4,032 bytes of on-chip EEPROM memory. The
EEPROM is accessible only by the CPU.
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1.11 Detailed block diagram
Fig 2. LPC408x/407x block diagram, CPU and buses
Multilayer
AHB Matrix
ARM Cortex-M4
with FPU
AHB to
APB bridge
AHB to
APB bridge
JTAG
interface
Periph. SRAM
Up to 16 kB
TEST/DEBUG
INTERFACE
General
Purpose
DMA
controller
System
bus
D-code
bus
I-code
bus
clock generation,
power control,
and other
system functions
Main SRAM
Up to 64 kB
Boot ROM
8 kB
Flash
Up to 512 kB
RST
Xtalin
Xtalout
APB slave group 1
Note:
- Orange shaded peripheral blocks
support General Purpose DMA.
- Yellow shaded peripheral blocks
include a dedicated DMA controller.
APB slave group 0
voltage regulator
clocks
and
controls
internal
power
Vdd
CLK
OUT
Capture/Match timer 0 & 1
Flash
Accelerator
Driver ROM
16 kB
Ethernet
10/100
MAC
USB
OTG/
Host/Dev
LCD
panel
interface
Static / Dynamic
Memory
Controller
D[31:0]
A[25:0]
control
Periph. SRAM
Up to 16 kB
Ethernet PHY
interface
USB bus or
tranceiver
LCD
panel
Watchdog oscillator Windowed Watchdog
Ethernet
registers
GPDMA
registers
CRC
engine
USB
registers
LCD
registers
HS
GPIO
Mem Ctl
registers
SSP1
UARTs 0 & 1
CAN 1 & 2
12-bit ADC
Pin connect block
GPIO interrupt control
I
2
C 0 & 1
PWM0 & 1
UARTs 2, 3, & 4
SSP0 & 2
System control
DAC
External interrupts
Motor control PWM
I
2
S
I
2
C 2
SD card interface
Capture/Match timer 2 & 3
Quadrature Encoder i/f
EEPROM
Up to 4 kB
120621
RTC Power Domain
32 kHz oscillator
Backup registers
(20 bytes)
ultra-low power
regulator
Vbat
ALARM
Real Time Clock
Event Inputs
Event Monitor/
Recorder
SPI Flash
Interface
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2.1 Memory map and peripheral addressing
The ARM Cortex-M4 processor has a single 4 GB address space. The following table
shows how this space is used on the LPC408x/407x.
[1] Can be up to 256 MB, upper address 0x8FFF FFFF, if the address shift mode is enabled. See SCS register
bit 0 (Section 3.3.7.1
).
[2] Can be up to 128 MB, upper address 0x97FF FFFF, if the address shift mode is enabled. See SCS register
bit 0 (Section 3.3.7.1
).
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Rev. 3 — 12 March 2014 User manual
Table 3. Memory usage and details
Address range General Use Address range details and description
0x0000 0000 to
0x1FFF FFFF
On-chip non-volatile
memory
0x0000 0000 - 0x0007 FFFF For devices with 512 kB of flash memory.
0x0000 0000 - 0x0003 FFFF For devices with 256 kB of flash memory.
0x0000 0000 - 0x0001 FFFF For devices with 128 kB of flash memory.
On-chip SRAM 0x1000 0000 - 0x1000 FFFF For devices with 64 kB of Main SRAM.
0x1000 0000 - 0x1000 7FFF For devices with 32 kB of Main SRAM.
Boot ROM 0x1FFF 0000 - 0x1FFF 7FFF 8 kB Boot ROM with flash services.
Driver ROM 0x1FFF 8000 - 0x1FFF 1FFF 16 kB Driver ROM
0x2000 0000 to
0x3FFF FFFF
On-chip SRAM
(typically used for
peripheral data)
0x2000 0000 - 0x2000 1FFF Peripheral SRAM - bank 0 (first 8 kB)
0x2000 2000 - 0x2000 3FFF Peripheral SRAM - bank 0 (second 8 kB)
0x2000 4000 - 0x2000 7FFF Peripheral SRAM - bank 1 (16 kB)
AHB peripherals 0x2008 0000 - 0x200B FFFF See Section 2.3.1
for details
SPIFI buffer space 0x2800 0000 - 0x28FF FFFF SPIFI memory mapped access space
0x4000 0000 to
0x7FFF FFFF
APB Peripherals 0x4000 0000 - 0x4007 FFFF APB0 Peripherals, up to 32 peripheral blocks of
16 kB each.
0x4008 0000 - 0x400F FFFF APB1 Peripherals, up to 32 peripheral blocks of
16 kB each.
0x8000 0000 to
0xDFFF FFFF
Off-chip Memory via
the External Memory
Controller
Four static memory chip selects:
0x8000 0000 - 0x83FF FFFF Static memory chip select 0 (up to 64 MB)
[1]
0x9000 0000 - 0x93FF FFFF Static memory chip select 1 (up to 64 MB)
[2]
0x9800 0000 - 0x9BFF FFFF Static memory chip select 2 (up to 64 MB)
0x9C00 0000 - 0x9FFF FFFF Static memory chip select 3 (up to 64 MB)
Four dynamic memory chip selects:
0xA000 0000 - 0xAFFF FFFF Dynamic memory chip select 0 (up to 256MB)
0xB000 0000 - 0xBFFF FFFF Dynamic memory chip select 1 (up to 256MB)
0xC000 0000 - 0xCFFF FFFF Dynamic memory chip select 2 (up to 256MB)
0xD000 0000 - 0xDFFF FFFF Dynamic memory chip select 3 (up to 256MB)
0xE000 0000 to
0xE00F FFFF
Cortex-M4 Private
Peripheral Bus
0xE000 0000 - 0xE00F FFFF Cortex-M4 related functions, includes the NVIC
and System Tick Timer.
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User manual Rev. 3 — 12 March 2014 15 of 947
NXP Semiconductors
UM10562
Chapter 2: LPC408x/407x Memory map
2.2 Memory maps
The LPC408x/407x incorporates several distinct memory regions, shown in the following
figures. Figure 3
shows the overall map of the entire address space from the user
program viewpoint following reset. The interrupt vector area supports address remapping,
which is described later in this section.
Figure 3
and Table 5 show different views of the peripheral address space. The AHB
peripheral area is 2 megabyte in size, and is divided to allow for up to 128 peripherals.
The APB peripheral area is 1 megabyte in size and is divided to allow for up to 64
peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows
simplifying the address decoding for each peripheral.
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User manual Rev. 3 — 12 March 2014 16 of 947
NXP Semiconductors
UM10562
Chapter 2: LPC408x/407x Memory map
Fig 3. System memory map
31-24
23
22-19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x4008 0000
0x4006 0000
0x4005 C000
0x4004 C000
0x4004 8000
0x4004 4000
0x4004 0000
0x4003 C000
0x4003 8000
0x4003 4000
0x4003 0000
0x4002 C000
0x4002 8000
0x4002 4000
0x4002 0000
0x4001 C000
0x4001 8000
0x4001 4000
0x4001 0000
0x4000 C000
0x4000 8000
0x4000 4000
0x4000 0000
reserved
I2C1
reserved
CAN 2
CAN 1
CAN common
CAN AF registers
CAN AF RAM
ADC
SSP1
pin connect
GPIO interrupts
RTC
Comparators
I2C0
PWM1
PWM0
UART1
UART0
Timer1
Timer0
Watchdog timer
APB0 peripherals
7
6
5
4
3
2
1
0
0x200A 0000
0x2009 C000
0x2009 8000
0x2009 4000
0x2009 0000
0x2008 C000
0x2008 8000
0x2008 4000
0x2008 0000
EMC registers
GPIO
SPIFI registers
CRC engine
USB
LCD controller
Ethernet
GP DMA ctlr
AHB peripherals
I-Code and
D-Code
memory space
31
30-17
16
15
14
13-12
11
10
9
8
7
6
5
4
3
2
1-0
0x4010 0000
0x400F C000
0x400C 4000
0x400C 0000
0x400B C000
0x400B 8000
0x400B 0000
0x400A C000
0x400A 8000
0x400A 4000
0x400A 0000
0x4009 C000
0x4009 8000
0x4009 4000
0x4009 0000
0x4008 C000
0x4008 8000
0x4008 0000
system control
reserved
SD card
QEI
motor ctl PWM
reserved
SSP2
I2S
UART4
I2C2
UART3
UART2
Timer3
Timer2
DAC
SSP0
reserved
APB1 peripherals
0.5 GB
1 GB
2 GB
4 GB
active interrupt
vectors
0x0400
0x0000
reserved
private peripheral bus
external memory
(4 dynamic chip selects)
APB peripheral group 1
APB peripheral group 0
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
AHB peripherals
Boot ROM and Driver ROM
external memory
(4 static chip selects)
APB peripheral
bit-band addressing
SPIFI memory
mapped space
peripheral SRAM 1
peripheral SRAM 0
64 kB Main SRAM
512 kB flash memory
Memory space
0xFFFF FFFF
0xE010 0000
0xE004 0000
0xE000 0000
0xA000 0000
0x8000 0000
0x4400 0000
0x4200 0000
0x4010 0000
0x4008 0000
0x4000 0000
0x2900 0000
0x2800 0000
0x200C 0000
0x2000 4000
0x2000 0000
0x1FFF 0000
0x1001 0000
0x1000 0000
0x0008 0000
0x0000 0000
0x2400 0000
0x2200 0000
0x2008 0000
peripheral SRAM bit-band
addressing
120420
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User manual Rev. 3 — 12 March 2014 17 of 947
NXP Semiconductors
UM10562
Chapter 2: LPC408x/407x Memory map
2.3 On-chip peripherals
All peripheral register addresses are word aligned (to 32-bit boundaries) regardless of
their size. This eliminates the need for byte lane mapping hardware that would be required
to allow byte (8-bit) or half-word (16-bit) accesses to occur at smaller boundaries. An
implication of this is that word and half-word registers must be accessed all at once. For
example, it is not possible to read or write the upper byte of a word register separately.
2.3.1 AHB peripherals
The following table shows the addresses of peripheral functions that reside directly on the
AHB bus matrix. Complete register descriptions may be found in the relevant chapters.
2.3.2 APB peripheral addresses
The following table shows the address maps of the 2 APB buses. APB peripherals do not
use all of the 16 kB space allocated to them. Typically each device’s registers are
"aliased" or repeated at multiple locations within each 16 kB range.
Table 4. AHB peripherals and base addresses
AHB peripheral Address range Peripheral name
0 0x2008 0000 to 0x2008 3FFF General Purpose DMA controller
1 0x2008 4000 to 0x2008 7FFF Ethernet MAC
2 0x2008 8000 to 0x2008 BFFF LCD controller
3 0x2008 C000 to 0x2008 FFFF USB interface
4 0x2009 0000 to 0x2009 3FFF CRC engine
5 0x2009 4000 to 0x2009 7FFF SPIFI
6 0x2009 8000 to 0x2009 BFFF GPIO
7 0x2009 C000 to 0x2009 FFFF External Memory Controller
8 to 15 0x200A 0000 to 0x200B FFFF reserved
Table 5. APB0 peripherals and base addresses
APB0 peripheral Base address Peripheral name
0 0x4000 0000 Watchdog Timer
1 0x4000 4000 Timer 0
2 0x4000 8000 Timer 1
3 0x4000 C000 UART0
4 0x4001 0000 UART1
5 0x4001 4000 PWM0
6 0x4001 8000 PWM1
7 0x4001 C000 I
2
C0
8 0x4002 0000 Comparators
9 0x4002 4000 RTC and Event Monitor/Recorder
10 0x4002 8000 GPIO interrupts
11 0x4002 C000 Pin Connect Block
12 0x4003 0000 SSP1
13 0x4003 4000 ADC
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User manual Rev. 3 — 12 March 2014 18 of 947
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UM10562
Chapter 2: LPC408x/407x Memory map
2.4 Memory re-mapping
The Cortex-M4 incorporates a mechanism that allows remapping the interrupt vector table
to alternate locations in the memory map. This is controlled via the Vector Table Offset
Register contained in the Cortex-M4. Refer to the NVIC description in Section 5.4
and to
the ARM Cortex-M4 User Guide referred to in Section 40.1
.
Boot ROM re-mapping
Following a hardware reset, the Boot ROM is temporarily mapped to address 0. This is
normally transparent to the user. However, if execution is halted immediately after reset by
a debugger, it should correct the mapping for the user. See Section 39.8
.
14 0x4003 8000 CAN Acceptance Filter RAM
15 0x4003 C000 CAN Acceptance Filter Registers
16 0x4004 0000 CAN Common Registers
17 0x4004 4000 CAN Controller 1
18 0x4004 8000 CAN Controller 2
19 to 22 0x4004 C000 to 0x4005 8000 reserved
23 0x4005 C000 I
2
C1
24 to 31 0x4006 0000 to 0x4007 C000 reserved
Table 6. APB1 peripherals and base addresses
APB1 peripheral Base address Peripheral name
0 to 1 0x4008 0000 to 0x4008 4000 reserved
2 0x4008 8000 SSP0
30x4008C000 DAC
4 0x4009 0000 Timer 2
5 0x4009 4000 Timer 3
6 0x4009 8000 UART2
70x4009C000 UART3
8 0x400A 0000 I
2
C2
9 0x400A 4000 UART4
10 0x400A 8000 I
2
S
11 0x400A C000 SSP2
12 to 13 0x400B 0000 to 0x400B 4000 reserved
14 0x400B 8000 Motor control PWM
15 0x400B C000 Quadrature Encoder Interface
16 0x400C 0000 SD card interface
17 to 30 0x400D 0000 to 0x400F 8000 reserved
31 0x400F C000 System control
Table 5. APB0 peripherals and base addresses
APB0 peripheral Base address Peripheral name
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Chapter 2: LPC408x/407x Memory map
2.5 AHB arbitration
The Multilayer AHB Matrix arbitrates between several masters, only if they attempt to
access the same matrix slave port at the same time. By default, the Cortex-M4 D-code
bus has the highest priority, followed by the I-Code bus. All other masters share a lower
priority.
The default priority can be altered by the user if care is taken. This may be particularly
useful if the LCD interface is used and it has difficulty getting sufficient data.
2.5.1 Matrix Arbitration register
The Matrix Arbitration register provides the ability to change the default AHB Matrix
arbitration priorities.
The values used for the various priorities are 3 = highest, 0 = lowest.
An example of a way to give priority to the LCD DMA is to use the value 0x0000 0C09.
The gives the LCD highest priority, D-code second priority, I-Code third priority, and all
others lowest priority.
Where in the memory space code and various types of data are located can be managed
to help minimize the need for arbitration and possible starvation of any of the bus masters,
as well as a need for changing the default priorities. For instance, LCD refresh from
off-chip memory connected to the EMC, while also executing off-chip code via the EMC
can cause a great deal of arbitration.
Table 7. Matrix Arbitration register (MATRIXARB - 0x400F C188) bit description
Bit Symbol Description Reset value
1:0 PRI_ICODE I-Code bus priority. Should be lower than PRI_DCODE for proper operation. 0x1
3:2 PRI_DCODE D-Code bus priority. 0x3
5:4 PRI_SYS System bus priority. 0
7:6 PRI_GPDMA General Purpose DMA controller priority. 0
9:8 PRI_ETH Ethernet DMA priority. 0
11:10 PRI_LCD LCD DMA priority. 0
13:12 PRI_USB USB DMA priority. 0
15:14 - Reserved. Read value is undefined, only zero should be written. NA
16 ROM_LAT ROM latency select. Set to 1 by the boot code. Special notes when operating at
above 60MHz: 1. When connecting the device for debugging, user should set this
bit for proper operation if the debugger bypasses the boot code. 2. If the value of
this register is altered by user code, this bit must not be inadvertently cleared.
1
31:17 - Reserved. Read value is undefined, only zero should be written. NA
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User manual Rev. 3 — 12 March 2014 20 of 947
3.1 Introduction
The system control block includes several system features and control registers for a
number of functions that are not related to specific peripheral devices. These include:
Chip Reset (see Section 3.4)
Peripheral Reset control (see Section 3.5)
Brown-Out Detection (see Section 3.6)
External Interrupt Inputs (see Section 3.7)
Each type of function has its own registers if any are required and unneeded bits are
defined as reserved in order to allow future expansion.
3.1.1 Summary of clocking and power control functions
This section describes the generation of the various clocks needed for device operation,
and options of clock source selection, as well as power control and wake-up from reduced
power modes. Functions described in the following subsections include:
Oscillators (see Section 3.8)
PLLs (see Section 3.10)
Clock selection and dividers (see Section 3.11)
Power control (see Section 3.12)
Wake-up timer (see Section 3.13)
External clock output (see Section 3.14)
UM10562
Chapter 3: LPC408x/407x System and clock control
Rev. 3 — 12 March 2014 User manual
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NXP LPC4078FBD144 User guide

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User guide

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